CN112349673A - 一种基于键合线连接的超薄封装件及其制作工艺 - Google Patents

一种基于键合线连接的超薄封装件及其制作工艺 Download PDF

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CN112349673A
CN112349673A CN202011244476.1A CN202011244476A CN112349673A CN 112349673 A CN112349673 A CN 112349673A CN 202011244476 A CN202011244476 A CN 202011244476A CN 112349673 A CN112349673 A CN 112349673A
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肖国庆
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Jiangxi Star Core Microelectronics Co ltd
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Abstract

本发明提供了一种基于键合线连接的超薄封装件及其制作工艺,封装件包括:引线框架、芯片、塑封体、镀银层、镀NiPdAu层、铜倒角连接层和键合线;镀银层为相互独立的镀银层段,部分镀银层上具有芯片;芯片和未设置芯片的部分镀银层通过键合线连接;塑封体包围了芯片、镀银层、镀NiPdAu层、铜倒角连接层和键合线;芯片、镀银层、镀NiPdAu层、铜倒角连接层和键合线构成了电路的电源和信号通道。在图形镀银层和框架基板之间增加一层铜倒角互连层,塑封之后形成有效的防拖拉结构,极大地降低了框架在腐蚀变薄后,在模具内滑动的风险,同时降低了塑封料压力,增加了塑封料与金属框架的接合面积,封装可靠性大幅提升。

Description

一种基于键合线连接的超薄封装件及其制作工艺
技术领域
本发明属于集成电路封装技术领域,具体涉及一种基于键合线连接的超薄封装件及其制作工艺。
背景技术
集成电路扁平无引脚封装(QFN/DFN),在近几年随着通讯设备(如基站、交换机)、智能手机、便携式设备(如平板电脑)、可穿戴设备(如智能手表、智能眼镜、智能手环等)的普及而迅速发展,特别适用于有高频、高带宽、低噪声、高导热、小体积、高速度等电性需求的大规模集成电路的封装。集成电路扁平无引脚封装(QFN/DFN)有效地利用了引线脚的封装空间,从而大幅度地提高了封装效率。该封装由于引线短小、塑封体尺寸小、封装体薄,可以使CPU体积缩小30%-50%。所以它能提供卓越的电性能,同时还提供了出色的散热性能。
传统的集成电路扁平无引脚封装封装(QFN/DFN)主要存在以下不足:框架载体的QFN/DFN封装产品需要根据芯片尺寸及电路连通需求设计框架图形,再用腐蚀等方法将框架加工成设计好的图形,设计及制作周期长,成本比较高。并且目前的QFN/DFN封装系列封装件在凸点的排布以及I/O的密集程度上也由于框架设计及框架制造工艺而有所限制。同时,由于框架在腐蚀变薄后,在模具内有滑动的风险,封装可靠性得不到保障。还有就是传统的QFN/DFN产品厚度仍然比较大,无法满足当前的便携式设备对小体积、高密度封装的需求。
发明内容
为了克服上述现有技术存在的问题,本发明提供了一种基于键合线连接的免贴膜、免电镀的超薄封装件及其制作工艺。本发明通过电镀银之后在植有的金属凸点上直接压焊,也可通过电镀银后直接打线的方法实现与外部电路的连通;引线框架图形的设计在框架制作时期就可以完成,缩短了制作周期,更好地实现芯片与载体的互联,使I/O更加密集,成本更低;同时,在图形镀银层和框架基板之间增加一层铜倒角互连层,塑封之后形成有效的防拖拉结构,极大地降低了框架在腐蚀变薄后,在模具内滑动的风险,同时降低了塑封料压力,增加了塑封料与金属框架的接合面积,封装可靠性大幅提升。
为达此目的,本发明采用以下技术方案:
一种基于键合线连接的超薄封装件,所述封装件包括:
引线框架、芯片、塑封体、镀银层、镀NiPdAu层、铜倒角连接层和键合线;
所述镀银层为相互独立的镀银层段,部分所述镀银层上具有所述芯片;
所述芯片和未设置所述芯片的部分所述镀银层通过所述键合线连接;
所述塑封体包围了所述芯片、所述镀银层、所述镀NiPdAu层、所述铜倒角连接层和所述键合线;
所述芯片、所述所述镀银层、所述镀NiPdAu层、所述铜倒角连接层和所述键合线构成了电路的电源和信号通道。
本实施例中,所述封装件还包括:
金属凸点,部分所述镀银层上具有所述金属凸点,所述芯片和所述金属凸点通过所述键合线连接;
所述塑封体包围了所述金属凸点、所述芯片、所述镀银层、所述镀NiPdAu层、所述铜倒角连接层和所述键合线;
所述金属凸点、所述芯片、所述镀银层、所述镀NiPdAu层、所述铜倒角连接层和所述键合线共同构成电路的电源和信号通道。
本发明还公开了一种基于键合线连接的超薄封装件的制作工艺,具体按照以
下步骤进行:
步骤1,引线框架形成镀NiPdAu层:在所述引线框架的预设区域形成所述NiPdAu层;所述NiPdAu层的厚度为3um~5um;
步骤2,生长铜倒角连接层:在所述NiPdAu层预设区域内形成所述铜倒角连接层;所述铜倒角连接层的厚度为50um~100um,并并腐蚀倒凸结构;
步骤3,铜倒角层连接镀银:在所述铜倒角连接层上形成所述镀银层;所述镀银层的厚度为3um~5um;
步骤4,进行减薄处理,减薄厚度为50μm~200μm,并控制表面粗糙度为Ra0.10mm~0.05mm;
步骤5,采用划片机进行划片;
步骤6,上芯,将所述芯片通过所述镀银层与所述引线框架相连通;
步骤7,制作所述金属凸点,在所述镀银层的无芯片部分制作所述金属凸点,然后在所述芯片焊区将所述键合线连接在所述金属凸点上;
步骤8,塑封:对整体进行塑封,塑封料填充满所述铜倒角连接层的凹槽,形成有效的防拖拉结构,确保封装可靠性;
步骤9,用化学溶液腐蚀掉全部所述引线框架,并露出所述NiPdAu层;
步骤10,将步骤9形成的封装件进行切割、包装。
本实施例中,所述芯片和未设置所述芯片的部分所述镀银层通过所述键合线通过压焊连接。
本实施例中,所述铜倒角连接层的材质为A194。
本发明的有益效果为:
本发明提供的一种基于键合线连接的超薄封装件,包括引线框架、芯片、塑封体、镀银层、镀NiPdAu层、铜倒角连接层和键合线;镀银层为相互独立的镀银层段,部分镀银层上具有芯片;芯片和未设置芯片的部分镀银层通过键合线连接;塑封体包围了芯片、镀银层、镀NiPdAu层、铜倒角连接层和键合线;芯片、镀银层、镀NiPdAu层、铜倒角连接层和键合线构成了电路的电源和信号通道。通过上述设置,使得本发明具备以下技术效果:
(1)本发明采用普通框架即可进行产品制作流程,无需过多加工框架载体,缩短设计周期,降低成本。
(2)镀银层和镀NiPdAu层厚度仅3um~5um,大大降低了QFN/DFN封装产品的厚度(可控制在0.35mm以内),而传统的QFN/DFN封装体厚度在0.7mm以上。本发明提供的技术可使封装体厚度减小100%。
(3)本发明通过电镀银之后在植有的金属凸点上直接压焊,也可通过电镀银后直接打线的方法实现与外部电路的连通。
(4)在图形镀银层和框架基板之间增加一层铜倒角互连层,塑封之后形成有效的防拖拉结构,极大地降低了框架在腐蚀变薄后,在模具内滑动的风险;同时,降低了塑封料压力,增加了塑封料与金属框架的接合面积,封装可靠性大幅提升。
(5)本发明提供的封装件将镀NiPdAu层作为与外部电路的信号连接通道,相当于普通封装的“管脚”,可以省去电镀环节。
(6)传统的QFN/DFN框架,为了防止塑封时发生“溢胶”,在框架背面贴有一层膜;而本发明由于框架上面镀了一层NiPdAu,可以起到隔离塑封料的作用,塑封后腐蚀掉框架,同样可以起到防止“溢胶”的作用,这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件可以免电镀、免贴膜,生产成本可以大幅降低,产品更有竞争力。
附图说明
图1为引线框架剖面图;
图2为引线框架镀NiPdAu后剖面图;
图3为引线框架的镀NiPdAu层上生长铜层(A194)并腐蚀出倒角后的剖面图;
图4为铜倒角连接层上镀银后的剖面图;
图5为产品上芯后剖面图;
图6为框架植金属凸点后剖面图;
图7为产品压焊后剖面图;
图8为产品塑封后剖面图;
图9为产品腐蚀框架后剖面图;
图10为产品成品剖面图;
图11为产品无金属凸点压焊后剖面图;
图12为产品无金属凸点塑封后剖面图;
图13为产品无金属凸点腐蚀框架后剖面图;
图14为产品无金属凸点成品剖面图。
图中:
1、引线框架;2、金属凸点;3、芯片;4、塑封体;5、镀银层;6、镀NiPdAu层;7、铜倒角连接层;8、键合线。
具体实施方式
下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。
如图1-14所示,一种基于键合线连接的超薄封装件,封装件包括:
引线框架1、芯片3、塑封体4、镀银层5、镀NiPdAu层6、铜倒角连接层7和键合线8;
镀银层5为相互独立的镀银层段,部分镀银层5上具有芯片3;
芯片3和未设置芯片3的部分镀银层5通过键合线8连接;
塑封体4包围了芯片3、镀银层5、镀NiPdAu层6、铜倒角连接层7和键合线8;
芯片3、镀银层5、镀NiPdAu层6、铜倒角连接层7和键合线8构成了电路的电源和信号通道。
进一步地,封装件还包括:
金属凸点2,部分镀银层5上具有金属凸点2,芯片3和金属凸点2通过键合线8连接;
塑封体4包围了金属凸点2、芯片3、镀银层5、镀NiPdAu层6、铜倒角连接层7和键合线8;
金属凸点2、芯片3、镀银层5、镀NiPdAu层6、铜倒角连接层7和键合线8共同构成电路的电源和信号通道。
本实施例还提供了一种基于键合线连接的超薄封装件的制作工艺,具体按照
以下步骤进行:
步骤1,引线框架1形成镀NiPdAu层6:在引线框架1的预设区域形成NiPdAu层6;NiPdAu层6的厚度为3um~5um;
步骤2,生长铜倒角连接层7:在NiPdAu层6预设区域内形成铜倒角连接层7;铜倒角连接层7的厚度为50um~100um,并并腐蚀倒凸结构;
步骤3,铜倒角层连接镀银:在铜倒角连接层7上形成镀银层5;镀银层5的厚度为3um~5um;
步骤4,进行减薄处理,减薄厚度为50μm~200μm,并控制表面粗糙度为Ra0.10mm~0.05mm;
步骤5,采用划片机进行划片;
步骤6,上芯,将芯片3通过镀银层5与引线框架1相连通;
步骤7,制作金属凸点2,在镀银层5的无芯片部分制作金属凸点2,然后在芯片3焊区将键合线8连接在金属凸点2上;
步骤8,塑封:对整体进行塑封,塑封料填充满铜倒角连接层7的凹槽,形成有效的防拖拉结构,确保封装可靠性;
步骤9,用化学溶液腐蚀掉全部引线框架1,并露出NiPdAu层6;
步骤10,将步骤9形成的封装件进行切割、包装。
进一步地,芯片3和未设置芯片3的部分镀银层5通过键合线8通过压焊连接。
进一步地,铜倒角连接层7的材质为A194。
以上实施,具体来说,传统的QFN/DFN工艺流程为:框架镀银→晶圆减薄
→划片→上芯→做金属凸点→压焊→塑封→腐蚀框架→电镀→切割→包装。
本实施例的一种基于键合线连接的超薄封装件的工艺流程如下:框架镀NiPdAu→生长铜倒角连接层(通过腐蚀,在铜层和镀NiPdAu层之间形成如附图3所示的倒角凹槽)→铜倒角连接层上镀银→晶圆减薄→划片→上芯→做金属凸点→压焊→塑封→腐蚀框架→切割→包装;其中做金属凸点的流程可省略。
更为具体来说,如图1至图14所示,本实施例的一种基于键合线连接的超
薄封装件的制作工艺,具体按照以下步骤进行:
步骤1,引线框架1形成镀NiPdAu层6:在引线框架1的预设区域形成NiPdAu层6;NiPdAu层6的厚度为3um~5um;
步骤2,生长铜倒角连接层7:在NiPdAu层6预设区域内形成铜倒角连接层7;铜倒角连接层7的厚度为50um~100um,并并腐蚀倒凸结构;
步骤3,铜倒角层连接镀银:在铜倒角连接层7上形成镀银层5;镀银层5的厚度为3um~5um;具体底,在框架制作厂家制作过程中,先设计好框架的图形,然后镀银层5形成图形。采用普通框架,在完成步骤1和步骤2之后再镀银即可进行产品制作流程,无需过多加工框架载体,即可实现电路连通,缩短设计及制作周期,节约成本。
步骤4,进行减薄处理,减薄厚度为50μm~200μm,并控制表面粗糙度为Ra 0.10mm~0.05mm;
步骤5,采用划片机进行划片;针对划片工艺,具体地,针对厚度在150μm以上晶圆同普通集成电路扁平封装件划片工艺,但厚度在150μm以下晶圆,使用双刀划片机及其工艺。
步骤6,上芯,将芯片3通过镀银层5与引线框架1相连通;
步骤7,制作金属凸点2,在镀银层5的无芯片部分制作金属凸点2,然后在芯片3焊区将键合线8连接在金属凸点2上;
步骤8,塑封:对整体进行塑封,塑封料填充满铜倒角连接层7的凹槽,形成有效的防拖拉结构,确保封装可靠性;同现有技术已知的方法;此处不在累述。
步骤9,用化学溶液腐蚀掉全部引线框架1,并露出NiPdAu层6;此方法可缩短设计及制作周期,降低成本。
步骤10,将步骤9形成的封装件进行切割、包装。同现有技术已知的方法;此处不在累述。
另外,在凸点排布及I/O数不受框架设计及制作限制的前提下,本发明通过电镀银之后在植有的金属凸点上直接压焊,也可通过电镀银后直接打线的方法实现与外部电路的连通。引线框架图形的设计在框架制作时期就可以完成,缩短了制作周期,更好地实现芯片与载体的互联,使I/O更加密集,成本更低。同时,增加了一层3um~5um的NiPdAu层,使生产时免电镀;增加了一层铜(A194)倒角连接层,塑封之后,塑封料填充满铜倒角层的凹槽,形成有效的防拖拉结构,同时降低了塑封料压力,增加了塑封料与金属框架的接合面积,提高了封装的可靠性。
本发明提供的封装件将镀NiPdAu层作为与外部电路的信号连接通道,相当于普通封装的“管脚”,可以省去电镀环节。传统的QFN/DFN框架,为了防止塑封时发生“溢胶”,在框架背面贴有一层膜;而本发明由于框架上面镀了一层NiPdAu,可以起到隔离塑封料的作用,塑封后腐蚀掉框架,同样可以起到防止“溢胶”的作用,这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件免电镀、免贴膜,生产成本可以大幅降低,产品更有竞争力。
本发明是通过优选实施例进行描述的,本领域技术人员知悉,在不脱离本发明的精神和范围的情况下,可以对这些特征和实施例进行各种改变或等效替换。本发明不受此处所公开的具体实施例的限制,其他落入本申请的权利要求内的实施例都属于本发明保护的范围。

Claims (5)

1.一种基于键合线连接的超薄封装件,其特征在于:所述封装件包括:
引线框架(1)、芯片(3)、塑封体(4)、镀银层(5)、镀NiPdAu层(6)、铜倒角连接层(7)和键合线(8);
所述镀银层(5)为相互独立的镀银层段,部分所述镀银层(5)上具有所述芯片(3);
所述芯片(3)和未设置所述芯片(3)的部分所述镀银层(5)通过所述键合线(8)连接;
所述塑封体(4)包围了所述芯片(3)、所述镀银层(5)、所述镀NiPdAu层(6)、所述铜倒角连接层(7)和所述键合线(8);
所述芯片(3)、所述所述镀银层(5)、所述镀NiPdAu层(6)、所述铜倒角连接层(7)和所述键合线(8)构成了电路的电源和信号通道。
2.如权利要求1所述的一种基于键合线连接的超薄封装件,其特征在于:
所述封装件还包括:
金属凸点(2),部分所述镀银层(5)上具有所述金属凸点(2),所述芯片(3)和所述金属凸点(2)通过所述键合线(8)连接;
所述塑封体(4)包围了所述金属凸点(2)、所述芯片(3)、所述镀银层(5)、所述镀NiPdAu层(6)、所述铜倒角连接层(7)和所述键合线(8);
所述金属凸点(2)、所述芯片(3)、所述镀银层(5)、所述镀NiPdAu层(6)、所述铜倒角连接层(7)和所述键合线(8)共同构成电路的电源和信号通道。
3.一种基于键合线连接的超薄封装件的制作工艺,其特征在于:具体按照以下步骤进行:
步骤1,引线框架(1)形成镀NiPdAu层(6):在所述引线框架(1)的预设区域形成所述NiPdAu层(6);所述NiPdAu层(6)的厚度为3um~5um;
步骤2,生长铜倒角连接层(7):在所述NiPdAu层(6)预设区域内形成所述铜倒角连接层(7);所述铜倒角连接层(7)的厚度为50um~100um,并并腐蚀倒凸结构;
步骤3,铜倒角层连接镀银:在所述铜倒角连接层(7)上形成所述镀银层(5);所述镀银层(5)的厚度为3um~5um;
步骤4,进行减薄处理,减薄厚度为50μm~200μm,并控制表面粗糙度为Ra 0.10mm~0.05mm;
步骤5,采用划片机进行划片;
步骤6,上芯,将所述芯片(3)通过所述镀银层(5)与所述引线框架(1)相连通;
步骤7,制作所述金属凸点(2),在所述镀银层(5)的无芯片部分制作所述金属凸点(2),然后在所述芯片(3)焊区将所述键合线(8)连接在所述金属凸点(2)上;
步骤8,塑封:对整体进行塑封,塑封料填充满所述铜倒角连接层(7)的凹槽,形成有效的防拖拉结构,确保封装可靠性;
步骤9,用化学溶液腐蚀掉全部所述引线框架(1),并露出所述NiPdAu层(6);
步骤10,将步骤9形成的封装件进行切割、包装。
4.如权利要3所述的一种基于键合线连接的超薄封装件的制作工艺,其特征在于:
所述芯片(3)和未设置所述芯片(3)的部分所述镀银层(5)通过所述键合线(8)通过压焊连接。
5.如权利要3所述的一种基于键合线连接的超薄封装件的制作工艺,其特征在于:
所述铜倒角连接层(7)的材质为A194。
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