CN105514079A - 集成电路封装结构及其生产工艺 - Google Patents

集成电路封装结构及其生产工艺 Download PDF

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CN105514079A
CN105514079A CN201510895527.XA CN201510895527A CN105514079A CN 105514079 A CN105514079 A CN 105514079A CN 201510895527 A CN201510895527 A CN 201510895527A CN 105514079 A CN105514079 A CN 105514079A
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silver coating
chip
silver
nickel plating
plating layer
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刘兴波
梁大钟
宋波
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Guangdong Style Science And Technology Ltd
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Abstract

本发明提供了一种基于键合线连接的免贴膜、免电镀的集成电路封装结构及其生产工艺，集成电路封装结构，包括有镀银层，所述镀银层为相互独立的镀银层段，还包括有设于部分镀银层段上的芯片，各部分镀银层段通过键合线连接，所述芯片、镀银层、镀镍钯金层和键合线外周设有塑封体，芯片、镀银层、镀镍钯金层和键合线构成了芯片的电源和信号通道。本发明同时提供了上述集成电路封装的生产工艺，由于本发明提供的封装件可以免电镀、免贴膜，生产成本可以大幅降低，产品更有竞争力。适用于集成电路封装中应用。

Description

集成电路封装结构及其生产工艺
技术领域
本发明属于集成电路封装技术领域，更具体的说，涉及一种基于键合线连接的免贴膜、免电镀的生产工艺。
背景技术
集成电路扁平无引脚封装（QFN/DFN），在近几年随着通讯设备(如基站、交换机)、智能手机、便携式设备(如平板电脑)、可穿戴设备(如智能手表、智能眼镜、智能手环等)的普及而迅速发展，特别适用于有高频、高带宽、低噪声、高导热、小体积、高速度等电性需求的大规模集成电路的封装。集成电路扁平无引脚封装(QFN/DFN)有效地利用了引线脚的封装空间，从而大幅度地提高了封装效率。该封装由于引线短小、塑封体尺寸小、封装体薄，可以使CPU体积缩小30%-50%，同时具有良好的散热性能。传统的QFN/DFN工艺流程为：框架镀银→晶圆减薄→划片→上芯→做金属凸点→压焊→塑封→腐蚀框架→电镀→切割→包装。传统的集成电路扁平无引脚封装封装（QFN/DFN）主要存在以下不足：一是设计及制作周期长，成本比较高；二是凸点的排布以及I/O的密集程度受到框架设计及框架制造工艺的限制；三是框架在腐蚀变薄后，在模具内有滑动的风险，封装可靠性得不到保障；四是传统的QFN/DFN产品厚度仍然比较大，无法满足当前的便携式设备对小体积、高密度封装的需求。
发明内容
为了克服传统QFN工艺存在QFN/DFN产品厚度仍然比较大，无法满足当前的便携式设备对小体积、高密度封装的需求的不足，本发明提供了一种基于键合线连接的免贴膜、免电镀的集成电路封装结构及其生产工艺
为实现以上技术目的，本发明的技术方案是：
集成电路封装结构，包括有镀银层，所述镀银层为相互独立的镀银层段，还包括有设于部分镀银层段上的芯片，各部分镀银层段通过键合线连接，所述芯片、镀银层、镀镍钯金层和键合线外周设有塑封体，芯片、镀银层、镀镍钯金层和键合线构成了芯片的电源和信号通道。
集成电路封装的生产工艺，包括有如下步骤
a.在引线框架上镀镍钯金
b.生长倒角镀银层，通过腐蚀，使镀镍钯金层之上的镀银层形成倒角凹槽
c.晶圆减薄；
d.划片；
e.将芯片放置于引线框架上；
f.在引线框架上设置有金属凸点；
g.对键合线进行压焊；
h.将述芯片、镀银层、镀镍钯金层和键合线塑封于塑封体中；
并对塑封完成后的产品进行腐蚀框架、切割及包装。
本发明的技术效果是：做金属凸点的流程可省略，明通过电镀银之后在植有的金属凸点上直接压焊，也可通过电镀银后直接打线的方法实现与外部电路的连通。引线框架图形的设计在框架制作时期就可以完成，缩短了制作周期，更好地实现芯片与载体的互联，使I/O更加密集，成本更低。同时，在镀镍钯金层上有一层倒角镀银层，塑封之后形成有效的防拖拉结构，极大地降低了框架在腐蚀变薄后，在模具内滑动的风险，同时降低了塑封料压力，增加了塑封料与金属框架的接合面积，封装可靠性大幅提升。本发明采用普通框架即可进行产品制作流程，无需过多加工框架载体，缩短设计周期，降低成本。镀镍钯金层厚度仅1um，大大降低了QFN/DFN封装产品的厚度(可控制在0.35mm以内)，而传统的QFN/DFN封装体厚度在0.7mm以上。本发明提供的技术可使封装体厚度减小100%。本发明通过电镀银之后在植有的金属凸点上直接压焊，也可通过电镀银后直接打线的方法实现与外部电路的连通。在镀镍钯金层上有一层倒角镀银层，塑封之后形成有效的防拖拉结构，极大地降低了框架在腐蚀变薄后，在模具内滑动的风险；同时，降低了塑封料压力，增加了塑封料与金属框架的接合面积，封装可靠性大幅提升。本发明提供的封装件将镀镍钯金层作为与外部电路的信号连接通道，相当于普通封装的“管脚”，可以省去电镀环节。传统的QFN/DFN框架，为了防止塑封时发生“溢胶”，要在框架背面贴有一层膜；而本发明由于框架上面镀了一层镍钯金，可以起到隔离塑封料的作用，塑封后腐蚀掉框架，同样可以起到防止“溢胶”的作用，这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件可以免电镀、免贴膜，生产成本可以大幅降低，产品更有竞争力。
附图说明
图1为引线框架剖面图；
图2为引线框架镀镍钯金后剖面图；
图3为引线框架的镀镍钯金层上镀银并腐蚀出倒角后的剖面图；
图4为产品上芯后剖面图；
图5为植完金属凸点后剖面图；
图6为产品压焊后剖面图；
图7为产品塑封后剖面图；
图8为产品腐蚀框架后剖面图；
图9为产品成品剖面图；
图10为产品无金属凸点压焊后剖面图；
图11为产品无金属凸点塑封后剖面图；
图12为产品无金属凸点腐蚀框架后剖面图；
图13为产品无金属凸点成品剖面图。
图中，1为引线框架、2为金属凸点、3为芯片、4为塑封体、5为倒角镀银层、6为镀镍钯金层、7为键合线。
具体实施方式
如图9所示，一种基于键合线连接的免贴膜、免电镀的封装件还包括有金属凸点2。所述倒角镀银层5为相互独立的镀银层段，部分倒角镀银层5上有芯片3，部分倒角镀银层5上有金属凸点2，所述芯片3和金属凸点2通过键合线7连接，塑封体4包围了金属凸点2、芯片3、倒角镀银层5、镀镍钯金层6和键合线7，金属凸点2、芯片3、倒角镀银层5、镀镍钯金层6和键合线7构成了电路的电源和信号通道。如图13所示，一种基于键合线连接的免贴膜、免电镀的封装件也可以不做金属凸点，直接将键合线打到框架的焊盘上（倒角镀银层5）。一种基于键合线连接的免贴膜、免电镀的封装件的工艺流程如下：框架镀镍钯金→生长倒角镀银层（通过腐蚀，使镀镍钯金层之上的镀银层形成如附图3所示的倒角凹槽）→晶圆减薄→划片→上芯→做金属凸点→压焊→塑封→腐蚀框架→切割→包装。在实施中，所述做金属凸点的流程可省略。
如图1至图9所示，一种基于键合线连接的免贴膜、免电镀的封装件的制作工艺，按照以下步骤进行：
1)框架镀镍钯金：在引线框架1的图形部分镀一层1um的镍钯金层6；
2)镍钯金层镀银：在镍钯金层6上镀一层20~30um的银层5，并腐蚀出倒角形状；
3)晶圆减薄：减薄厚度50um～200um，粗糙度Ra0.10mm～0.05mm；
4)划片：150um以上晶圆同普通集成电路扁平封装件划片工艺，但厚度在150um以下晶圆，使用双刀划片机及其工艺；
5)上芯：芯片3通过倒角镀银层5和引线框架1连通；
6)做金属凸点，压焊：在倒角镀银层5的无芯片部分做金属凸点2，然后在芯片3焊区直接打键合线7到金属凸点2上；
7)塑封：同常规方法，塑封料填充满倒角镀银层的凹槽，形成有效的防拖拉结构，极大地提高了封装可靠性；
8)框架腐蚀：用化学溶液腐蚀掉全部引线框架1，露出镀镍钯金层6；
9)切割、包装同常规方法。
在凸点排布及I/O数不受框架设计及制作限制的前提下，本发明通过电镀银之后在植有的金属凸点上直接压焊，也可通过电镀银后直接打线的方法实现与外部电路的连通。引线框架图形的设计在框架制作时期就可以完成，缩短了制作周期，更好地实现芯片与载体的互联，使I/O更加密集，成本更低。同时，增加了一层1um的镍钯金层，使生产时免电镀；在镀镍钯金层上有一层倒角镀银层，塑封之后，塑封料填充满倒角镀银层的凹槽，形成有效的防拖拉结构，同时降低了塑封料压力，增加了塑封料与金属框架的接合面积，提高了封装的可靠性。
本发明提供的封装件将镀镍钯金层作为与外部电路的信号连接通道，相当于普通封装的“管脚”，可以省去电镀环节。传统的QFN/DFN框架，为了防止塑封时发生“溢胶”，要在框架背面贴有一层膜；而本发明由于框架上面镀了一层镍钯金，可以起到隔离塑封料的作用，塑封后腐蚀掉框架，同样可以起到防止“溢胶”的作用，这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件免电镀、免贴膜，生产成本可以大幅降低，产品更有竞争力。

Claims (2)

1.集成电路封装结构，其特征是：包括有镀银层，所述镀银层为相互独立的镀银层段，还包括有设于部分镀银层段上的芯片，各部分镀银层段通过键合线连接，所述芯片、镀银层、镀镍钯金层和键合线外周设有塑封体，芯片、镀银层、镀镍钯金层和键合线构成了芯片的电源和信号通道。
2.集成电路封装的生产工艺，其特征是：包括有如下步骤
a.在引线框架上镀镍钯金
b.生长倒角镀银层，通过腐蚀，使镀镍钯金层之上的镀银层形成倒角凹槽
c.晶圆减薄；
d.划片；
e.将芯片放置于引线框架上；
f.在引线框架上设置有金属凸点；
g.对键合线进行压焊；
h.将述芯片、镀银层、镀镍钯金层和键合线塑封于塑封体中。
CN201510895527.XA 2015-12-08 2015-12-08 集成电路封装结构及其生产工艺 Pending CN105514079A (zh)

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CN110600382A (zh) * 2018-06-12 2019-12-20 深圳市环基实业有限公司 一种芯片封装工艺及产品
CN112349673A (zh) * 2020-11-10 2021-02-09 江西芯世达微电子有限公司 一种基于键合线连接的超薄封装件及其制作工艺
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CN110600382A (zh) * 2018-06-12 2019-12-20 深圳市环基实业有限公司 一种芯片封装工艺及产品
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CN116995054A (zh) * 2023-07-13 2023-11-03 日月新半导体(昆山)有限公司 集成电路封装产品以及集成电路封装方法
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