CN105531805B - 电子器件搭载基板及其制造方法 - Google Patents

电子器件搭载基板及其制造方法 Download PDF

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Publication number
CN105531805B
CN105531805B CN201480049462.0A CN201480049462A CN105531805B CN 105531805 B CN105531805 B CN 105531805B CN 201480049462 A CN201480049462 A CN 201480049462A CN 105531805 B CN105531805 B CN 105531805B
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electronic device
silver
face
metallic plate
copper
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CN105531805A (zh
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砂地直也
小山内英世
栗田哲
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Dowa Metaltech Co Ltd
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Dowa Metaltech Co Ltd
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    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4924—Bases or plates or solder therefor characterised by the materials
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    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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Abstract

由铜或(在表面形成镀铜皮膜20的情况下)铝、或者铝合金形成的金属板10的一侧的主面上搭载有电子器件14的电子元件搭载基板的制造方法中，实施将金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)粗糙化为表面粗糙度为0.4μm以上的表面加工，在其主面(或镀铜皮膜20的表面)上涂布银糊料设置电子器件14后，将银糊料中的银烧结而形成银接合层12，通过该银接合层12将电子器件14接合在金属板10的一侧的主面(或镀铜皮膜20的表面)上。

Description

电子器件搭载基板及其制造方法
技术领域
本发明涉及电子器件搭载基板及其制造方法，特别涉及铜板或铜镀覆板的一侧的面接合在陶瓷基板上的金属-陶瓷接合基板的金属板的另一侧的面上安装有半导体芯片等电子器件的电子器件搭载基板及其制造方法。
背景技术
以往，为了控制电动汽车、电车、工作机械等的大电流，使用功率模块。以往的功率模块中，将金属-陶瓷绝缘基板固定至称为底板的金属板或复合材料的一个面，并通过锡焊将半导体芯片固定在该金属-陶瓷绝缘基板的金属板上。
近年来，提出了将包含银微粒的银糊料作为接合材料使用，使接合材料介于铜板等被接合物间，在被接合物间施加压力的同时以规定时间加热，使接合材料中的银烧结，将被接合物彼此接合的技术方案(例如，参照日本专利特开2011-80147号公报)，尝试了使用这种包含银微粒的银糊料形成的接合材料替代焊锡，在金属-陶瓷绝缘基板的金属板上固定半导体芯片等电子器件。
作为这种在基板上固定电子器件的方法，提出了使在半导体元件的端子和基板的电极之间低温烧结的Ag纳米粒子介于其间，将Ag纳米粒子烧结，使半导体元件的端子与基板的电极接合的方法(例如，参照日本专利特开2007-208082号公报)。
另外，提出了使Ag纳米粒子分散于有机类溶剂中的金属糊料介于半导体元件的Ag部分和陶瓷绝缘基板上的Cu电路板之间，加热进行接合的方法(例如，参照日本专利特开2006-202586号公报)。该方法中，Cu电路板在与半导体元件的Ag部分接合的Cu电路板的表面形成凹陷部分，有利于大面积的接合。
但是，日本专利特开2011-80147号公报、日本专利特开2007-208082号公报以及日本专利特开2006-202586号公报的方法中，使用铜板或(铝板上实施了镀铜的)铜镀覆板作为(电子器件搭载用)金属板，利用银糊料形成的接合材料在金属板上接合半导体芯片等电子器件的情况下，无法以接合缺陷少的状态进行接合，接合后若施加加热循环，则无法保持良好的接合状态。
发明内容
因此，本发明鉴于上述以往的问题点，目的在于提供在铜板或铜镀覆板上以接合缺陷少的状态接合电子器件、施加加热循环之后也能保持良好的接合状态、耐热冲击性良好的电子器件搭载基板及其制造方法。
本发明者为解决上述课题进行了认真研究，结果发现铜板或铜镀覆板的一侧的面上搭载有电子器件的电子器件搭载基板的制造方法中，实施使铜板或铜镀覆板的一侧的面的表面粗糙度为0.4μm以上的表面加工，在该面上涂布银糊料而设置电子器件之后，将银糊料中的银烧结而形成银接合层，通过该银接合层将电子器件接合在铜板或铜镀覆板的一侧的面上，在铜板或铜镀覆板上以接合缺陷少的状态接合电子器件，施加加热循环之后也能保持良好的接合状态，从而完成了本发明。
即，本发明的电子器件搭载基板的制造方法为在铜板或铜镀覆板的一侧的面上搭载有电子器件的电子器件搭载基板的制造方法，其特征是，实施使铜板或铜镀覆板的一侧的面的表面粗糙度为0.4μm以上的表面加工，在该面上涂布银糊料而设置电子器件之后，将银糊料中的银烧结而形成银接合层，通过该银接合层将电子器件接合在铜板或铜镀覆板的一侧的面上。
该电子器件搭载基板的制造方法中，表面加工优选为湿式喷砂处理。另外，实施表面加工后，在涂布银糊料之前，优选将铜板或铜镀覆板退火，优选通过该退火使铜板或铜镀覆板的维氏硬度Hv为40以下。另外，银糊料中银的烧结优选对电子器件加压的同时向铜板或铜镀覆板进行加热。此外，电子器件与铜板或铜镀覆板的一侧的面接合的面，优选使用选自金、银以及钯中的至少一种金属或这些金属的合金进行镀覆。另外，优选使铜板或铜镀覆板的另一个面与陶瓷基板的一侧的面接合，优选使陶瓷基板的另一侧的面与金属底板接合。
另外，本发明的电子器件搭载基板为在铜板或铜镀覆板的一侧的面上搭载有电子器件的电子器件搭载基板，其特征是，铜板或铜镀覆板的一侧的面的表面粗糙度为0.4μm以上，该铜板或铜镀覆板的一侧的面上通过银接合层接合了电子器件。
该电子器件搭载基板上，优选铜板或铜镀覆板的一侧的面的表面粗糙度为0.5～2.0μm。另外，优选铜板或铜镀覆板的一侧的面的维氏硬度Hv为100以下，更优选为40以下。此外，电子器件与铜板或铜镀覆板的一侧的面接合的面，优选使用选自金、银以及钯中的至少一种金属或这些金属的合金进行镀覆。另外，银接合层优选含有银的烧结体。此外，优选使铜板或铜镀覆板的另一侧的面与陶瓷基板的一侧的面接合，优选使陶瓷基板的另一侧的面与金属底板接合。
若利用本发明，则能够提供在铜板或铜镀覆板上以接合缺陷少的状态接合电子器件、施加加热循环之后也能保持良好的接合状态、耐热冲击性良好的电子器件搭载基板及其制造方法。
附图说明
图1是表示本发明的电子器件搭载基板的实施方式的剖视图。
图2是图1的电子器件搭载基材的立体图。
具体实施方式
下面，参照附图，对本发明的电子器件搭载基板及其制造方法的实施方式进行详细说明。
如图1以及图2所示，本发明的电子器件搭载基板的实施方式中，平面形状为大致矩形的(电子器件搭载用)金属板10的一侧的主面上，通过(含有银的烧结体)的银接合层12接合了电子器件14。另外，金属板10的另一侧的主面与平面形状为大致矩形的陶瓷基板16的一侧的主面接合，该陶瓷基板16的另一侧的主面也可与平面形状为大致矩形的散热用金属板(金属底板)18接合。另外，金属板10的一侧的主面上形成镀铜皮膜20，该镀铜皮膜20上也可通过银接合层12与电子器件14接合。
另外，金属板10由铜或(形成镀铜皮膜20的情况下)铝或者铝合金形成，金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)的表面粗糙度为0.4μm以上，优选为0.5～2.0μm。另外，金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)的维氏硬度Hv优选为100以下，更优选为40以下。
另外，电子器件14的金属板10的一侧的主面(接合电子器件14的面)(形成镀铜皮膜20的情况下为镀铜皮膜20的表面)上接合的面，优选使用选自金、银以及钯中的至少一种金属或这些金属的合金一类的能够用银接合层12接合的金属进行覆盖，优选使用选自金、银以及钯中的至少一种金属或这些金属的合金进行镀覆。
本发明的电子器件搭载基板的制造方法的实施方式中，由铜或(形成镀铜皮膜20的情况下)铝或者铝合金形成的金属板10的一侧的主面(或镀铜皮膜20的表面)上搭载有电子器件14的电子器件搭载基板的制造方法中，实施将金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)粗糙化为表面粗糙度为0.4μm以上、优选0.5～2.0μm的表面加工，在其主面(或镀铜皮膜20的表面)上涂布银糊料而设置电子器件14后，将银糊料中的银烧结而形成银接合层12，通过该银接合层12将电子器件14接合在金属板10的一侧的主面(或镀铜皮膜20的表面)上。
另外，实施表面加工后，在涂布银糊料之前，优选将金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)加热处理而退火，优选通过该退火使金属板10(或镀铜皮膜20)的维氏硬度Hv(降低)(软化)为40以下。该退火时的加热温度优选为300～650℃，更优选为350～450℃。另外，该退火时的加热时间优选为15～90分钟，更优选为30～60分钟。
另外，银糊料中银的烧结优选对电子器件14加压的同时向金属板10(或镀铜皮膜20)进行加热。该烧结时的加热温度优选为200～400℃，更优选为220～300℃。另外，该烧结时的加热时间优选为1～10分钟。另外，该烧结时加压的压力可以是10MPa以下，优选2～10MPa，更优选为3～8MPa。
另外，也可以是金属板10的另一侧的主面与平面形状为大致矩形的陶瓷基板16的一侧的主面接合，该陶瓷基板16的另一侧的主面与平面形状为大致矩形的散热用金属板(金属底板)18接合。这种情况下，也可以是金属板10和陶瓷基板16之间以及陶瓷基板16和金属底板18之间接合后，实施金属板10的一侧的主面(或镀铜皮膜20的表面)(接合电子器件14的面)的表面加工，在其主面(或镀铜皮膜20的表面)上涂布银糊料而配置电子器件14后，将银糊料中的银烧结而形成银接合层12，通过该银接合层12将电子器件14接合在金属板10的一侧的主面(或镀铜皮膜20的表面)上。
另外，金属板10由铜板形成的情况下，金属板10和陶瓷基板16之间以及陶瓷基板16和金属底板18之间既可直接接合，也可通过焊材进行接合。这些情况下，也可在金属板10和陶瓷基板16间(以及陶瓷基板16和金属底板18间)的接合之前，对金属板10的一侧的主面(或镀铜皮膜20的表面)进行表面加工。这种情况下，表面加工后即便不通过加热处理进行退火，接合时通过加热金属板10(或镀铜皮膜20)，也能够使金属板10(或镀铜皮膜20)的维氏硬度Hv(降低)(软化)为40以下。
另外，金属板10由铝或铝合金形成的情况下，金属板10和陶瓷基板16之间以及陶瓷基板16和金属底板18之间的接合中，优选在铸造模具(图中未示出)中设置陶瓷基板16后，以与陶瓷基板16的两个主面接触的方式将铝或铝合金的熔液注入，之后通过使熔液冷却固化，在陶瓷基板16的各主面上形成金属板10以及金属底板18而直接接合。
另外，表面加工优选通过(将液体中含有微粒的研磨材料的浆料喷射于金属板表面的湿式喷砂处理等)喷砂处理、(通过作为磨粒的磨削剂在磨削盘上设置金属板，向金属板施加压力使之滑动而研磨)磨削加工进行。
此外，作为银糊料，可使用含有能在400℃以下的温度烧结的银微粒的糊料，优选使用将被山梨酸等碳数8以下(优选6～8)的有机化合物覆盖的一次粒子平均粒径为1～200nm的银微粒分散于分散介质(优选极性溶剂)的接合材料(例如同和电子科技株式会社(DOWAエレクトロニクス株式会社)制的PA-HT-1503M-C)。也可使用在这种分散有银微粒的分散介质中进一步分散了一次粒子平均粒径(D50径)为0.5～3.0μm的(球状)银微粒的接合材料(例如同和电子科技株式会社制的PA-HT-1001L)。
本发明的电子器件搭载基板的制造方法的实施方式中，即便在银糊料中的银烧结时施加5～7MPa左右的低压力的同时以250～260℃左右的低温进行加热的情况下，也能够在金属板(铜板或铜镀覆板)上以(接合部几乎没有空隙等接合缺陷)足够的接合强度接合电子器件。
另外，本说明书中，“表面粗糙度”是根据JIS B0601(2001年)计算出的算术平均粗糙度Ra。另外，“银粒子的一次粒子平均粒径(D50径)”是指通过激光衍射法测定的银粒子的50％粒径(D50径)(累积50质量％粒径)，“银微粒的一次粒子平均粒径”是指利用透射型电子显微镜照片(TEM图像)的银微粒的一次粒径的平均值。
以下，对本发明的电子器件搭载基板及其制造方法的实施例进行详细说明。
实施例1
首先，准备48mm×57mm×0.25mm的由无氧铜形成的(电子器件搭载用)金属板和(散热用)金属底板。
然后，通过含有作为活性金属的Ti的Ag-Cu系焊材将(电子器件搭载用)金属板的一侧的面与49mm×58mm×0.64mm的AlN形成的陶瓷基板的一侧的主面接合，同时将(散热用)金属底板与该陶瓷基板的另一侧的面接合，制作了金属-陶瓷接合基板。
之后，通过湿式喷砂装置(马科株式会社(マコー株式会社)制的型号NFR-737)实施金属-陶瓷接合基板的(电子器件搭载用)金属板的另一侧的面的表面处理。另外，作为湿式喷砂装置的处理条件，以气压0.20MPa、处理速度0.3m/分、投射距离20mm、投射角度90°的条件，使用了水中含有15体积％的作为磨粒的平均粒径为40μm的氧化铝#320的研磨材料浆料。对于该湿式喷砂处理后的(电子器件搭载用)金属板，使用超深度表面形状测定显微镜(株式会社基恩士(株式会社キーエンス)制的VK-8500)的线粗糙度测定功能，测定与金属板表面的任意100μm×100μm的正方形区域的一边平行的长100μm的任意直线沿线的线粗糙度，从该结果根据JISB0601(2001年)算出表面粗糙度(算术平均粗糙度Ra)，结果为0.81μm。另外，通过显微硬度试验机(赫尔穆特费歇尔公司(ヘルモートフィッシャー社)制的フィッシャースコープHM2000)以300mN/10s的条件测定该金属板的另一侧的面的维氏硬度Hv，结果为97.8。
然后，作为银微粒和银粒子分散于分散介质的银糊料，准备了山梨酸包覆的一次粒子平均粒径为100nm的银微粒(银纳米粒子)的凝集体的干燥粉末和一次粒子平均粒径(D50径)为1.0μm的球状银粒子的粉末(同和电子科技株式会社制的2-1C球状银粉末)以及分散剂同时混合于分散介质的银糊料(同和电子科技株式会社制的PA-HT-1001L)。将该银糊料涂布于上述金属-陶瓷接合基板的(电子器件搭载用)金属板的(表面处理过的)表面的电子器件搭载部分，在其上设置作为电子器件的底面(反面)被金镀覆的(13mm×13mm大小的)Si芯片，在空气中以100℃预加热10分钟后，通过Si橡胶片以7MPa加压的同时以260℃加热2分钟，在(电子器件搭载用)金属板上接合了Si芯片。
对于这样制作的电子器件搭载基板，通过超声波探伤装置(SAT)(日立建机精细技术株式会社(日立建機ファインテック株式会社)制的FineSAT FS100II)观察(电子器件搭载用)金属板和Si芯片的接合部，发现接合部没有剥离，以没有空隙等接合缺陷的方式良好接合。
另外，将制作的电子器件搭载基板于-40℃保持15分钟后，在室温下保持1分钟，之后于175℃保持15分钟后在室温下保持1分钟，进行100次和300次上述加热循环后确认接合状态，发现100次循环后的电子器件搭载基板中(电子器件搭载用)金属板和Si芯片接合良好，而300次循环后的电子器件搭载基板则大致接合良好(虽然发现有少量的空隙等接合缺陷导致的不良状态)。
实施例2
除了将实施了(电子器件搭载用)金属板的表面处理的金属-陶瓷接合基板于作为还原气体气氛的氢气中以370℃加热30分钟进行退火之外，通过与实施例1同样的方法制作了电子器件搭载基板。另外，退火后的(电子器件搭载用)金属板的(表面处理过的)表面的表面粗糙度(算术平均粗糙度Ra)为0.77μm，其(电子器件搭载用)金属板的(表面处理过的)表面的维氏硬度Hv为36.1。
对于这样制作的电子器件搭载基板，通过与实施例1同样的方法观察(电子器件搭载用)金属板和Si芯片的接合部，发现接合部没有剥离，接合良好。
另外，对于制作的电子器件搭载基板，确认与实施例1同样的加热循环后的接合状态，发现100次循环和300次循环后(电子器件搭载用)金属板和Si芯片均接合良好。
比较例1
除了未进行湿式喷砂处理以外，通过与实施例1同样的方法制作了电子器件搭载基板。另外，(电子器件搭载用)金属板的(表面处理过的)表面的表面粗糙度(算术平均粗糙度Ra)为0.09μm，(电子器件搭载用)金属板的维氏硬度Hv为35.4。
对于这样制作的电子器件搭载基板，通过与实施例1同样的方法观察(电子器件搭载用)金属板和Si芯片的接合部，发现接合大致良好(虽然观察到少量的不良状态)。
另外，对于制作的电子器件搭载基板，确认了与实施例1同样的加热循环后的接合状态，发现100次循环后的电子器件搭载基板中大致接合良好(虽然观察到少量的不良状态)，但一部分存在不良状态的接合部并未达到剥离程度，300次循环后的电子器件搭载基板中虽然存在一部分的不良状态，但是接合部并未达到剥离程度。
实施例3
在铸造模具内设置78mm×95mm×0.64mm大小的由AlN形成的陶瓷基板，以与该陶瓷基板的两个主面接触的形式将99.9质量％的铝熔液注入后，通过冷却固化熔液而在陶瓷基板的各主面上形成68mm×85mm×0.2mm大小的(电子器件搭载用)金属板和68mm×85mm×0.2mm大小的(散热用)金属底板，分别与陶瓷基板的主面直接接合。
然后，通过与实施例1同样的湿式喷砂装置进行(电子器件搭载用)金属板的表面处理。另外，作为湿式喷砂装置的处理条件，以气压0.20MPa、处理速度0.3m/分、投射距离30mm、投射角度90°的条件，使用了水中含有15体积％的作为磨粒的平均粒径为40μm的氧化铝#320的研磨材料浆料。对于该湿式喷砂处理后的(电子器件搭载用)金属板，通过与实施例1同样的方法算出表面粗糙度(算术平均粗糙度Ra)，结果为1.6μm。另外，该金属板的维氏硬度Hv为29.1。
接着，对表面处理后的(电子器件搭载用)金属板的表面实施脱脂以及化学研磨，将该脱脂以及化学研磨后的(电子器件搭载用)金属板于25℃的锌置换液(奥野制药工业株式会社(奥野製薬工業株式会社)制的サブスターZN-111)中浸渍30秒进行锌置换，水洗并在室温下于硝酸中浸渍30秒进行酸洗，然后水洗并在与上述相同的锌置换液中浸渍30秒以进行第二次的锌置换，之后水洗，藉此对(电子器件搭载用)金属板实施了双锌酸盐处理(两次锌置换)。
然后，通过将双锌酸盐处理后的(电子器件搭载用)金属板浸渍于非电解镍镀覆液(奥野制药工业株式会社制的トップニコロンTOM-LF)，在(电子器件搭载用)金属板上形成了厚度4～5μm的Ni镀覆层。
然后，通过将形成了Ni镀覆层的(电子器件搭载用)金属板浸渍于非电解铜镀覆液(奥野制药工业株式会社制的AIS-アドカッパーCT)，在(电子器件搭载用)金属板上的Ni镀覆层上形成了厚度0.4～0.5μm的Cu镀覆层。
另外，形成了Cu镀覆层后的(电子器件搭载用)金属板上的Cu镀覆层的表面的表面粗糙度(算术平均粗糙度Ra)为1.6μm，维氏硬度Hv为29.1。
接着，除了接合时的压力为5MPa以外，通过与实施例1同样的方法，在(电子器件搭载用)金属板上的Cu镀覆层上接合了Si芯片。
对于这样制作的电子器件搭载基板，通过与实施例1同样的方法观察(电子器件搭载用)金属板上的Cu镀覆层和Si芯片的接合部，发现接合部没有剥离，接合良好。
另外，将制作的电子器件搭载基板于-40℃保持15分钟后，在室温下保持1分钟，之后于250℃保持5分钟后在室温下保持1分钟，进行100次、300次和1000次上述加热循环后确认接合状态，发现100次循环后、300次循环后、1000次循环后(电子器件搭载用)金属板上的Cu镀覆层和Si芯片均接合良好。
比较例2
除了用抛光研磨替代湿式喷砂处理进行表面处理以外，通过与实施例3同样的方法制作了电子器件搭载基板。另外，(电子器件搭载用)金属板上Cu镀覆层(表面处理过的)表面的表面粗糙度(算术平均粗糙度Ra)为0.15μm，(电子器件搭载用)金属板的维氏硬度Hv为29.1。
对于这样制作的电子器件搭载基板，通过与实施例3同样的方法观察(电子器件搭载用)金属板和Si芯片的接合部，发现接合部没有剥离，接合良好。
另外，对于制作的电子器件搭载基板，确认了与实施例1同样的加热循环后的接合状态，发现100次循环后的电子器件搭载基板中(电子器件搭载用)金属板和Si芯片接合良好，300次循环后的电子器件搭载基板中大致接合良好(虽然观察到少量的不良状态)，但存在一部分不良状态的接合部并未达到剥离程度，1000次循环后的电子器件搭载基板中存在一部分不良状态的接合部并未达到剥离程度。
实施例4
除了在铸造模具内设置34mm×31mm×0.6mm大小的由AlN形成的陶瓷基板，在该陶瓷基板的各主面上形成30mm×27mm×0.4mm大小的(电子器件搭载用)金属板和30mm×27mm×0.4mm大小的(散热用)金属底板以外，通过与实施例3同样的方法在陶瓷基板的各主面上直接接合金属板而制作了金属-陶瓷接合基板之后，实施金属板的表面处理以及双锌酸盐处理，形成了Ni镀覆层以及Cu镀覆层。另外，形成了Cu镀覆层后的(电子器件搭载用)金属板上的Cu镀覆层的表面的表面粗糙度(算术平均粗糙度Ra)为1.5μm，维氏硬度Hv为29.0。
然后，在制作的金属-陶瓷接合基板的(电子器件搭载用)金属板上的Cu镀覆层表面的电子器件搭载部分上涂布与实施例1同样的银糊料，在其上设置作为电子器件的Si芯片(底面(反面)上形成作为基底层的厚度1μm的Ti镀覆层和(其上的)厚度3μm的Ni镀覆层的同时，这些基底层被镀金(7mm×7mm大小的)的Si芯片)，在氮气气氛中以1℃/s的升温速度升温后，以6MPa加压的同时以250℃加热5分钟，在(电子器件搭载用)金属板上的Cu镀覆层上接合了Si芯片。
对于这样制作的电子器件搭载基板，通过超声波探伤装置(SAT)(日立建机精细技术株式会社(日立建機ファインテック株式会社)制的FineSAT FS100II)观察(电子器件搭载用)金属板上的Cu镀覆层和Si芯片的接合部，发现接合部没有剥离，接合良好。另外，通过剪切强度测定仪(RISI公司(ライジ社)制的DAGE200)测定了(电子器件搭载用)金属板和Si芯片的接合部的剪切强度，结果为40MPa以上，接合良好。
另外，对于制作的电子器件搭载基板，通过SAM观察与实施例3同样的加热循环100次循环、500次循环、1000次循环后的接合状态，发现100次循环、500次循环和1000次循环后(电子器件搭载用)金属板上的Cu镀覆层和Si芯片均接合良好。另外，测定与实施例3同样的加热循环100次循环、500次循环和1000次循环后(电子器件搭载用)金属板上的Cu镀覆层和Si芯片的接合部的剪切强度，结果为100次循环和500次循环后的剪切强度为40MPa以上，1000次循环后的剪切强度为29MPa，接合良好。

Claims (5)

1.电子器件搭载基板的制造方法，该方法是在铜板或铜镀覆板的一侧的面上搭载有电子器件的电子器件搭载基板的制造方法，其特征在于，实施使铜板或铜镀覆板的一侧的面的表面粗糙度为0.4μm以上的表面加工，之后对该铜板或铜镀覆板进行退火，在其一侧的面上涂布银糊料而设置电子器件之后，将银糊料中的银烧结而形成银接合层，通过该银接合层将电子器件接合在铜板或铜镀覆板的一侧的面上。
2.如权利要求1所述的电子器件搭载基板的制造方法，其特征在于，利用所述退火使所述铜板或铜镀覆板的维氏硬度Hv为40以下。
3.如权利要求1所述的电子器件搭载基板的制造方法，其特征在于，所述表面加工是湿式喷砂处理。
4.如权利要求1所述的电子器件搭载基板的制造方法，其特征在于，所述铜板或铜镀覆板的另一侧的面与陶瓷基板的一侧的面接合。
5.如权利要求4所述的电子器件搭载基板的制造方法，其特征在于，所述陶瓷基板的另一侧的面与金属底板接合。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3236495B1 (en) * 2014-12-16 2019-09-11 Kyocera Corporation Circuit substrate and electronic device
DE102015102759A1 (de) * 2015-02-26 2016-09-01 Heraeus Deutschland GmbH & Co. KG Leistungselektronik-Modul und Verfahren zur Herstellung eines Leistungselektronik-Moduls
JP6782561B2 (ja) * 2015-07-16 2020-11-11 Ｊｘ金属株式会社 キャリア付銅箔、積層体、積層体の製造方法、プリント配線板の製造方法及び電子機器の製造方法
JP6200042B2 (ja) 2015-08-06 2017-09-20 Ｊｘ金属株式会社 キャリア付銅箔、積層体、プリント配線板の製造方法及び電子機器の製造方法
JP6694059B2 (ja) * 2016-04-26 2020-05-13 京セラ株式会社 パワーモジュール用基板およびパワーモジュール
JP6753721B2 (ja) * 2016-07-29 2020-09-09 Ｄｏｗａメタルテック株式会社 金属−セラミックス回路基板およびその製造方法
CN110476244B (zh) 2017-03-31 2023-11-03 罗姆股份有限公司 功率模块及其制造方法
CN110622301B (zh) * 2017-05-10 2023-06-23 罗姆股份有限公司 功率半导体装置及其制造方法
CN110731129B (zh) * 2017-06-09 2024-01-09 电化株式会社 陶瓷电路基板
JP7207904B2 (ja) * 2017-08-25 2023-01-18 京セラ株式会社 パワーモジュール用基板およびパワーモジュール
KR20200135395A (ko) * 2018-03-23 2020-12-02 미쓰비시 마테리알 가부시키가이샤 전자 부품 실장 모듈의 제조 방법
US11070190B2 (en) 2018-03-27 2021-07-20 Statek Corporation Silver-bonded quartz crystal
JP6991950B2 (ja) * 2018-09-26 2022-01-13 日立Astemo株式会社 パワーモジュール
CN110582166B (zh) * 2019-09-04 2021-09-14 广州陶积电电子科技有限公司 一种dbc与dpc结合的陶瓷板加工方法及陶瓷基板
EP3792962A1 (en) * 2019-09-12 2021-03-17 Infineon Technologies AG Method for monitoring a process of forming a sinterable connection layer by photometric measurements

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1368904A (zh) * 1999-07-09 2002-09-11 希普雷公司 在绝缘基板上形成薄金属层的方法
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
DE102006037198A1 (de) * 2006-08-09 2008-02-14 Waag, Andreas, Dr. Verbindungsschicht mit anisotroper Leitfähigkeit

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01135057A (ja) * 1987-11-20 1989-05-26 Kobe Steel Ltd リードフレーム材料の製造方法
JP3222614B2 (ja) * 1993-04-15 2001-10-29 松下電工株式会社 立体表面への膜形成方法
DE4315272A1 (de) 1993-05-07 1994-11-10 Siemens Ag Leistungshalbleiterbauelement mit Pufferschicht
JPH08158027A (ja) * 1994-12-05 1996-06-18 Nippon Foil Mfg Co Ltd 圧延銅箔の焼鈍方法
KR100371974B1 (ko) * 1997-05-26 2003-02-17 스미토모덴키고교가부시키가이샤 구리회로접합기판 및 그 제조방법
JP2004022852A (ja) * 2002-06-18 2004-01-22 Cmk Corp 微細回路の形成方法
JP4704025B2 (ja) * 2004-12-21 2011-06-15 Ｊｘ日鉱日石金属株式会社 高周波回路用粗化処理圧延銅箔及びその製造方法
JP2006202586A (ja) * 2005-01-20 2006-08-03 Nissan Motor Co Ltd 接合方法及び接合構造
JP4857594B2 (ja) * 2005-04-26 2012-01-18 大日本印刷株式会社 回路部材、及び回路部材の製造方法
US7262491B2 (en) * 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
WO2007061112A1 (ja) * 2005-11-28 2007-05-31 Dai Nippon Printing Co., Ltd. 回路部材、回路部材の製造方法、及び、回路部材を含む半導体装置
JP4731340B2 (ja) 2006-02-02 2011-07-20 富士通株式会社 半導体装置の製造方法
US7821130B2 (en) * 2008-03-31 2010-10-26 Infineon Technologies Ag Module including a rough solder joint
US7754533B2 (en) * 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device
JP5824201B2 (ja) * 2009-09-11 2015-11-25 Ｄｏｗａエレクトロニクス株式会社 接合材およびそれを用いた接合方法
JP2011073194A (ja) * 2009-09-29 2011-04-14 Dowa Metaltech Kk 金属−セラミックス接合基板およびその製造方法
US8885326B2 (en) * 2011-04-26 2014-11-11 Rohm Co., Ltd. Solid electrolytic capacitor and method for manufacturing the same
JP6099453B2 (ja) * 2012-11-28 2017-03-22 Ｄｏｗａメタルテック株式会社 電子部品搭載基板およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1368904A (zh) * 1999-07-09 2002-09-11 希普雷公司 在绝缘基板上形成薄金属层的方法
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
DE102006037198A1 (de) * 2006-08-09 2008-02-14 Waag, Andreas, Dr. Verbindungsschicht mit anisotroper Leitfähigkeit

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EP3048640A1 (en) 2016-07-27
JP2015053414A (ja) 2015-03-19
WO2015034078A1 (ja) 2015-03-12
US9831157B2 (en) 2017-11-28
EP3048640A4 (en) 2017-07-19
CN105531805A (zh) 2016-04-27
JP6262968B2 (ja) 2018-01-17
KR20160054549A (ko) 2016-05-16

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