CN105514073B - 具有限制层的互连结构 - Google Patents

具有限制层的互连结构 Download PDF

Info

Publication number
CN105514073B
CN105514073B CN201510621969.5A CN201510621969A CN105514073B CN 105514073 B CN105514073 B CN 105514073B CN 201510621969 A CN201510621969 A CN 201510621969A CN 105514073 B CN105514073 B CN 105514073B
Authority
CN
China
Prior art keywords
layer
contact pad
conductive material
tsv
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510621969.5A
Other languages
English (en)
Other versions
CN105514073A (zh
Inventor
罗晓筠
林咏淇
薛仰志
吴仓聚
邱文智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US14/511,006 external-priority patent/US9673132B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105514073A publication Critical patent/CN105514073A/zh
Application granted granted Critical
Publication of CN105514073B publication Critical patent/CN105514073B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04073—Bonding areas specifically adapted for connectors of different types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05018—Shape in side view being a conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05023—Disposition the whole internal layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0568—Molybdenum [Mo] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05681—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明公开了一种互连结构和用于提供互连结构的方法，该互连结构包括具有减小的形貌变化的导电部件。互连结构包括设置在衬底上方的接触焊盘。接触焊盘包括第一导电材料的第一层和位于第一层上方的第二导电材料的第二层。第一导电材料和第二导电材料由基本相同的材料制成并且具有第一平均晶粒尺寸和第二平均晶粒尺寸，第二平均晶粒尺寸小于第一平均晶粒尺寸。互连结构还包括覆盖衬底和接触焊盘的钝化层，并且钝化层具有暴露出接触焊盘的开口。本发明还涉及具有限制层的互连结构。

Description

具有限制层的互连结构
相关申请的交叉引用
本申请是于2014年6月9日提交的美国申请第14/299,886号的部分继续申请，其是于2012年4月27日提交的美国申请第13/457,841号(现在发行为美国专利第8,772,945)的分案申请，其全部内容通过引用结合于此作为参考。
技术领域
本发明涉及具有限制层的互连结构。
背景技术
一般来说，现代电子产品的设计中的一个驱动因素是在给定的空间内可以塞进的计算效率的量和存储的量。用于将更多的计算效率封装到给定的空间和减少形成系统的各个芯片之间的距离的一种方法是堆叠芯片，其中互连件垂直地延伸。衬底中的嵌入式互连件或金属填充的通孔通常被称为硅通孔或衬底通孔(“TSV”)。TSV可以用来连接位于衬底的相对两侧上的芯片，或提供穿过芯片的主体的芯片级连接。
TSV也用于创建3D集成电路，并且与引线接合或其他连接技术相比是有利的，这是因为通孔的密度基本上更高，并且因为连接件的长度更短。诸如系统级封装、芯片堆叠多芯片模块(MCM)等的3D封装件包含两个以上的芯片(集成电路)垂直地堆叠，从而使得它们占用较少的空间和/或具有更大的连通性。3D封装的另一类型是硅载体封装技术，其中，IC不堆叠但是含有TSV的载体衬底用于将封装件中的多个IC连接在一起。在大多数3D封装件中，堆叠的芯片沿着它们的边缘布线在一起，并且该边缘布线略增加封装件的长度和宽度，并且通常需要位于芯片之间的中介层。在一些3D封装件中，通过生成穿过芯片的主体的垂直互连件而使硅通孔代替边缘布线。产生的封装件没有增加的长度或宽度。因为不需要中介层，TSV3D封装件也可以比边缘布线的3D封装件更均匀(flatter)。这种TSV技术有时也被称为TSS(硅穿通堆叠或硅穿孔堆叠)。3D集成电路(3D IC)是通过堆叠硅晶圆和/或管芯并且垂直地互连它们从而使得它们表现为单个器件的单个集成电路。通过使用TSV技术，3D IC可以将大量的功能集成到一个小的覆盖区内。堆叠件中的不同的管芯可以是异质的，例如将CMOS逻辑、DRAM和III-V族材料组合至单个IC内。
不需要使用硅作为中介层或衬底，即使是指硅中的通孔。这些中介层衬底通常是硅、玻璃或一些其他绝缘体，其中，铜、金或其他导体设置在穿过中介层的通孔中。
发明内容
为了解决现有技术中的问题，根据本发明的一些实施例，提供了一种半导体器件，包括：接触焊盘，设置在衬底上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸；钝化层，覆盖所述衬底和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及连接件，穿过所述开口连接至所述接触焊盘。
根据本发明的另一些实施例，提供了一种半导体器件，包括：衬底，具有有源表面和与所述有源表面相对的非有源表面；衬底通孔(TSV)结构，嵌入在所述衬底中并且具有从所述非有源表面突出的突出部分；接触焊盘，设置在所述TSV结构的突出部分上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸；钝化层，覆盖所述衬底的非有源表面和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及连接件，穿过所述开口连接至所述接触焊盘。
根据本发明的又一些实施例，提供了一种用于制造半导体器件的方法，包括：使用多步电镀操作在衬底上方形成接触焊盘，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，所述多步电镀操作包括以第一镀速率沉积所述第一层和以第二镀速率沉积所述第二层，所述第二镀速率小于所述第一镀速率；在所述接触焊盘上方形成钝化层，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及穿过所述开口将连接件连接至所述接触焊盘。
附图说明
为了更完全地理解本发明实施例及其优势，现在结合附图来对以下的描述作出参考，其中：
图1A是示出衬底上的TSV材料的典型的沉积的截面图；
图1B是示出抛光之后的典型的TSV和衬底的截面图；
图1C是示出典型的TSV中的表面扩散和晶粒再定向的截面图；
图2A是示出沉积TSV材料以为创建阻挡焊盘结构作准备的实施例的截面图；
图2B是仅金属第一化学机械抛光之后的TSV结构的截面图；
图2C是具有示例性阻挡焊盘的TSV结构的截面图；
图2D是具有第二沉积的TSV材料的TSV结构的截面图；
图2E是具有阻挡焊盘并且在第二平坦化之后的TSV结构的截面图；
图3是示出用于构建具有阻挡焊盘的TSV的步骤的流程图；
图4A是具有另一示例性的阻挡焊盘的TSV结构的截面图；
图4B是具有在另一示例性的阻挡焊盘上的第二沉积TSV材料的TSV结构的截面图；
图4C是具有另一示例性阻挡焊盘和在第二平坦化之后的TSV结构的截面图；
图5A至图5I是根据本发明的一些实施例的在形成包括互连结构的半导体器件中的中间步骤的截面图，其中，互连结构具有限制层；
图6是根据本发明的一些实施例的在图5中示出的标记部分的放大视图；
图7A和图7B示出了根据本发明的一些实施例的接触焊盘的顶视图的光学显微镜图像；
图8至图10是根据本发明的各个可选实施例的半导体器件的截面图；以及
图11是根据本发明的一些实施例示出的形成包括互连结构的半导体器件的方法的流程图，其中，互连结构具有限制层。
具体实施方式
在下文中详细论述了本实施例的制造和使用。然而，应当理解，本发明提供了许多可以体现在各种具体上下文中的可应用的概念。所论述的具体实施例仅仅是制造和使用所公开的主题的说明性的具体方式，并且不限制不同实施例的范围。
将结合具体环境来描述实施例，即，硅通孔(TSV)结构。然而，其他实施例中也可以应用至其他的电气结构，包括但不限于，导电互连件、再定向层、球栅阵列、管芯安装结构、或任何其他导电结构。此外，虽然参考提供具有阻挡焊盘并且设置在用于封装件水平处理(诸如倒装芯片封装)中的衬底中的TSV来描述所呈现的原理，但是本领域普通技术人员将认识到可以将相同的原理有利地应用至其他规模。例如，本发明所呈现的原理可以应用于诸如印刷电路板的更高水平封装，或应用于管芯水平制造，诸如设置在半导体衬底材料中作为穿过芯片的主体的连接件的通孔，通孔在3D封装件或3D集成电路中使用以代替边缘布线互连系统。
本发明的概念是针对提供具有阻挡焊盘的嵌入式互连件或硅通孔以减少表面扭曲。阻挡焊盘可以以一深度设置在TSV中的导电焊盘下方，该深度足以降低表面导电焊盘中的金属晶体的平均尺寸并且创建用于附接互连件的更平滑的表面。
参考图1A，示出了衬底102上的TSV材料的典型的沉积的截面图。当在衬底102中形成通孔并且在衬底102上沉积导电TSV材料106时形成TSV104。理想的情况是，TSV材料106应完全地填充通孔。使用TSV材料106填充通孔过程中的空隙或其他物理的缺陷可能改变TSV104的导电性能。在沉积TSV材料106的单独的层中，优选地使TSV材料填充通孔的长度和宽度。
TSV 104的直径通常在1微米和20微米之间。然而，TSV 104的直径可以具有任何适当的尺寸。TSV 104可以旨在承载特定的电流，并且因此，可以基于TSV 104的高度(推而广之，衬底102的厚度)、TSV材料106的电阻和所需要的电流容量来确定合适的最小直径。此外，TSV 104的最大直径仅实际上仅受到TSV 104的期望的密度的限制。
TSV材料106也可以由各种导电材料组成。本领域普通技术人员将认识到铜(Cu)可以是一种常用的TSV材料106，并且由于其低成本而是有利的。可选地，金(Au)、钯(Pd)、镍(Ni)、金镍合金(AuNi)、钛(Ti)、铝(Al)或任何其他充分的导电材料也可以有利地用作TSV材料106。
在金属TSV材料106中表现的一个特征是金属晶粒结构。任何金属块是由大量的晶粒制成的，晶粒是金属原子的封装结构中的规则性区域。在晶界处，原子变得未对准，从而生成已知为位错的不规则。诸如合金化、冷加工、退火和回火的金属化处理可以改变金属晶粒的布置和尺寸。例如，冷加工打破了较大晶粒结构，使金属更硬和更脆，同时退火使用热量，然后缓慢冷却以通过生长较大的晶粒结构来软化金属。
铜(Cu)、铝(Al)、银(Ag)和金(Au)形成具有面心立方晶格的金属化晶体结构，从而形成立方体、八面体、十二面体和相关的晶体形态。相比之下，钛(Ti)、锌(Zn)、镉(Cd)形成六角形晶格，而钨(W)和钼(Mo)形成体心立方晶格。虽然一些金属形成相同类型的晶格，应当指出的是，晶格的间距可以不同，从而在两个沉积在一起的金属的界面处产生晶体结构不连续性。因此，金属类型可以决定晶体的晶格，这可以反过来决定TSV 104中的金属化晶粒结构的平均尺寸和形状。任何“晶种”或通过预先存在的化学物质的金属晶粒结构的影响也可以影响在TSV104中使用的金属的平均晶粒尺寸。
可以以任何合适的方式沉积TSV材料106，包括但不限制于电镀、浸没、化学汽相沉积、溅射、等离子体增强化学汽相沉积等。然而，沉积方法可以决定TSV材料106中的晶界的形成和物理性质。通孔的尺寸和几何形状也可以决定在TSV材料中形成的晶体晶粒的尺寸和物理性质。例如，狭窄的直径通孔将具有比更宽的通孔更小的平均晶粒结构。
电镀铜(Cu)是沉积廉价材料以形成TSV 104的廉价的方法。如图所示，在这一工艺中，TSV材料106可同时沉积在TSV 104中和沉积在衬底102目标表面上。在沉积的TSV材料106在衬底102的表面之上延伸的情况下，一个或多个晶粒结构可以凸立(proud)于衬底102的上表面或目标表面或在衬底102的上表面或目标表面之上延伸。
参考图1B，示出了在抛光120之后的TSV和衬底的截面图。在其中TSV材料106沉积在衬底上以及沉积在通孔中的情况下，可研磨或抛光TSV材料106，从而使得在TSV 104和衬底中的抛光的TSV材料122形成平坦、均匀的表面。这可以通过机械或化学机械抛光来完成。然而，当抛光具有较大晶粒结构的金属时遇到的一个问题为位于抛光界面处的单独的晶体晶粒可以被剪切，或者可以被压缩和/或重新布置在晶体金属基体中。凸晶粒124被取代在抛光的TSV材料106内，并且被示出为剪切的，其中，矩形晶粒结构已经被打乱。
图1C是表现表面扩散和晶粒再定向140的TSV104的截面图。在半导体材料的处理期间，包括具有TSV104的半导体衬底，通常将衬底102加热至影响TSV104的金属化结构的温度。例如，在掺杂之后，可以加热半导体以驱动任何沉积的掺杂物质。可选地，半导体晶圆的退火是一种常见的实践方法其中，加热和缓慢冷却晶圆或其他衬底以缓解半导体衬底中的应力并且软化半导体衬底。
TSV材料106的表面处理以使TSV 104表面平滑并且使其与衬底目标表面102平齐，在金属化晶粒结构中产生了应力，特别是在表面处产生了应力。在处理期间加热衬底102和TSV 104使金属化晶粒结构变得更具有移动性，从而缓解金属化晶粒结构中的应力。晶粒结构142能够移动至一位置内并且重新形成结构，需要更少的能量以维持新位置或结构。例如，由于通过结构的加热处理引起的移动性，凸晶粒结构142的部分已经突起在衬底102表面和抛光的TSV 122表面的平面之上。这可以是在抛光工艺期间位错的晶粒结构142，结合有处理的热量允许晶粒回到能量较低的位置。可选地，晶粒结构142可能已经被切割、研磨或以其他方式去除。在这种情况下，热量处理可以允许晶粒结构的重新形成，产生出凸晶粒结构142。
抛光的TSV表面122的顶部可以用作用于安装引线接合件、其他金属安装焊盘、焊料焊盘、焊料球、再定向层或任何其他导电界面的焊盘。为了使引线接合、焊料球或其他金属至金属连接以有效地接合，抛光的TSV表面122将是理想地尽可能平滑。通常，目标表面越平滑，则接合性越好。虽然期望最小的抛光的TSV表面122部件，然而对于表面不规则性或形貌变化具有一些容差，这些形貌变化的尺寸取决于器件中部件的尺寸。例如，在利用20纳米制造工艺制造的器件中，小于约100埃的表面特征或形貌变化是可以容忍的，而在利用45纳米制造工艺制造的器件中，小于约500埃的表面特征或形貌变化是可以容忍的。
当将电导体安装至抛光的TSV表面时，提供尽可能最平滑的TSV表面允许封装件生产中的更高的产量。呈现的原理针对提供具有更小的晶粒结构的TSV结构，更小的晶粒结构引起TSV上的更小的表面变形。在特别有用的实施例中，阻挡焊盘可以沉积在TSV表面下方以防止在TSV的表面处形成大的晶粒结构。
参考图2A，在截面图中示出了在衬底102上沉积TSV材料106以为制造阻挡焊盘结构200作准备。在特别有用的实施例中，可以通过化学汽相沉积工艺在衬底102目标表面上沉积铜(Cu)。然而，任何导电材料可有利地用于TSV 104，诸如，但不限于，金(Au)、镍(Ni)、镍金合金(NiAu)、钛(Ti)、铝(Al)、钼(Mo)、钽(Ta)、钨(W)等。同样地，任何合适的沉积工艺可用于沉积TSV 104的导电材料，包括但不限于化学汽相沉积(CVD)、分子束外延(MBE)、溅射、电镀等。将TSV材料106减少为低于通孔的高度以形成底部TSV焊盘。
图2B示出在第一仅金属抛光220之后的TSV 104结构的截面图。在特别有用的实施例中，第一抛光将使TSV材料222的表面降低为低于102的表面。这里，仅金属抛光的目的是在不影响衬底102的情况下，去除TSV材料106。这种仅金属抛光优选地在TSV材料222中创建平坦且均匀的表面，从而使得后续的层具有相对于衬底102的表面的均匀的厚度。此外，去除金属称为抛光，物理研磨是不需要的。可以有利地采用化学抛光，诸如但不限于硝酸或三氯化铁蚀刻剂。可选地，可以有利地采用标准的CMP工艺的众所周知的副作用是形成铜凹面。在CMP期间，去除铜可以比去除更耐用的衬底表面快，从而导致铜部件表面低于衬底表面。
图2C示出了具有施加240的阻挡焊盘242的TSV结构的截面图。阻挡焊盘242可由诸如金属的导电材料或具有足够低的电阻以适合导电的任何其他材料形成。此外，具有与TSV材料222足够不同的晶体或晶粒结构的材料以防止阻挡焊盘用作用于晶体生长的晶种层可以是有利的。例如，当使用铜(Cu)TSV 222材料时，可以有利地施加钽(Ta)、钴(Co)、钛(Ti)、镍(Ni)等的阻挡焊盘242。这些特定金属中的每种均相对廉价，并且可以采用化学汽相沉积工艺沉积，同时表现出至铜TSV材料222的足够的粘附性和足够低的电阻。虽然，先前公开的阻挡焊盘242材料可以用于一个或多个实施例中，本领域普通技术人员将认识到任何其他合适的材料也可以用作阻挡焊盘242。
可以沉积任何合适的厚度的阻挡焊盘242以防止底部TSV焊盘222影响顶部TSV部分的晶体生长。然而，阻挡焊盘242也应当沉积成足够薄的层以防止在阻挡焊盘242本身中形成大尺寸的晶粒。因此，可以选择阻挡焊盘242厚度足够薄以防止阻挡焊盘表面形貌变化大于预定尺寸。在一个有用的实施例中，阻挡焊盘242的厚度可小于约5微米。
阻挡焊盘也可以由任何已知或未知的沉积方法沉积。例如，可以掩蔽TSV 104通孔区域，从而使得CVD工艺在TSV 104通孔中仅施加阻挡焊盘242材料。掩蔽可以允许阻挡焊盘242抛光步骤的免除，然而，可以使用广义的金属沉积工艺，随后从衬底102的表面去除阻挡焊盘242材料。例如，可以通过电镀沉积阻挡焊盘242，并且可以通过过CMP工艺从衬底102的表面去除任何阻挡焊盘242材料。可选地，可以使用等离子体汽相沉积工艺。本领域普通技术人员将认识到各种汽相沉积工艺可能导致阻挡焊盘242材料沉积在TSV 104通孔的侧壁上。这种侧壁沉积将优选地相比于TSV104通孔截面和顶部TSV焊盘282(见图2E)顶面区域足够薄，从而使得沉积将不会干扰安装的元件与顶部TSV 282焊盘的粘接。
图2D示出了具有第二沉积的TSV材料262的TSV结构的截面260。第二沉积的TSV材料262将变成顶部TSV焊盘282，顶部TSV焊盘282将有利地足够薄以防止形成足够大的晶体晶粒结构以引起表面形貌问题。在特别有用的实施例中，厚度小于约6微米的顶部TSV焊盘282使表面形貌特征降低至可容忍的范围内，并且特别有用的实施例的顶部TSV焊盘282的厚度为1微米至3微米。本领域普通技术人员将认识到顶部TSV焊盘282的厚度将决定最大形貌变化，并且特定的顶部TSV焊盘282的厚度将与预定的最大形貌变化相关或者导致预定的最大形貌变化。例如，取决于顶部TSV焊盘282的材料，6微米的顶部TSV焊盘282的厚度可以导致在加热处理之后约500埃以下的表面形貌变化
图2E示出了在第二平坦化之后的具有阻挡焊盘的TSV 104结构的截面图280。在一个实施例中，第二TSV材料262沉积可以通过CVD工艺沉积，其中，TSV材料沉积在衬底102上以及沉积在TSV 104中。抛光第二TSV沉积262以形成顶部TSV焊盘282可以有利地从衬底和顶部TSV焊盘282的表面去除任何多余的TSV材料并且使顶部TSV焊盘282的上表面平滑以使其与衬底102的目标表面共面。
图4A示出了阻挡焊盘的可选实施例400的截面图。在该实施例中，可以制备和填充如图2A和图2B中示出的衬底102和TSV104，并且可以施加阻挡焊盘402的材料而不需要精确的掩蔽。这样的沉积可能导致阻挡焊盘402的材料沉积在衬底102的整个表面或使得阻挡焊盘402的材料沉积在TSV材料222上方的通孔104内以及通孔104的侧壁上，从而形成阻挡焊盘侧壁404。可以通过任何有利的工艺实现阻挡焊盘402的材料沉积，包括但不限于，溅射、CVD、PECVD、电镀等。本领域普通技术人员将认识到阻挡焊盘侧壁404的存在不会显著地影响顶部TSV焊盘282的性能。
图4B和图4C示出了具有施加的第二金属镀层262和平坦化以形成阻挡焊盘TSV440的另一示例性阻挡焊盘402的截面图。第二金属镀层结构262可以直接施加于阻挡焊盘402的材料上，并且，在一些实施例中，可以利用用于沉积阻挡焊盘402材料的任何掩蔽。在不偏离本发明原理的情况下，可以使用任何有利的沉积技术来实施第二金属结构262的沉积工艺。
可以有利地同时平坦化第二金属镀层结构262和阻挡焊盘402的材料，或者可以以多个步骤进行平坦化。例如，可以通过化学机械抛光将第二金属镀层结构262和阻挡焊盘402的材料降低至衬底102的水平，从而使得顶部TSV焊盘282通过阻挡焊盘402和阻挡焊盘侧壁404与块状的TSV材料222分隔开。
图3是示出用于构建具有阻挡焊盘的TSV的步骤的流程图300。首先，制备用于生成TSV104的现有的衬底，包括在框302中在衬底102中形成通孔。可以通过钻孔、研磨、化学蚀刻或通过任何其他手段来创建通孔。此外，可以在这个接点处实施任何其他衬底102的制备步骤，包括但不限于，衬底102的退火、抛光、清洗、掺杂、背面研磨等。在框304中，在衬底102已经具有创建了一个或多个通孔之后，首先沉积金属镀层以形成下部TSV焊盘222。如前所述，第一金属镀层步骤可以是CVD、电镀、或任何其他合适的沉积方法。此外，在沉积之前可以掩蔽TSV 104通孔和衬底102以防止过量的TSV材料106被沉积在非有用的位置中。
在框306中，例如，通过化学机械抛光(CMP)工艺抛光、蚀刻、或以其他方式降低下部TSV焊盘222。本领域普通技术人员将认识到，在优选地顶部TSV焊盘282的最大的厚度为6微米，和优选地阻挡焊盘242的最大的厚度为约1微米的情况下，在一个有用的实施例中，底部TSV焊盘222的表面将降低至低于衬底102的表面并且小于顶部TSV焊盘和阻挡焊盘的厚度，或者小于6微米。优选地，底部TSV焊盘222将降低至低于衬底表面约0.1微米和3微米之间，以容纳优选的阻挡焊盘242和顶部TSV焊盘282的厚度。由于将TSV底部焊盘222降低为低于衬底102的目标表面，生成了用于阻挡焊盘242和顶部TSV焊盘282的空间，顶部TSV焊盘282的最终厚度可以通过降低的底部TSV焊盘222的距离，以及阻挡焊盘242的厚度控制。在框310中，在底部焊盘222上沉积阻挡层242。阻挡层242可以用作阻挡件以防止在随后形成的TSV焊盘282中形成大尺寸晶粒。在一些实施例中，阻挡层242额外地用作用于电镀TSV焊盘282的晶种层。
在框310中，可以沉积第二金属镀层结构262以形成顶部TSV焊盘282，并且在框312中进行表面处理和抛光。对于该沉积步骤可以使用任何合适的沉积工艺，并且工艺不需要与沉积阻挡焊盘242或底部TSV焊盘222相同。
在可选实施例中，阻挡焊盘242可以是施加至TSV 104的最终的焊盘，并且可以省略框310。在这样的一个实施例中，阻挡焊盘242可以沉积在TSV底部焊盘222上，和然后降低至在衬底102的表面处实现阻挡焊盘242的优选的厚度的水平。然后，可以对阻挡焊盘242本身实施全抛光以表面处理阻挡焊盘242，从而用于诸如引线接合件等的连接结构的附接。
在特别有利的实施例中，对最终的顶部焊盘，顶部TSV焊盘282或阻挡焊盘242进行表面处理至与衬底102大约相同的水平处。在互连件的接合之前，也可以实施额外的TSV表面制备步骤。例如，诸如有机可焊性保护剂的抗氧化涂层或者镀钯可以施加于铜TSV焊盘以防止铜的氧化。可选地，可以在合适的地方应用焊料球、焊膏或焊剂材料，或者除了任何其他表面涂层之外，应用焊料球、焊膏或焊剂材料。
除了提供具有如上所述的尽可能最平滑的表面的TSV结构之外，对于半导体产业而言，也需要提供具有尽可能平滑的表面的高产量互连结构。在一些实施例中，在集成电路管芯上方形成互连结构。互连结构可包括形成在电介质内和上方的诸如导电线、通孔和接触焊盘的导电部件。互连结构可设置在正侧和/或背侧上以用作正端互连结构或背端互连结构。例如，“正侧”是指靠近衬底的有源表面的一侧，并且“背侧”是指靠近衬底的非有源表面的另一侧。虽然，在本文中使用“正侧”和“背侧”，它们的使用仅仅是为了方便和便于参考。
类似于TSV材料，互连结构的导电部件由金属化材料制成，并且金属化晶粒结构也呈现在导电部件中。任何金属块是由大量的晶体晶粒制成的，晶体晶粒是金属原子的封装结构中的规则性区域。在晶界处，原子变得未对准，从而生成已知为位错的不规则。金属化晶粒结构可以凸立(proud)于目标表面或在目标表面之上延伸，并且导致表面不规则。对于形貌变化具有一些容差，这些形貌变化的尺寸取决于器件中的部件的尺寸。例如，在利用20纳米制造工艺制造的器件中，小于约100埃的表面特征或形貌变化是可以容忍的，而在利用45纳米制造工艺制造的器件中，小于约500埃的表面特征或形貌变化是可以容忍的。然而，表面的不规则性问题可以随着金属化晶粒结构的尺寸的增加恶化，并且导电部件的金属化晶粒结构在热量加热或即使仅设置在室温时之后可以再生为更大的晶粒金属化结构。如果导电部件的表面不规则性由于金属化晶粒结构的尺寸增量而变得无法忍受，位于导电部件上面的钝化层(诸如层间电介质或后钝化层)将具有不尽人意的特点。在一些实施例中，介电层和导电部件的不尽人意的特点导致电流泄漏、短路连接和导电部件的氧化。
图5A至图5I示出了根据本发明的一些实施例的在形成半导体器件500中的中间步骤的截面图，半导体器件500包括具有限制层的互连结构。应当理解，提供如图5A至图5I中示出的互连结构仅用于示出的目的，互连结构可应用于各种衬底(例如，器件衬底或中介层衬底)、半导体器件和封装结构。此外，虽然互连结构可以包括多个导电和介电部件，为了简化和简单示出的目的，仅示出了互连结构的顶部。
参考图5A，根据本发明的一些实施例示出了半导体器件500的截面图。在一些实施例中，该半导体器件500包括嵌入在衬底502中的TSV结构504。TSV结构504包括沉积在衬底502内的通孔洞中的TSV材料522(见图5D)。衬底502可以是器件衬底或中介层衬底。在特定实施例中，TSV材料522是铜(Cu)。然而，可以有利地使用任何导电材料以沉积用于TSV结构504的TSV材料522，包括但不限于金(Au)、镍(Ni)、镍金合金(NiAu)、钛(Ti)、铝(Al)、钼(Mo)、钽(Ta)、钨(W)等。可以使用任何合适的沉积技术以沉积用于TSV结构504的TSV材料522，包括但不限于化学汽相沉积(CVD)、分子束外延(MBE)、溅射、电镀等。在一些实施例中，TSV结构504具有从衬底502的表面506突出的突出部分以便于形成接触焊盘(例如，见图5E中的接触焊盘528)。在一些其他实施例中，TSV结构504不包括突出部，但是具有与衬底502(未示出)的表面506平齐的表面。在一些实施例中，表面506是与衬底502的有源表面508相对的非有源表面。
在一些实施例中，TSV结构504包括靠近其顶面形成的阻挡层焊盘(未示出)。阻挡焊盘可以由钽、钴、钛、镍等制成并且具有与TSV材料522足够不同的晶粒结构以防止阻挡焊盘用作用于晶体生长的晶粒层。在一些实施例中，TSV结构504的粗糙表面轮廓是可以容忍的，省略阻挡层焊盘。
钝化层510形成在衬底502的表面506上方，并且暴露出TSV结构504的顶部。钝化层510可以包括旋涂玻璃(SOG)、氧化硅、氮氧化硅、氮化硅、聚酰亚胺(PI)、聚苯并恶唑(PBO)等或它们的多层。在一些实施例中，钝化层510沉积在衬底502的表面506上方，并且然后对钝化层510实施平坦化操作以去除位于TSV结构504上方的钝化层510的部分。
在一些实施例中，通过旋涂、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(CVD)或原子层沉积(ALD)沉积钝化层510。例如，平坦化操作包括化学机械抛光(CMP)。
参考图5B，在衬底502的表面506上方沉积晶种层512。晶种层512包括用于后续镀工艺的晶种材料。例如，晶种层512包括金属，诸如铜、钛和铜合金、其他金属、它们的合金组合或它们的多层。在一些实施例中，例如，晶种层512的厚度为约500埃到约5000埃。可选地，晶种层可以包括其他材料和尺寸。例如，通过物理汽相沉积(PVD)或其他合适的方法形成晶种层512。
参考图5C，在晶种层512上方形成牺牲材料516。在一些实施例中，牺牲材料516包括光刻胶、有机材料、绝缘材料或其他材料。牺牲材料516被图案化为具有用于多个接触焊盘和导电线的期望的图案。例如，如图5C所示，在牺牲材料516中形成用于接触焊盘和导电线的开口520。但是，应当理解，用于接触焊盘和导电线的开口的数量不受限制。可以使用光刻工艺或直接图案化工艺图案化牺牲材料516。在光刻工艺中，牺牲材料516包括光刻胶或由光刻掩模(未示出)反射或传输的光或能量的其他材料，光刻掩模上具有期望的图案。然后显影牺牲材料516并且然后灰化或蚀刻掉牺牲材料516的部分。例如，直接图案化工艺可以包括使用激光或其他合适的方法在牺牲材料516中形成图案。
参考图5D，在牺牲材料516中的图案中依次沉积第一导电材料的第一层522a，第二导电材料的第二层522b和第三导电材料的第三层522c以形成导电线526和接触焊盘528。第二导电材料是由与第一导电材料和第三导电材料基本相同的材料制成的。此外，第二导电材料具有相比于第一导电材料和第三导电材料的不同的平均晶粒尺寸。在一个实施例中，本文中描述的基本相同的材料是指超过约99.9wt％的每种导电材料是由相同的元素或合金制成的。例如，第一、第二和第三导电材料是由铜(Cu)制成的，由于它的低成本而是有利的。可选地，可以使用金(Au)、钯(Pd)、镍(Ni)、镍金合金(Ni Au)、钛(Ti)、铝(Al)、钼(Mo)、钽(Ta)、钨(W)等。
现在参考图6，例如，其示出了图5D中的标记部分A的放大视图。第一、第二和第三导电材料分别包括第一、第二和第三金属化晶粒结构524a-524c。在一些实施例中，第二导电材料的金属化晶粒结构524b的平均晶粒尺寸小于第一和第三导电材料的金属化晶粒结构524a和524c的平均晶粒尺寸。例如，第二导电材料的金属化晶粒结构524b的平均晶粒尺寸在从约0.1微米至约0.5微米的范围内。第一导电材料的金属化晶粒结构524a的平均晶粒尺寸在从约0.5微米至几微米的范围内。第三导电材料的金属化晶粒结构524c的平均晶粒尺寸在从约0.5微米至几微米的范围内。在一些实施例中，金属化晶粒结构524a和金属化晶粒结构524c具有基本相同的平均晶粒尺寸。在一些其他实施例中，第一导电材料的金属化晶粒结构524a和第三导电材料的金属化晶粒结构524c具有不同的平均晶粒尺寸。例如，金属化晶粒结构524c的平均晶粒尺寸小于金属化晶粒结构524a的平均晶粒尺寸。在一些实施例中，金属化晶粒结构524b的平均晶粒尺寸比金属化晶粒结构524a和524c小约3倍至约5倍以在第一层522a和第三层522c可以以较高速率沉积时有效地影响第一522a层和第三层522c中的晶粒生长。
在一些实施例中，接触焊盘528和导电线526的厚度T介于约1微米至约10微米的范围内，接触焊盘528和导电线526中的每个均包括第一层522a、第二层522b、第三层522c和晶种层512。由于第二层522b形成在接触焊盘528的中间中，接触焊盘528被分为多个层，其中，层522a、522b和522c各自的厚度比接触焊盘528的总厚度T薄。例如，第一层522a的厚度T1比接触焊盘528的厚度薄约2倍至约2.5倍，并且第三层522c的厚度T3比接触焊盘528的厚度薄约2倍至约2.5倍。在一些实施例中，第一层的厚度可以在从约1微米至约4微米的范围内；并且第三层的厚度T3可以在从约1微米至约4微米的范围内。第一层522a和第三层522c的厚度可以基本相同或彼此不同。此外，第二层522b也应当沉积为足够薄以防止在第二层522b本身中形成大尺寸晶粒。例如，第二层的厚度T2在从约0.1微米至约0.5微米的范围内。第二层522b用作限制层，该限制层确保金属化晶粒结构524a和524c仅可以在第一层522a和第三层522c的相应的限定内再生长。如上所述，第一层522a和第三层522c比接触焊盘528的总厚度薄，并且因此，如果发生晶粒生长，则金属化晶粒结构524a和524c具有限制的直径。因此，在一些实施例中，在热加热之后，接触焊盘528和导电线526具有小于约1微米的形貌变化(包括顶面和侧壁表面)。
在一些实施例中，通过多步电镀操作沉积第一、第二和第三层522a–522c。电镀是一种用于沉积廉价的导电材料以形成导电材料层522a–522c的经济有效的方法。此外，可以通过调节多步电镀操作的每个步骤中的镀条件来形成第一、第二和第三导电材料的金属化晶粒结构524a–524c的不同尺寸。例如，通过调整镀速率来控制层522a至层522c中的金属化晶粒结构524a–524c的尺寸。在一些实施例中，通过调整电流密度、镀浴温度、选择的镀浴溶液和/或其他条件控制镀速率。由于较低的镀速率，第二导电材料的金属化晶粒结构524b的平均尺寸小于金属化晶粒结构524a和524c的平均尺寸。在一些实施例中，沉积第一层522a和第三层522c的镀速率比沉积第二层522b的镀速率快约2倍到约10倍，以实现较高的产量目标。在一些实施例中，通过调整镀时间段来获得期望的厚度。根据一些实施例，由于以相对较低的镀速率沉积的第二层522b相对较薄并且需要相对较短的形成时间，导电线526和接触焊盘528的产量基本上不减小。在一些实施例中，多步电镀操作包括选择镀浴溶液，镀浴溶液包含诸如CuSO4的铜盐和诸如校平器、加速器和抑制器的添加剂。在一些实施例中，通过调整镀时间段来获得层522a–522c的期望的厚度。
通过在第一、第二和第三导电材料中提供不同尺寸的金属化晶粒结构524a–524c，也发现不同浓度的杂质526(见图6)出现在每种导电材料中。在其中第一、第二和第三导电材料是由铜制成的实施例中，杂质526包括氮、硫、碳、氧或其组合或可能存在于沉积的铜材料中的其他杂质。在一些实施例中，第一导电材料的第一杂质浓度在从约50ppm至约100ppm的范围内。第二导电材料的第二杂质浓度在从约100ppm至约300ppm的范围内。第三导电材料的第三杂质浓度在从约50ppm至约100ppm的范围内。第二导电材料可以具有比第一导电材料和第三导电材料更高的杂质浓度。在一些实施例中，第二导电材料的杂质浓度比第一和第三导电材料的杂质浓度高约2倍到约10倍。因为杂质浓度相对于诸如铜的主要材料非常小，所以第二导电材料的较高的杂质浓度将基本上不影响接触焊盘528和导电线526的电导率。
参考图5E，去除牺牲材料516，并且然后去除晶种层512的暴露部分。暴露出各自包括第一、第二和第三层522a–522c和剩余的晶种层512’的导电线526和接触焊盘528。在一些实施例中，导电线526可以用作后钝化线，有时也被称为后钝化互连件(PPI)。在一些实施例中，接触焊盘528包括布置成球栅阵列或其他的布置的图案中的凸块下金属化结构。
参考图5F，在衬底502的表面506上方形成另一钝化层550。如图5F所示，钝化层550以共形的方式覆盖衬底502的表面506、导电线526和接触焊盘528。在一些实施例中，钝化层550可以包括阻焊剂(SR)、聚酰亚胺(PI)、聚苯并恶唑(PBO)、旋涂玻璃(SOG)、氧化硅、氮氧化硅、氮化硅、等或它们的多层。例如，钝化层550的厚度在从约0.2微米至约2微米的范围内。可选地，钝化层550包括其他的材料和尺寸。例如，通过化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)或其他合适的沉积技术形成钝化层550。
参考图5G，在衬底502的表面506上方形成另一牺牲材料552。牺牲材料552包括光刻胶、有机材料、绝缘材料或其他材料。牺牲材料552被图案化并且包括暴露出接触焊盘528的至少一部分的开口554。可以使用光刻工艺或直接图案化工艺形成开口554。在光刻工艺中，牺牲材料552暴露于通过光刻掩模(未示出)反射或传输的光或能量，光刻掩模上具有期望的图案。然后显影牺牲材料552。例如，直接图案化工艺可以包括使用激光或其他合适的方法在牺牲材料552中形成开口554。
参考图5H，使用牺牲材料552作为掩模去除在开口554中的钝化层550的部分。通过开口556暴露出接触焊盘528。参考图5I，在一些实施例中，然后连接件560通过开口556连接至接触焊盘528。例如，连接件560包括诸如焊料的共晶材料。在一些实施例中，共晶材料包括通过加热共晶材料至共晶材料的融化温度回流焊球或焊膏。例如，使用中间掩模将共晶材料放置在开口554中。然后冷却和再固化共晶材料，将连接件560连接至接触焊盘528。连接件560可以包括其他类型的电连接件，诸如微凸块、可控塌陷芯片连接(C4)凸块或支柱，并且可以包括诸如Cu、Sn、Ag、Pb等的导电材料。在将连接件560连接至接触焊盘528之前或之后，可以去除牺牲材料552。
值得注意的是，接触焊盘528的改进的形貌变化也可以提供连接件560的放置的提高的精确度。图7A和图7B分别示出了形成为不具有限制层的接触焊盘和形成为具有限制层的接触焊盘的顶视图的光学显微镜图像。如图7A所示，一些黑点缺陷显示在接触焊盘的顶面上，并且使得接触焊盘的边缘可能与背景混淆。相比之下，图7B示出了具有更平滑的顶面并且基本上没有黑点缺陷的接触焊盘，从而可以清晰地从背景中识别。
参考图8，根据本发明的可选实施例示出了半导体器件800的截面图。在一些实施例中，半导体器件800包括从衬底502的表面506突出的TSV结构504。在一些实施例中，TSV结构504具有与衬底502(未示出)的表面506平齐的顶面。半导体器件800包括互连结构，互连结构包括在衬底502的表面506上方形成的导电线826和接触焊盘828。在实施例中，接触焊盘828设置在TSV结构504上方，并且导电线826邻近TSV结构504设置。在一些实施例中，导电层826和接触焊盘828包括至少两层，其中，接触焊盘828的顶层是第二导电材料的第二层522b。顶层522b下方的层是第一导电材料的第一层522a。晶种层512’形成在第一层522a和TSV结构504之间。钝化层550以共形的方式覆盖接触焊盘828和导电线826，并且具有暴露出接触焊盘828的开口。连接件560可以通过开口连接至接触焊盘828。在半导体器件800中，因为顶层包括更小的金属化晶粒结构，在接触焊盘828和导电线826的顶部拐角处提供更好的表面轮廓。可以在接触焊盘828和导电线826的顶部拐角处获得更好的修饰。此外，也可以获得接触焊盘828的改进的顶面轮廓。
参考图9，根据本发明的一些实施例示出了半导体器件900的截面图。半导体器件900类似于半导体器件500，除了接触焊盘928和导电线926各自包括多个第二层522b之外。多个第二层522b可以进一步降低接触焊盘928和导电线926中的其他层的厚度。从而，可以改进限制金属化晶粒结构的再生长的性能。
参考图10，根据本发明的一些实施例示出了半导体器件1000的截面图。图10示出了互连结构的接触焊盘1028和导电线1026可以实现为独立于TSV结构。接触焊盘1028和导电线1026可以具有与接触焊盘528和导电线526类似的结构，除了接触焊盘1028具有平坦的底部并且没有TSV结构形成在下面之外。可以通过与接触焊盘528和导电线526类似的方法形成接触焊盘1028和导电线1026。
图11是根据本发明的一些实施例的示出形成半导体器件的方法1100的流程图，半导体器件包括具有限制层的互连结构。方法1100包括操作1102，其中，使用多步电镀操作在衬底上方形成包括第一导电材料的第一层和位于第一层上方的第二导电材料的第二层的接触焊盘，多步电镀操作包括以第一镀速率沉积第一层和以第二镀速率沉积第二层，第二镀速率比第一镀速率慢。在一些实施例中，导电线也是由位于衬底的表面上方的多个层形成的。在一些实施例中，第二层的平均晶粒尺寸小于第一层的平均晶粒尺寸。在一些实施例中，第二层的杂质浓度高于第一层的杂质浓度。方法1100继续操作1104，其中，在衬底和接触焊盘上方形成钝化层，其中，钝化层具有暴露出接触焊盘的开口。方法1100继续操作1106，其中，通过开口将连接件连接至接触焊盘。
本发明的实施例提供了优于现有技术的优势，但是应当理解，其他实施例可以提供不同的优势，不是所有的优势都必须在本文中论述，并且没有特定的优势是所有的实施例都需要的。通过利用公开的半导体器件及其制造方法，在各个工艺之后，接触焊盘和位于其上的钝化层之间的适应性可以基本维持而不会损失产量。半导体器件也提供了接触焊盘上的连接件的放置的更好的精度。
因此，本发明根据一些实施例提供了一种半导体器件。半导体器件包括设置在衬底上方的接触焊盘。接触焊盘包括第一导电材料的第一层和位于第一层上方的第二导电材料的第二层。第一导电材料和第二导电材料由基本相同的材料制成。第一导电材料具有第一平均晶粒尺寸和第二导电材料具有第二平均晶粒尺寸，第二平均晶粒尺寸小于第一平均晶粒尺寸。半导体器件还包括覆盖衬底和接触焊盘的钝化层，钝化层具有暴露出接触焊盘的开口。半导体器件还包括通过开口连接至接触焊盘的连接件。
本发明根据一些实施例还提供了一种半导体器件。半导体器件包括具有有源表面和与有源表面相对的非有源表面的衬底。半导体器件还包括嵌入在衬底中的衬底通孔(TSV)结构，TSV结构包括从非有源表面突出的突出部分。半导体器件还包括设置在TSV结构的突出部分上方的接触焊盘。接触焊盘包括第一导电材料的第一层和位于第一层上方的第二导电材料的第二层。第一导电材料和第二导电材料由基本相同的材料制成，其中，第一导电材料具有第一平均晶粒尺寸和第二导电材料具有第二平均晶粒尺寸，第二平均晶粒尺寸小于第一平均晶粒尺寸。半导体器件还包括覆盖衬底和接触焊盘的钝化层，并且钝化层具有暴露出接触焊盘的开口。此外，半导体器件包括通过开口连接至接触焊盘的连接件。
本发明根据本发明的一些实施例提供了一种用于制造半导体器件的方法。该方法包括：在衬底上方使用多步电镀操作形成接触焊盘，接触焊盘包括第一导电材料的第一层和位于第一层上方的第二导电材料的第二层，多步电镀操作包括以第一镀速率沉积第一层和以第二镀速率沉积第二层，第二镀速率小于第一镀速率。该方法还包括在半导体衬底和接触焊盘上方形成钝化层。钝化层具有暴露出接触焊盘的开口。该方法还包括通过开口将连接件连接至分层的焊盘结构。
尽管已经详细地描述了实施例及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，可以对本发明进行各种改变、替换和更改。那些本领域普通技术人员应当理解，可以使用各种材料和处理步骤的顺序来实现以上论述的许多部件和功能。作为另一实例，那些本领域普通技术人员应当理解，可以以各种有利顺序实施许多步骤，同时仍保持在本发明的范围内。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。
为了解决现有技术中的问题，根据本发明的一些实施例，提供了一种半导体器件，包括：接触焊盘，设置在衬底上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸；钝化层，覆盖所述衬底和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及连接件，穿过所述开口连接至所述接触焊盘。
在上述半导体器件中，其中，所述第一平均晶粒尺寸比所述第二平均晶粒尺寸大约3倍至约5倍。
在上述半导体器件中，其中，所述第二平均晶粒尺寸在从约0.1微米至约0.5微米的范围内。
在上述半导体器件中，其中，所述第一导电材料包括铜、金、钯、镍、金-镍合金、钛、铝或它们的组合。
在上述半导体器件中，其中，所述第一层的厚度比所述接触焊盘的厚度薄约2倍至约2.5倍。
在上述半导体器件中，其中，所述第二层的杂质浓度比所述第一层的杂质浓度高。
在上述半导体器件中，其中，所述第二层的杂质浓度比所述第一层的杂质浓度高；其中，所述杂质包括氮、硫、碳、氧或它们的组合。
在上述半导体器件中，其中，所述第二层的杂质浓度比所述第一层的杂质浓度高；其中，所述第二层的杂质浓度比所述第一层的杂质浓度高2倍至约10倍。
在上述半导体器件中，还包括：衬底通孔(TSV)结构，嵌入在所述衬底中并且位于所述接触焊盘下方；以及导电线，设置在所述衬底上方并且邻近所述接触焊盘，其中，所述导电线包括所述第一层和所述第二层并且被所述钝化层覆盖。
在上述半导体器件中，其中，所述第二层是所述接触焊盘的顶层。
在上述半导体器件中，还包括：第三导电材料的第三层，位于所述第二层上方，其中，所述第三导电材料是由与所述第二导电材料基本上相同的材料制成的并且具有第三平均晶粒尺寸，所述第三平均晶粒尺寸大于所述第二平均晶粒尺寸。
根据本发明的另一些实施例，提供了一种半导体器件，包括：衬底，具有有源表面和与所述有源表面相对的非有源表面；衬底通孔(TSV)结构，嵌入在所述衬底中并且具有从所述非有源表面突出的突出部分；接触焊盘，设置在所述TSV结构的突出部分上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸；钝化层，覆盖所述衬底的非有源表面和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及连接件，穿过所述开口连接至所述接触焊盘。
在上述半导体器件中，其中，所述第二层的厚度在从约0.1微米至约0.5微米的范围内。
在上述半导体器件中，还包括：导电线，位于所述衬底上方并且邻近所述TSV结构，其中，所述导电线包括所述第一层和所述第二层并且被所述钝化层覆盖。
在上述半导体器件中，还包括：导电线，位于所述衬底上方并且邻近所述TSV结构，其中，所述导电线包括所述第一层和所述第二层并且被所述钝化层覆盖；其中，所述导电线是后钝化线。
在上述半导体器件中，还包括：第三导电材料的第三层，位于所述第二层上方，其中，所述第三导电材料是由与所述第二导电材料基本上相同的材料制成的，并且所述第三导电材料的杂质浓度低于所述第二导电材料的杂质浓度。
根据本发明的又一些实施例，提供了一种用于制造半导体器件的方法，包括：使用多步电镀操作在衬底上方形成接触焊盘，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，所述多步电镀操作包括以第一镀速率沉积所述第一层和以第二镀速率沉积所述第二层，所述第二镀速率小于所述第一镀速率；在所述接触焊盘上方形成钝化层，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及穿过所述开口将连接件连接至所述接触焊盘。
在上述方法中，还包括：在形成所述接触焊盘的同时形成导电线，其中，所述导电线包括所述第一层和所述第二层。
在上述方法中，其中，所述第一镀速率比所述第二镀速率快约2倍至约10倍。
在上述方法中，还包括：使用所述多步电镀操作在所述第二层上方形成第三层，其中，所述多步电镀操作还包括以比所述第二镀速率快的第三镀速率沉积所述第三层。

Claims (19)

1.一种半导体器件，包括：
接触焊盘，设置在衬底上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸，其中，所述第二层的杂质浓度比所述第一层的杂质浓度高；
钝化层，覆盖所述衬底和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及
连接件，穿过所述开口连接至所述接触焊盘。
2.根据权利要求1所述的半导体器件，其中，所述第一平均晶粒尺寸比所述第二平均晶粒尺寸大3倍至5倍。
3.根据权利要求1所述的半导体器件，其中，所述第二平均晶粒尺寸在从0.1微米至0.5微米的范围内。
4.根据权利要求1所述的半导体器件，其中，所述第一导电材料包括铜、金、钯、镍、金-镍合金、钛、铝或它们的组合。
5.根据权利要求1所述的半导体器件，其中，所述第一层的厚度比所述接触焊盘的厚度薄2倍至2.5倍。
6.根据权利要求1所述的半导体器件，其中，所述杂质包括氮、硫、碳、氧或它们的组合。
7.根据权利要求1所述的半导体器件，其中，所述第二层的杂质浓度比所述第一层的杂质浓度高2倍至10倍。
8.根据权利要求1所述的半导体器件，还包括：
衬底通孔(TSV)结构，嵌入在所述衬底中并且位于所述接触焊盘下方；以及
导电线，设置在所述衬底上方并且邻近所述接触焊盘，其中，所述导电线包括所述第一层和所述第二层并且被所述钝化层覆盖。
9.根据权利要求1所述的半导体器件，其中，所述第二层是所述接触焊盘的顶层。
10.根据权利要求1所述的半导体器件，还包括：第三导电材料的第三层，位于所述第二层上方，其中，所述第三导电材料是由与所述第二导电材料基本上相同的材料制成的并且具有第三平均晶粒尺寸，所述第三平均晶粒尺寸大于所述第二平均晶粒尺寸。
11.一种半导体器件，包括：
衬底，具有有源表面和与所述有源表面相对的非有源表面；
TSV(衬底通孔)结构，嵌入在所述衬底中并且具有从所述非有源表面突出的突出部分；
接触焊盘，设置在所述TSV结构的突出部分上方，其中，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，其中，所述第一导电材料和所述第二导电材料由基本相同的材料制成，其中，所述第一导电材料具有第一平均晶粒尺寸且所述第二导电材料具有第二平均晶粒尺寸，所述第二平均晶粒尺寸小于所述第一平均晶粒尺寸；
钝化层，覆盖所述衬底的非有源表面和所述接触焊盘，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及
连接件，穿过所述开口连接至所述接触焊盘。
12.根据权利要求11所述的半导体器件，其中，所述第二层的厚度在从0.1微米至0.5微米的范围内。
13.根据权利要求11所述的半导体器件，还包括：导电线，位于所述衬底上方并且邻近所述TSV结构，其中，所述导电线包括所述第一层和所述第二层并且被所述钝化层覆盖。
14.根据权利要求13所述的半导体器件，其中，所述导电线是后钝化线。
15.根据权利要求11所述的半导体器件，还包括：
第三导电材料的第三层，位于所述第二层上方，其中，所述第三导电材料是由与所述第二导电材料基本上相同的材料制成的，并且所述第三导电材料的杂质浓度低于所述第二导电材料的杂质浓度。
16.一种用于制造半导体器件的方法，包括：
使用多步电镀操作在衬底上方形成接触焊盘，所述接触焊盘包括第一导电材料的第一层和位于所述第一层上方的第二导电材料的第二层，所述多步电镀操作包括以第一镀速率沉积所述第一层和以第二镀速率沉积所述第二层，所述第二镀速率小于所述第一镀速率；
在所述接触焊盘上方形成钝化层，其中，所述钝化层具有暴露出所述接触焊盘的开口；以及
穿过所述开口将连接件连接至所述接触焊盘。
17.根据权利要求16所述的方法，还包括：
在形成所述接触焊盘的同时形成导电线，其中，所述导电线包括所述第一层和所述第二层。
18.根据权利要求16所述的方法，其中，所述第一镀速率比所述第二镀速率快2倍至10倍。
19.根据权利要求16所述的方法，还包括：
使用所述多步电镀操作在所述第二层上方形成第三层，其中，所述多步电镀操作还包括以比所述第二镀速率快的第三镀速率沉积所述第三层。
CN201510621969.5A 2014-10-09 2015-09-25 具有限制层的互连结构 Active CN105514073B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/511,006 2014-10-09
US14/511,006 US9673132B2 (en) 2012-04-27 2014-10-09 Interconnection structure with confinement layer

Publications (2)

Publication Number Publication Date
CN105514073A CN105514073A (zh) 2016-04-20
CN105514073B true CN105514073B (zh) 2018-06-22

Family

ID=55081030

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510621969.5A Active CN105514073B (zh) 2014-10-09 2015-09-25 具有限制层的互连结构

Country Status (5)

Country Link
US (1) US10032698B2 (zh)
KR (2) KR20150141119A (zh)
CN (1) CN105514073B (zh)
DE (1) DE102014115105B4 (zh)
TW (1) TWI618215B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019066977A1 (en) 2017-09-29 2019-04-04 Intel Corporation FIRST-LEVEL THIN-LEVEL INTERCONNECTIONS DEFINED BY AUTOCATALYTIC METAL FOR LITHOGRAPHIC INTERCONNECTION HOLES
JP7097139B2 (ja) * 2018-07-26 2022-07-07 京セラ株式会社 配線基板
KR102179167B1 (ko) * 2018-11-13 2020-11-16 삼성전자주식회사 반도체 패키지
US11342229B2 (en) * 2019-06-13 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a semiconductor device structure having an electrical connection structure
US11322464B2 (en) 2019-10-01 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Film structure for bond pad
EP4272249A1 (en) * 2020-12-30 2023-11-08 Adeia Semiconductor Bonding Technologies Inc. Structure with conductive feature and method of forming same
TWI789748B (zh) 2021-04-26 2023-01-11 友達光電股份有限公司 電子裝置及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175125A (en) * 1991-04-03 1992-12-29 Chartered Semiconductor Manufacturing Ltd. Pte Method for making electrical contacts
CN1244727A (zh) * 1998-08-06 2000-02-16 三星电子株式会社 形成自对准接触的方法
CN101246875A (zh) * 2007-02-15 2008-08-20 富士通株式会社 半导体器件及其制造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4013339B2 (ja) 1998-06-29 2007-11-28 株式会社デンソー バンプを有する電子部品の製造方法
US6376353B1 (en) 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
JP2004165575A (ja) 2002-11-15 2004-06-10 Kyocera Corp 配線基板の製造方法
JP3891299B2 (ja) 2003-05-06 2007-03-14 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、半導体デバイス、電子機器
CN100483612C (zh) 2003-06-04 2009-04-29 刘明哲 用于制造垂直结构的复合半导体器件的方法
US7019402B2 (en) 2003-10-17 2006-03-28 International Business Machines Corporation Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor
US7279411B2 (en) 2005-11-15 2007-10-09 International Business Machines Corporation Process for forming a redundant structure
JP2009147218A (ja) 2007-12-17 2009-07-02 Toshiba Corp 半導体装置とその製造方法
US7741226B2 (en) 2008-05-06 2010-06-22 International Business Machines Corporation Optimal tungsten through wafer via and process of fabricating same
US8653648B2 (en) 2008-10-03 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Zigzag pattern for TSV copper adhesion
US8168529B2 (en) 2009-01-26 2012-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming seal ring in an integrated circuit die
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
US8907457B2 (en) 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US8304863B2 (en) 2010-02-09 2012-11-06 International Business Machines Corporation Electromigration immune through-substrate vias
US8232648B2 (en) 2010-06-01 2012-07-31 International Business Machines Corporation Semiconductor article having a through silicon via and guard ring
JP5730654B2 (ja) 2010-06-24 2015-06-10 新光電気工業株式会社 配線基板及びその製造方法
US8039385B1 (en) 2010-09-13 2011-10-18 Texas Instruments Incorporated IC devices having TSVS including protruding tips having IMC blocking tip ends
TWI500134B (zh) 2010-11-26 2015-09-11 財團法人工業技術研究院 矽穿孔基板結構及其堆疊組合
JP5733002B2 (ja) 2011-04-28 2015-06-10 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2013089910A (ja) * 2011-10-21 2013-05-13 Fujikura Ltd フレキシブルプリント基板及びその製造方法
KR20130053338A (ko) 2011-11-15 2013-05-23 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자
US8796851B2 (en) 2012-01-05 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and method of making same
US8772945B2 (en) 2012-04-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with embedded barrier pad
US8803292B2 (en) 2012-04-27 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias and methods for forming the same
KR20140011137A (ko) 2012-07-17 2014-01-28 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
KR101992352B1 (ko) 2012-09-25 2019-06-24 삼성전자주식회사 반도체 장치
JP2014107304A (ja) 2012-11-22 2014-06-09 Renesas Electronics Corp 半導体装置およびその製造方法
US9331038B2 (en) 2013-08-29 2016-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor interconnect structure
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175125A (en) * 1991-04-03 1992-12-29 Chartered Semiconductor Manufacturing Ltd. Pte Method for making electrical contacts
CN1244727A (zh) * 1998-08-06 2000-02-16 三星电子株式会社 形成自对准接触的方法
CN101246875A (zh) * 2007-02-15 2008-08-20 富士通株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
US20170271242A1 (en) 2017-09-21
KR20150141119A (ko) 2015-12-17
CN105514073A (zh) 2016-04-20
TWI618215B (zh) 2018-03-11
US10032698B2 (en) 2018-07-24
KR20170020398A (ko) 2017-02-22
DE102014115105B4 (de) 2023-06-22
KR101802695B1 (ko) 2017-11-28
TW201614792A (en) 2016-04-16
DE102014115105A1 (de) 2016-04-14

Similar Documents

Publication Publication Date Title
CN105514073B (zh) 具有限制层的互连结构
US11121104B2 (en) Method for manufacturing interconnect structure
US11282817B2 (en) Semiconductor device package including embedded conductive elements
US10079200B2 (en) Packaging devices and methods
US7713785B1 (en) Surface mountable direct chip attach device and method including integral integrated circuit
US9673132B2 (en) Interconnection structure with confinement layer
US9318465B2 (en) Methods for forming a semiconductor device package
JP5284314B2 (ja) 小型電子機器、その形成方法、およびシステム
KR20230116761A (ko) 반도체 장치 및 그 제조 방법
USRE46618E1 (en) Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
US10741520B2 (en) Method of controlling bump height variation
TW201246466A (en) Device packaging with substrates having embedded lines and metal defined pads
US8980741B2 (en) Through silicon via with embedded barrier pad
TW201104797A (en) Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
CN109979903A (zh) 具有凸块结构的半导体器件和制造半导体器件的方法
CN106887420A (zh) 凸块构造与其构成的内连结构
CN117542836A (zh) 半导体器件及其形成方法
KR101758999B1 (ko) 반도체 디바이스 및 그 제조 방법
KR100896841B1 (ko) 반도체 소자 제조시 본드 패드 형성방법
US20220384322A1 (en) Semiconductor package
JP2024019051A (ja) 熱管理構造及び熱管理構造の製造方法
CN1502439A (zh) 预镀可湿引线框倒焊晶片组件限制回流时焊料扩散的方法
CN102790033A (zh) 封装结构及其制作方法
CN117594462A (zh) 凸块的成型方法
KR20240000682A (ko) 반도체 패키지 및 반도체 패키지의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant