CN105489121B - 焊盘结构和具有该焊盘结构的显示装置 - Google Patents

焊盘结构和具有该焊盘结构的显示装置 Download PDF

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CN105489121B
CN105489121B CN201510631546.1A CN201510631546A CN105489121B CN 105489121 B CN105489121 B CN 105489121B CN 201510631546 A CN201510631546 A CN 201510631546A CN 105489121 B CN105489121 B CN 105489121B
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metal layer
contact hole
display device
contact
pad structure
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CN105489121A (zh
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黄淳载
郑基
郑一基
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LG Display Co Ltd
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LG Display Co Ltd
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • GPHYSICS
    • G02OPTICS
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    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
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    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00Electroluminescent light sources
    • H05B33/02Details
    • H05B33/06Electrode terminals
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    • H05K1/0298Multilayer circuits
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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Abstract

焊盘结构和具有该焊盘结构的显示装置。本发明提供了一种显示装置,该显示装置包括:多条信号线,其布置在基板的显示区中;焊盘结构,其位于非有源区中并且与信号线连接。所述焊盘结构包括多个金属层和两个或更多个绝缘层,所述绝缘层位于所述金属层之间并且具有使所述金属层之中的两个金属层彼此接触的一个或更多个接触孔,分别位于所述绝缘层中的所述接触孔没有彼此重叠。

Description

焊盘结构和具有该焊盘结构的显示装置
相关申请的交叉引用
本申请要求2014年10月2日提交的韩国专利申请No.10-2014-0132959的优先权和权益,该专利申请特此出于所有目的以引用方式并入,如同在本文中完全阐明。
技术领域
本发明涉及焊盘结构和具有该焊盘结构的显示装置。
背景技术
一直在研究开发诸如厚度纤薄、重量减轻、低功耗等各种平板显示器的性能。
近来,已经使用了诸如液晶显示装置(LCD)、等离子体显示面板装置(PDP)、场发射显示装置(FED)、电致发光显示装置(ELD)、电润湿显示装置(EWD)和有机发光显示装置(OLED)的各种平板显示器。
通常,平板显示器包括显示面板、选通驱动器、数据驱动器、时序控制器和电压发生器。显示面板在多条选通线和多条数据线的各交叉部分限定各像素。选通驱动器驱动多条选通线。数据驱动器包括驱动多条数据线的多个数据驱动集成电路。时序控制器为选通驱动器和数据驱动器提供各种控制信号。电压发生器产生参考电压并且将参考电压提供给数据驱动器。
选通驱动器可内置于显示面板的非有源区并且多个数据驱动集成电路以膜上芯片(COF)的方式安装在膜上,以减小平板显示器的体积并且降低制造成本。
各种信号线、选通驱动器、数据线等集成在显示装置中,趋势是使它们最小。因此,组件制造过程所需的设计余量变得不充足并且需要精确对准技术。
在数据驱动器的情况下,形成两个或更多个接触孔,使得缺少设计余量会导致接触电阻根据接触孔的最小而增大。因接触孔重叠,造成陡峭的阶梯,使得数据驱动集成电路和上面安装数据驱动集成电路的膜之间会发生断开缺陷。
发明内容
按照一个实施方式,显示装置可包括:多条信号线,其布置在基板的显示区中;焊盘结构,其位于非有源区中并且与信号线连接。
所述焊盘结构可包括两个或更多个金属层和绝缘层,所述绝缘层位于所述金属层之间并且具有使所述金属层之中的两个金属层彼此接触的一个或更多个接触孔,分别位于所述绝缘层中的所述接触孔没有彼此重叠。
按照另一个实施方式,一种焊盘结构可包括:两个或更多个金属层;绝缘层,其位于所述金属层之间并且具有使所述金属层之中的两个金属层彼此接触的一个或更多个接触孔。
分别位于所述绝缘层中的所述接触孔可不彼此重叠。
附图说明
图1是根据本发明的实施方式的显示装置的示意性系统构造视图。
图2是示意性示出根据本发明的一个实施方式的显示装置的平面图。
图3A是示意性示出一般显示装置的焊盘结构的平面图。
图3B和图3C是示出一般显示装置的焊盘结构的剖视图。
图4是示意性示出根据本发明的一个实施方式的显示装置的焊盘结构的平面图。
图5是沿着图4的C-C'线截取的剖视图。
图6是沿着图2中的部分“E”的F-F'线截取的剖视图。
图7是放大图6中的部分“G”的剖视图。
图8A是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图8B是沿着图8A的I-I'线截取的剖视图。
图9A是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图9B是沿着图9A的II-II’线截取的剖视图。
图10A是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图10B是沿着图10A的III-III'线截取的剖视图。
图11A是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图11B是沿着图11A的IV-IV'线截取的剖视图。
图12A和图12B是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图13A和图13B是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。
图14A是示出一般显示装置的焊盘结构和数据驱动芯片膜的剖视图。
图14B是示出根据本发明的各种实施方式的显示装置的焊盘结构和数据驱动芯片膜的剖视图。
具体实施方式
下文中,将参照附图描述本发明的一些实施方式。在下面的描述中,相同元件将用相同的参考标号指明,尽管这些相同元件是在不同附图中示出的。另外,在下面对本发明的描述中,当并入本文中的已知功能和构造的详细描述使本发明的主题相当不清楚时,它将被省略。
另外,当描述本发明的组件时,可使用诸如“第一”、“第二”、A、B、(a)、(b)等术语。这些术语中的每个并不用于限定对应组件的本质、次序顺序或数量,而只是用于将对应组件与其它组件区分开。应该注意,如果在说明书中描述了一个组件“连接”、“联接”或“接合”到另一个组件,则尽管第一组件可直接连接、联接或接合到第二组件,但第三组件可“连接”、“联接”或“接合”在第一组件和第二组件之间。
图1是根据实施方式的显示装置的示意性系统构造视图。
参照图1,根据各种实施方式的显示装置100包括:显示面板140,其包括m(这里,m是自然数)条数据线DL1、…、DLm和n(这里,n是自然数)条选通线GL1、…、GLn;数据驱动器120,其驱动m条数据线DL1、…、DLm;选通驱动器130,其顺序地驱动n条选通线GL1、…、GLn;时序控制器110,其控制数据驱动器120和选通驱动器130。
首先,时序控制器110基于诸如垂直/水平同步信号(Vsync和Hsync)、图像数据、时钟信号(CLK)等外部时序信号,输出用于控制数据驱动器120的数据控制信号(DCS)和用于控制选通驱动器130的选通控制信号(GCS)。另外,时序控制器110将从主机系统输入的图像数据(Data)转换成用在数据驱动器120中的数据信号格式,并且将转换后的图像数据(Data')提供到数据驱动器120。
响应于从时序控制器110输入的DCS和转换后的图像数据(Data'),数据驱动器120将图像数据(Data')转换成数据信号(模拟像素信号或数据电压),该数据信号是与灰阶值对应的电压值,并且数据驱动器120将数据信号提供到数据线(DL1~DLm)。
数据驱动器120将输入的图像数据Data'存储在存储器(未示出)中,将对应的图像数据Data'转换成模拟形式的数据电压Vdata,并且将数据电压Vdata提供到m条数据线DL1、…、DLm,以根据时序控制器110的控制在启用特定选通线时驱动m条数据线DL1、…、DLm。
数据驱动器120可包括多个数据驱动集成电路(也被称为源驱动集成电路)。多个数据驱动集成电路可通过载带自动键合(TAB)方法或玻璃上芯片(COG)方法与显示面板的键合焊盘连接或者直接形成在显示面板140中。有时候,多个数据驱动集成电路可被集成形成在显示面板140中。
此显示装置100可包括显示面板140的非有源区中的、与布置在有源区中的多条信号线GL和DL连接的焊盘结构。这里,焊盘结构可包括两个或更多个金属层和位于这些金属层之间并且具有使这些金属层之中的两个金属层彼此接触的一个或更多个接触孔的绝缘层。分别位于绝缘层中的接触孔没有彼此重叠。
选通驱动器130响应于从时序控制器110输入的GCS,将扫描信号(选通脉冲或扫描脉冲,和选通导通信号)顺序供应到选通线(GL1~GLn)。
根据选通驱动器130的驱动方案,上述选通驱动器130可只设置在显示面板140的一侧(如图1中所示)或者可被划分成两个单元并且设置在显示面板140的两侧。
另外,选通驱动器130可包括多个选通驱动集成电路。多个选通驱动集成电路可通过载带自动键合(TAB)方法或玻璃上芯片(COG)方法与显示面板140的键合焊盘连接,或者被实现为板内选通(GIP)型并且直接形成在显示面板140中。有时候,多个选通驱动集成电路可被集成形成在显示面板140中。
尽管选通驱动器130以板内选通(GIP)的方式位于显示面板140的一侧,但不限于此。
显示面板140上的各像素(P)可形成在由数据线(DL1~DLm)和选通线(GL1~GLn)限定的像素区中并且可设置成矩阵形式,并且可对应于包括对应于第一电极的阳极、对应于第二电极的阴极和有机层的至少一个有机发光器件。
图2是示意性示出根据一个实施方式的显示装置的平面图。
图2是示出根据一个实施方式的显示装置100和其中包括的焊盘结构的示例性视图,但不限于此。
参照图2,显示装置100可包括:多条信号线GL和DL,其布置在基板上的有源区AA中;焊盘结构DP,其位于非有源区NA中并且与信号线GL和DL连接。
这里,焊盘结构DP可包括:多个金属层;绝缘层,其位于这些金属层之间并且具有使多个金属层之中的两个金属层彼此接触的一个或多个接触孔。形成在绝缘层中的接触孔不重叠。多条选通线GL1至GLn和数据线DL1至DLm在有源区AA中交叉。
显示面板140可包括有源区(显示区)AA和非有源区(非显示区)NA。非有源区可对应于有源区AA的外部区域。像素P限定在选通线和数据线中的每条的交叉部分。
同时,选通驱动芯片或选通驱动集成电路232和上面集成了选通驱动芯片232的选通驱动芯片膜230按板内选通(GIP)的模式位于非有源区的一侧。
选通驱动芯片膜230可按玻璃上线(LOG)的方式安装在显示面板140的基板上,以与非有源区NA中的线和选通线GL1至GLn连接。尽管如图2中所示选通驱动芯片232的数量可以是两个,但当显示面板140变大时,该数量将增大。当显示面板140变大时,选通驱动芯片232还可位于显示面板140的两侧。这个选通驱动芯片232可通过选通线240将选通信号顺序地供应到选通线GL1至GLn。
同时,多个数据驱动芯片膜210布置在非有源区NA的一侧,例如,布置在图2中的非有源区的上侧。驱动芯片封装DCP的一个端部部分可与源印刷电路板(SPCB)160连接。
驱动芯片212可以是数据驱动芯片或源驱动集成电路并且置于数据驱动芯片膜上。这里,膜210可以是源柔性电路膜。数据驱动芯片膜210的输入端可以是包括导电球的各向异性导电膜(ACF)并且键合到源印刷电路板160和显示面板140的基板上。数据和时序控制信号可按膜上线(LOF)的方式通过源印刷电路板160和数据驱动芯片膜210上的线被发送到驱动芯片212。
驱动芯片212可从时序控制器110接收数据,使用数模转换器(DAC)产生数据电压,并且通过数据链接线将数据电压供应到数据线DL1至DLm。
同时,源印刷电路板160可通过柔性电路电缆170与控制印刷电路板(CPCB)180连接。控制印刷电路板180可包括时序控制器110和电力驱动芯片。
源印刷电路板160包括多条线,这多条线用于传输驱动驱动芯片212和选通驱动芯片232所需的电力和信号。可根据显示面板140的大小,在显示面板140上划分和键合多个源印刷电路板160。
时序控制器110、电力驱动芯片等置于控制印刷电路板180上。
时序控制器110基于从主机系统接收的诸如垂直/水平同步信号(Vsync和Hsync)、图像数据、时钟信号(CLK)等外部时序信号,将数据控制信号(DCS)输出到用于控制数据驱动器120的数据驱动芯片212并且将选通控制信号(GCS)输出到用于控制选通驱动器130的选通驱动芯片232。另外,时序控制器110将从主机系统输入的图像数据(Data)转换成用在数据驱动器120中的数据信号格式,并且将转换后的图像数据(Data')提供到数据驱动器120。
这里,主机系统可以是TV系统、机顶盒、导航系统、DVD播放器、蓝光显示器、个人计算机、家庭影院系统、电话系统等中的任一个。
同时,电力驱动芯片可产生施加到像素的电力、施加到数据驱动芯片212和选通驱动芯片232的电力、伽玛补偿电压(VGMA)、诸如VGH和VGL的选通驱动电力等。
在本说明书中,焊盘结构DP可以是数据焊盘结构和位于显示面板140的非有源区中的一侧的端部端口的区域的结构。换句话讲,焊盘结构可意指键合到数据驱动芯片膜210的端口的结构。
图3A是示意性示出一般显示装置的焊盘结构的平面图。图3B和图3C是示出一般显示装置的焊盘结构的剖视图。图3B和图3C是沿着图3A的A-A'线截取的剖视图。
参照图3A至图3C,一般显示装置的焊盘结构DP包括:第一金属层250,其位于基板248上;第一绝缘层252,其位于第一金属层250上并且具有第一接触孔CH1;第二金属层260,其位于第一绝缘层和通过第一接触孔CH1暴露的第一金属层250上;第二绝缘层262,其位于第二金属层260上并且具有第二接触孔CH2;第三金属层270,其位于第二绝缘层262和通过第二接触孔CH2暴露的第二金属层260上。
这里,可通过与有源区AA的选通线GL相同的过程来形成第一金属层250。可通过与数据线DL相同的过程来形成第二金属层260。可通过与有源层AA的像素电极相同的过程来形成第三金属层270。
第一绝缘层252和第二绝缘层262可由SiOx、SiNx等组成。
同时,第一接触孔和第二接触孔基本上彼此重叠。随着显示装置变大并且显示面板中的有源区的宽度变小,各种信号线GL和DL、链接线220和240和以玻璃上线(LOG)的方式形成的各种线的宽度变窄并且重叠的接触孔CH1和CH2可因设计余量不足而造成面板140中有缺陷。
图3B示出第一金属层250和第二金属层260的制造过程中的掩模的对准误差。
详细地,在第一金属层250上形成第一绝缘层252之后,形成第一接触孔,以将第一金属层250和第二金属层260彼此连接。通过掩模蚀刻第一绝缘层252。此时,如果掩模的位置没有精确对准,则可在不同于设计位置的区域形成第一接触孔CH1。
在这种情况下,问题在于,第一金属层250和第二金属层260的接触区B减小,使得接触电阻可增大。换句话讲,为了解决上述问题,第一金属层250的宽度需要增大,以确保图3A中的充足设计余量W1。例如,如果显示装置100是有机发光显示装置,则因为多条数据线DL、选通线DL和链接线220和240形成在其上,所以不可确保焊盘结构的充足设计余量W1。
同时,图3C是示出第二金属层260和第三金属层270的制造过程中的掩模的对准误差的视图。
详细地,当在形成在第二金属层260上的第二绝缘层262中形成第二接触孔CH2时,掩模可与设计位置不对准,使得它可形成在不同于设计位置的区域中。
在这种情况下,第二金属层260和第三金属层270的接触区域减小,使接触电阻增大。如图3C中所示,第二接触孔CH2的斜率变得相对陡峭,以致使第三金属层中有断开缺陷。换句话讲,在形成第三金属层270的过程中,第三金属层270可在相对陡峭区域B'中断开。这样使得第三金属层与第二层260电断开,没有保证设计余量。
以下,将参照附图描述焊盘结构DP和包括焊盘结构DP的显示装置100。
图4是示意性示出根据一个实施方式的显示装置的焊盘结构的平面图。图5是沿着图4的C-C'线截取的剖视图。
参照图4和图5,显示装置100包括:多条信号线GL和DL,其布置在基板248的有源区AA中;焊盘结构DP,其位于基板的非有源区NA中并且与信号线连接。
这里,多条信号线GL和DL包括在有源区AA中彼此交叉的数据线DL和选通线GL。
根据一个实施方式的一般显示装置的焊盘结构DP包括诸如第一金属层250、第二金属层260和第三金属层270的多个金属层。第一金属层250和第二金属层260通过第一接触孔CH1彼此连接,第一接触孔CH1位于第一金属层250和第二金属层260之间的第一绝缘层252中。第二金属层260和第三金属层270通过第二接触孔CH2彼此连接,第二接触孔CH2位于第二金属层260和第三金属层270之间的第二绝缘层262中。第一接触孔CH1的位置可不同于第二接触孔CH2的位置。
更具体地,焊盘结构DP可以是与多条信号线GL和DL之中的数据线连接的数据焊盘结构。尽管根据各种实施方式的焊盘结构可被简称为数据焊盘结构,但不限于此。根据各种实施方式的焊盘结构可应用于选通焊盘。
焊盘结构可以意指位于非有源区NA的一端并且与上面构建数据驱动芯片212的数据驱动芯片膜210连接的部分,如图2中所示。
同时,第一金属层250可执行将焊盘结构DP连接到数据线DL的功能。第一金属层250可以是将第二金属层260电连接到多条信号线GL和DL之中的数据线DL的链接线220。也就是说,第一金属层250可意指链接线220的一侧的端部部分。还可通过与有源区AA的选通线GL相同的过程来形成第一金属层250。第一金属层250可由与有源区AA的选通线GL相同的材料(诸如,Cu、Mo等)制成。第一金属层250可在与有源区AA相邻的部分通过第一接触孔CH1与数据线DL接触。
可通过与数据线DL相同的过程来形成第二金属层260。第二金属层260可由与有源区AA的选通线GL相同的材料(诸如,Cu、Mo等)制成。第二金属层260可或不可与有源区AA的数据线DL连接。当第二金属层260与数据线DL连接时,可执行将第一金属层250与焊盘结构DL一起连接到数据线DL的功能,从而减小对电流的阻力。第一金属层250和第二金属层260二者可与数据线接触,因为它们可用作较粗的单条线。
可通过包括多个导电球的粘合部分,将第三金属层270与基板248的非有源区NA中键合的第二金属层260和数据驱动芯片膜210电连接。以膜上芯片(COF)的方式,第三金属层270可执行将内置于数据驱动芯片212的数据驱动芯片膜210与数据线DL连接的功能。可通过与有源层AA的像素电极相同的过程来形成第三金属层270。第三金属层270可由与有源区AA的像素电极相同的材料(例如,诸如ITO(铟锡氧化物)等透明材料)制成。
同时,第一金属层250和第二金属层260通过位于第一绝缘层252中的第一接触孔CH1彼此电连接。第二金属层260和第三金属层270通过位于第二绝缘层262中的第二接触孔CH2彼此电连接。
这里,第一接触孔CH1和第二接触孔CH2被设计成没有重叠。也就是说,第一接触孔CH1的位置不同于第二接触孔CH2的位置。
换句话讲,第一接触孔CH1可位于与图4中的有源区相邻的区域中。第二接触孔CH2可位于与图4中的基板248的一个端部侧相邻的区域中。根据各种实施方式的显示装置100可包括如下所述的具有各种形状、数量和位置的第一接触孔CH1和第二接触孔CH2。
第一接触孔CH1和第二接触孔CH2被设计成没有重叠,从而确保足以进行接触的设计余量Wp。
换句话讲,上述实施方式可解决接触电阻增大从而产生因接触孔大小最小化和接触孔CH1和CH2的设计余量不足而造成的断开缺陷的问题。
更具体地,根据所有信号线的纤薄和组成元件的集成,需要使接触孔CH1和CH2最小。当因制造过程中的掩模对准误差而没有充分确保多个金属层250、260和270之间的接触区时,接触电阻可增大。当接触孔CH1和CH2形成在不同于设计位置的区域中从而造成相对陡峭的阶梯时,金属层250、260和270中的至少一个可断开或者金属层之间会出现不良接触。
根据实施方式的显示装置100的焊盘结构DP使得第一接触孔CH1和第二接触孔CH2彼此分开以确保制造过程中的充足设计余量Wp,从而尽管掩模有对准误差,也防止了上述问题。
图6是沿着图2中的部分“E”的F-F'线截取的剖视图。图7是放大图6中的部分“G”的剖视图。
参照图6和图7,显示装置100可包括:显示面板140;焊盘结构DP,其位于所述显示面板140的非有源区NA中;数据驱动芯片膜210,与焊盘结构DP连接的数据驱动芯片212置于其上;源印刷电路板160,其一面的端部与数据驱动芯片膜210连接并且被设置成对应于显示面板140。
焊盘结构DP可包括:第一金属层250,其位于基板248上;两个第一接触孔CH1;第二金属层260,其通过第一接触孔CH1与第一金属层250连接。焊盘结构DP可包括第三金属层270,第三金属层270通过位于第二金属层260上的两个第二接触孔CH2与第二金属层260连接。
可通过包括多个导电球的粘合部分将第三金属层270与位于基板248的非有源区NA中的第二金属层260和数据驱动芯片膜210电连接。
在本说明书中,驱动芯片212可以是数据驱动芯片或源驱动集成电路212,但不限于此。上面构建驱动芯片212的膜210可以是数据驱动芯片膜210,但不限于此。
如图7中所示,第一接触孔CH1和第二接触孔CH2可以分别是多个。第一接触孔CH1和第二接触孔CH2的位置可互不相同。第二接触孔CH2可与显示面板140的一面的端部相邻设置。
采用膜上线(LOF)方式的膜线214可位于数据驱动芯片膜210上。这条膜线214可与焊盘结构DP接触并且键合。
可通过包括导电球CB的粘合部分将焊盘结构DP和数据驱动芯片膜210彼此键合。这里,粘合部分282可以是例如各向异性导电膜(ACF),但不限于此。
第三金属层270可通过导电球CB电连接到数据驱动芯片212。详细地,根据TAB(载带自动键合)的方式通过热压将导电球CB分散在第三金属层270和第二接触孔CH2上,以将数据驱动芯片膜210和第三金属膜270彼此电连接。
此时,问题在于,根据导电球CB的电连接状态,在数据焊盘DP和数据驱动芯片膜210之间没有出现断开缺陷。也就是说,导电球CB的电连接状态可根据导电球CB受压时的状态而变化。例如,当导电球CB没有达到充分受压时,在数据驱动芯片膜210的膜线214和第三金属层270之间可产生接触电阻,使得数据焊盘DP和数据驱动芯片膜210之间可出现断开缺陷。
第一接触孔CH1和第二接触孔CH2的大小可以是大约6μm至8μm。导电球CB的直径可以是大约1μm至3μm,更优选地,2μm。第一接触孔CH1和第二接触孔CH2的重叠区域中的阶梯变得陡峭倾斜,使得导电球CB可根本不受压或者可不充分受压。
另一方面,根据各种实施方式的显示装置100中的第一接触孔CH1和第二接触孔CH2彼此不重叠,使得阶梯没有相对陡峭倾斜。因此,导电球CB可充分受压,从而防止接触电阻增大。
以下,将参照附图描述根据另一个实施方式的焊盘结构的各种示例。
图8A是示意性示出根据另一个实施方式的显示装置的焊盘结构的平面图。图8B是沿着图8A的I-I'线截取的剖视图。
参照图8A和图8B,在显示装置100的焊盘结构中,第一金属层250和第一接触孔CH1的位置可不同于第二接触孔CH2的位置。
更具体地,第一金属层250可位于与第三金属层270不对应的区域。结果,第一接触孔CH1和第二接触孔CH2彼此分开。因为第三金属层270与数据驱动芯片膜210接触,所以第一接触孔CH1和第二接触孔CH2可分别位于与有源区AA相邻的区域和与基板248的一端侧相邻的区域上。第二金属层260可变成连接第一金属层250和第三金属层270的介质。
在这种情况下,第一金属层250和第三金属层270没有彼此重叠,从而有效减小了焊盘结构DP的整体厚度。因为第一接触孔CH1和第二接触孔CH2彼此分开,所以可以确保制造过程中的充足设计余量。
图9A是示意性示出根据另一个实施方式的显示装置的焊盘结构的平面图。图9B是沿着图9A的II-II’线截取的剖视图。
参照图9A和图9B,在显示装置100的焊盘结构中,第一金属层250和第一接触孔CH1的位置可不同于第二接触孔CH2的位置。第一接触孔CH1和第二接触孔CH2可分别是多个,例如,两个。
在这个实施方式中,第一金属层250和第二金属层260之间的接触区域和第二金属层260和第三金属层270之间的接触区域分别增大,使得接触电阻可减小。尽管在接触区域的一部分出现接触缺陷和断开,但接触区域的增大会导致保持接触。
图10A是示意性示出根据本发明的另一个实施方式的显示装置的焊盘结构的平面图。图10B是沿着图10A的III-III'线截取的剖视图。
参照图10A和10B,在显示装置100的焊盘结构中,第一金属层250和第一接触孔CH1的位置可不同于第二接触孔CH2的位置。换句话讲,第一金属层250和第三金属层270可不彼此分开并且顺序地沉积在焊盘结构中。
包括这个焊盘结构DP的显示装置100的优点是确保了充足的接触余量,因为在制造过程中,第一接触孔CH1和第二接触孔CH2相互充分分开。
图11A是示意性示出根据另一个实施方式的显示装置的焊盘结构的平面图。图11B是沿着图11A的IV-IV'线截取的剖视图。
参照图11A和图11B,在显示装置100的焊盘结构中,第一金属层250和第一接触孔CH1的位置可不同于第二接触孔CH2的位置。第一接触孔CH1和第二接触孔CH2可分别是多个,例如,三个。
换句话讲,第一金属层250和第三金属层270可不彼此分开并且顺序地沉积在焊盘结构中。
在这个实施方式中,第一金属层250和第二金属层260之间的接触区域和第二金属层260和第三金属层270之间的接触区域分别增大,使得接触电阻可减小。尽管在接触区域的一部分可出现接触或断开缺陷,但由于接触区域增大,导致可保持金属层之间的接触。
图12A和图12B是示意性示出根据另一个实施方式的显示装置的焊盘结构的平面图(即,当从上方观察时的接触孔)。
参照图12A和图12B,第一接触孔CH1和第二接触孔CH2沿着线交替布置。更详细地,第一接触孔CH1和第二接触孔CH2中的一个或更多个可分别成组并且沿着线交替布置。
这里,在显示装置100的焊盘结构中,第一金属层250和第一接触孔CH1的位置可不同于第二接触孔CH2的位置。
图13A和图13B是示意性示出根据另一个实施方式的显示装置的焊盘结构的平面图。
参照图13A和图13B,第一接触孔CH1和第二接触孔CH2沿着线以曲折(zigzag)方式交替布置。具体地,第一接触孔CH1和第二接触孔CH2中的一个或多个分别成组并且以曲折方式布置。尽管在附图中未描述,但第一接触孔CH1和第二接触孔CH2以不规则的曲折方式布置。
第一接触孔CH1和第二接触孔CH2的曲折方式的布置可使得它们彼此完全分开,从而确保充足的设计余量。
类似于以上实施方式,金属层250、260和270之间的接触区域的增大可导致接触电阻减小,从而焊盘结构DP和显示面板100的可靠性提高。
如上所述,焊盘结构DP可包括三个金属层250、260和270,两个绝缘层252和262分别位于其中两个之间,分别位于绝缘层252和262之间的两个接触孔CH1和CH2不彼此重叠。然而,本发明不限于此。例如,焊盘结构DP可包括四个或更多个金属层和三个或更多个绝缘层。如上所述,第一接触孔CH1和第二接触孔CH2可具有各种形状、各种数量和各种位置。
图14A是示出一般显示装置的焊盘结构和数据驱动芯片膜的剖视图。图14B是示出根据各种实施方式的显示装置的焊盘结构和数据驱动芯片膜的剖视图。
参照图14A,焊盘结构DP和数据芯片驱动膜210可通过包括导电球CB的粘合部分282彼此键合。
第三金属层270可通过导电球CB电连接到数据驱动芯片212。详细地,根据TAB(载带自动键合)的方式通过热压将导电球CB分散在第三金属层270和第二接触孔CH2上,以将数据驱动芯片膜210和第三金属膜270彼此电连接。
在一般显示装置100的情况下,因为接触孔CH1和CH2彼此重叠,所以第一接触孔CH1和第二接触孔CH2的重叠区域处的阶梯差异H1变得相对大,使得设置在接触孔形成区CHA1中的导电球CB可不充分受压。因此,数据驱动芯片膜210的膜线214和第三金属层之间的接触电阻可增大,使得焊盘结构DP和数据驱动芯片膜210之间会出现断开缺陷。
同时,参照图14B,根据各种实施方式的显示装置100中的第一接触孔CH1和第二接触孔CH2没有彼此重叠,使得接触孔形成区CHA2中的阶梯差异H2相对小,并且可不相对陡峭地倾斜。因此,导电球CB可充分受压,从而防止接触电阻增大并且通过焊盘结构DP和数据驱动芯片膜210之间进行的稳定连接来提高显示面板100中的焊盘结构DP的可靠性。
总之,显示装置100的焊盘结构DP可被设计成,第一接触孔CH1和第二接触孔CH2没有彼此重叠,以通过减小接触孔形成区CHA2中的阶梯差异从而减小接触电阻来确保充足的设计余量并且提高形成接触孔CH1和CH2的过程的可靠性。
尽管目前为止已经参照附图描述了各种实施方式,但本发明不限于此。
关于一个实施方式,一种显示装置可包括:多条信号线,其包括布置在基板的显示区中的数据线和选通线;焊盘结构,其位于所述基板的非有源区中并且与所述信号线连接,其中,所述焊盘结构包括两个或更多个金属层、以及绝缘层,所述绝缘层位于所述金属层之间并且具有使所述金属层之中的两个金属层彼此接触的一个或更多个接触孔,分别位于所述绝缘层中的所述接触孔没有彼此重叠。
所述焊盘结构可以是与所述多条信号线之中的所述数据线连接的数据焊盘结构。
所述焊盘结构还可包括:第一金属层、第二金属层和第三金属层,所述第一金属层和所述第二金属层通过第一接触孔彼此连接,所述第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层和所述第三金属层通过第二接触孔彼此连接,所述第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第一接触孔的位置不同于所述第二接触孔的位置。
所述第一金属层可以是将所述第二金属层电连接到所述数据线的链接线。
可通过包括多个导电球的粘合部分将所述第三金属层与位于所述基板的所述非有源区中的所述第二金属层和数据驱动芯片膜电连接。
所述第一金属层和所述第一接触孔可位于与所述第三金属层所处的区域不同的区域。
所述第一金属层和所述第一接触孔可位于与所述第三金属层所处的区域对应的区域。
所述第一接触孔可位于与所述有源区相邻的区域并且所述第二接触孔位于与所述基板的一端侧相邻的区域。
所述信号线可包括所述数据线和与所述数据线交叉的所述选通线,所述第一金属层由与所述选通线相同的材料制成,所述第二金属层由与所述数据线相同的材料制成,所述第三金属层由与像素电极相同的材料制成。
关于另一个实施方式,一种焊盘结构可包括:多个金属层;两个或更多个绝缘层,其设置在所述金属层之间,各绝缘层具有使所述多个金属层之中的两个金属层彼此接触的一个或更多个接触孔,其中,分别位于所述绝缘层中的每个中的所述接触孔没有彼此重叠。
所述金属层可包括第一金属层、第二金属层和第三金属层,其中,所述第一金属层和所述第二金属层通过第一接触孔彼此连接,所述第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层和所述第三金属层通过第二接触孔彼此连接,所述第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第一接触孔的位置不同于所述第二接触孔的位置。
所述第一金属层和所述第一接触孔可位于与所述第三金属层所处的区域不同的区域。
所述第一金属层和所述第一接触孔可位于与所述第三金属层所处的区域对应的区域。
所述第一接触孔和所述第二接触孔可交替布置。
所述第一接触孔和所述第二接触孔可以曲折方式布置。
关于另一个,一种在显示装置中形成焊盘结构的方法可包括:在基板上提供多个金属层;提供两个或更多个绝缘层,各绝缘层设置在所述金属层之间并且具有使所述多个金属层之中的两个金属层彼此接触的一个或更多个接触孔,其中,分别设置在所述绝缘层中的每个中的所述接触孔没有彼此重叠。
所述金属层可包括第一金属层、第二金属层和第三金属层,其中,所述第一金属层和所述第二金属层通过第一接触孔彼此连接,所述第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层和所述第三金属层通过第二接触孔彼此连接,所述第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第一接触孔的位置不同于所述第二接触孔的位置。
所述第一金属层和所述第一接触孔可位于与所述第三金属层所处的区域不同的区域。
所述第一接触孔和所述第二接触孔可交替布置。
所述第一接触孔和所述第二接触孔可以曲折方式布置。
另外,由于诸如“包括”、“包含”和“具有”的术语意指可存在一个或更多个对应组件(除非特别做相反描述),因此应当理解,可包括一个或更多个其它组件。除非做相反定义,否则所有术语在技术上、科学上或者在其它方面与本领域技术人员理解的含义一致。由字典定义的一般使用的术语等应当被理解为,它的含义与相关描述的背景下的含义等同,并且不应当以理想或过度正式的含义进行理解,除非在本说明书中清楚定义。
尽管已经出于例证目的描述了本发明的实施方式,但在不脱离本发明的范围的情况下,可以进行各种修改、添加和替代。因此,本发明中公开的实施方式不旨在示出本发明的技术思路的范围,并且本发明的范围不受实施方式限制。本发明的范围应当是以与随附权利要求等同的范围内包括的所有技术思路属于本发明这样的方式基于权利要求书进行理解。

Claims (10)

1.一种用于显示装置中的焊盘结构,该焊盘结构包括:
多个金属层,所述多个金属层包括第一金属层、第二金属层和第三金属层,
其中,所述第一金属层和所述第二金属层通过多个第一接触孔彼此连接,所述多个第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层位于所述第一绝缘层和通过所述多个第一接触孔暴露的所述第一金属层上,
所述第二金属层和所述第三金属层通过多个第二接触孔彼此连接,所述多个第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第三金属层位于所述第二绝缘层和通过所述多个第二接触孔暴露的所述第二金属层上,
所述第一接触孔和所述第二接触孔没有彼此重叠,
所述第一金属层和所述多个第一接触孔没有与所述第三金属层重叠,并且
所述第一金属层由与所述显示装置的选通线相同的材料制成,所述第二金属层由与所述显示装置的数据线相同的材料制成,所述第三金属层由与所述显示装置的像素电极相同的材料制成。
2.根据权利要求1所述的焊盘结构,其中,当从上方观察所述第一接触孔和所述第二接触孔时,所述第一接触孔、或所述第二接触孔、或所述第一接触孔和所述第二接触孔二者偏离所述线。
3.根据权利要求2所述的焊盘结构,其中,所述第一接触孔和所述第二接触孔以曲折方式布置。
4.一种显示装置,该显示装置包括:
多条信号线,所述多条信号线包括布置在基板的显示区中的数据线和选通线;
焊盘结构,所述焊盘结构位于非有源区中并且与所述信号线连接,其中,所述焊盘结构还包括:
多个金属层,所述多个金属层包括第一金属层、第二金属层和第三金属层,
其中,所述第一金属层和所述第二金属层通过多个第一接触孔彼此连接,所述多个第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层位于所述第一绝缘层和通过所述多个第一接触孔暴露的所述第一金属层上,
所述第二金属层和所述第三金属层通过多个第二接触孔彼此连接,所述多个第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第三金属层位于所述第二绝缘层和通过所述多个第二接触孔暴露的所述第二金属层上,
所述第一接触孔和所述第二接触孔没有彼此重叠,
所述第一金属层和所述多个第一接触孔没有与所述第三金属层重叠,并且
所述第一金属层由与所述选通线相同的材料制成,所述第二金属层由与所述数据线相同的材料制成,所述第三金属层由与像素电极相同的材料制成。
5.根据权利要求4所述的显示装置,
其中,所述焊盘结构是与所述多条信号线之中的所述数据线连接的数据焊盘结构。
6.根据权利要求4所述的显示装置,
其中,所述第一金属层是将所述第二金属层电连接到所述数据线的链接线。
7.根据权利要求4所述的显示装置,
其中,所述第三金属层与所述第二金属层电连接,
所述第三金属层通过包括多个导电球的粘合部分电连接到位于所述基板的非有源区中的数据驱动芯片膜。
8.根据权利要求4所述的显示装置,
其中,所述第一接触孔位于与所述显示区相邻的区域并且所述第二接触孔位于与所述基板的一端侧相邻的区域。
9.一种在显示装置中形成焊盘结构的方法,该方法包括:
在基板上提供多个金属层,以在所述基板的显示区中形成多条信号线;
提供两个或更多个绝缘层,各绝缘层设置在所述金属层之间并且具有使所述多个金属层之中的两个金属层彼此接触的一个或更多个接触孔,
其中,分别位于所述绝缘层中的每个中的所述接触孔没有彼此重叠,
其中,所述多个金属层包括第一金属层、第二金属层和第三金属层,
其中,所述第一金属层和所述第二金属层通过多个第一接触孔彼此连接,所述多个第一接触孔位于所述第一金属层和所述第二金属层之间的第一绝缘层中,所述第二金属层位于所述第一绝缘层和通过所述多个第一接触孔暴露的所述第一金属层上,
所述第二金属层和所述第三金属层通过多个第二接触孔彼此连接,所述多个第二接触孔位于所述第二金属层和所述第三金属层之间的第二绝缘层中,所述第三金属层位于所述第二绝缘层和通过所述多个第二接触孔暴露的所述第二金属层上,
所述第一接触孔和所述第二接触孔没有彼此重叠,
所述第一金属层和所述多个第一接触孔没有与所述第三金属层重叠,并且
所述第一金属层由与所述显示装置的选通线相同的材料制成,所述第二金属层由与所述显示装置的数据线相同的材料制成,所述第三金属层由与所述显示装置的像素电极相同的材料制成。
10.根据权利要求9所述的方法,其中,所述第一接触孔和所述第二接触孔以曲折方式布置。
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EP3002629A1 (en) 2016-04-06
KR20160040338A (ko) 2016-04-14

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