CN105474388A - 电磁干扰互连低的裸片封装体 - Google Patents

电磁干扰互连低的裸片封装体 Download PDF

Info

Publication number
CN105474388A
CN105474388A CN201480038222.0A CN201480038222A CN105474388A CN 105474388 A CN105474388 A CN 105474388A CN 201480038222 A CN201480038222 A CN 201480038222A CN 105474388 A CN105474388 A CN 105474388A
Authority
CN
China
Prior art keywords
lead
wire
nude film
die package
package body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480038222.0A
Other languages
English (en)
Other versions
CN105474388B (zh
Inventor
S·S·卡希尔
E·A·圣胡安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rosenberger Hochfrequenztechnik GmbH and Co KG
Original Assignee
Rosenberger Hochfrequenztechnik GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rosenberger Hochfrequenztechnik GmbH and Co KG filed Critical Rosenberger Hochfrequenztechnik GmbH and Co KG
Publication of CN105474388A publication Critical patent/CN105474388A/zh
Application granted granted Critical
Publication of CN105474388B publication Critical patent/CN105474388B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6611—Wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6638—Differential pair signal lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/4556—Disposition, e.g. coating on a part of the core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45565—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554—Coating
    • H01L2224/45599—Material
    • H01L2224/4569—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4801—Structure
    • H01L2224/48011—Length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901—Structure
    • H01L2224/4903—Connectors having different sizes, e.g. different diameters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/4917—Crossed wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8593—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85931—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by chemical means, e.g. etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8593—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85935—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8593—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape
    • H01L2224/85935—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing
    • H01L2224/85939—Reshaping, e.g. for severing the wire, modifying the wedge or ball or the loop shape by heating means, e.g. reflowing using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H01L2225/06537—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

一种裸片封装体，其具有提供电磁干扰降低的连接至裸片的引线结构。连接至所述裸片的混合阻抗的引线包括：第一引线，其具有第一金属芯(302)、包围该第一金属芯(302)的电介质层(300,304)和连接至接地端的第一外金属层(306)；以及第二引线，其具有第二金属芯(302)、包围该第二金属芯(302)的第二电介质层(300,304)和连接至接地端的第二外金属层(306)。各引线降低了对EMI和串扰的敏感性。

Description

电磁干扰互连低的裸片封装体
技术领域
本发明涉及提供电磁干扰降低的连接至裸片的新颖引线结构。通过本发明的实现，降低了引线之间的串扰、以及对封装体内部或外部的电磁辐射所产生的噪声的敏感性。
此外，本发明涉及为了连接与一个或多个裸片相连接的电介质涂布引线所形成的新颖的多个接地层。
背景技术
电磁干扰导致性能降低对于封装裸片而言、特别是对于具有以千兆赫频率进行工作的输入/输出(IO)的裸片而言，是越来越普遍的问题。许多集成电路产生不期望量的EMI。通常，集成电路所产生的噪声源自于裸片及其经由封装体向引脚的连接。由于EMI耦合至相邻组件和集成电路，因此EMI与这些相邻组件和集成电路的个体性能发生干扰，而这可能会影响系统的整体性能。由于EMI的负面影响并且由于对可接受的辐射EMI的水平进行严格的监管限制，因此期望遏制或抑制集成电路所产生的EMI。
诸如引线的分离或与利用屏蔽件的隔离等的解决方案不总是可用的或足够的。此外，由于IC封装水平的主要关注是信号完整性和功能性，因此经常忽略该水平的EMI解决方案。由于封装水平的EMI解决方案将有助于减少针对“下游”或附加的解决方案的需求，因此具有封装水平的EMI解决方案将是有益的。
发明内容
考虑到现有技术的这些问题和不足，因此本发明的目的是提供一种紧凑型裸片封装体，特别是提供一种具有两个或更多个引线从而提供优良的信号完整性和功能性的堆叠型裸片封装体和/或BGA封装体。
在本发明中实现本领域技术人员将明白的上述和其它目的，其中本发明涉及一种EMI衰减所用的裸片封装体，包括：裸片，其具有多个连接压焊点；裸片衬底，其支撑多个连接元件；第一引线，其包括具有第一金属芯直径的第一金属芯、包围所述第一金属芯的具有第一电介质厚度的第一电介质层和包围所述第一电介质层的第一外金属层，其中所述第一外金属层贴装接地；以及第二引线，其包括具有第二金属芯直径的第二金属芯、包围所述第二金属芯的具有第二电介质厚度的第二电介质层和包围所述第二电介质层的第二外金属层，其中所述第二外金属层贴装接地，使得对所述第一引线和所述第二引线之间的EMI和串扰的敏感性降低。
此外，本发明涉及一种裸片封装体，包括：裸片，其具有多个连接压焊点；裸片衬底，其支撑多个连接元件；第一引线，其包括具有第一金属芯直径的第一金属芯、包围所述第一金属芯的具有第一电介质厚度的第一电介质层和包围所述第一电介质层的第一外金属层，其中所述第一外金属层贴装至第一接地层；以及第二引线，其包括具有第二金属芯直径的第二金属芯、包围所述第二金属芯的具有第二电介质厚度的第二电介质层和包围所述第二电介质层的第二外金属层，其中所述第二外金属层贴装至第二接地层，使得所述第一引线和所述第二引线降低了对所述第一引线和所述第二引线之间的EMI和串扰的敏感性。所述第一引线可以从第一裸片延伸至所述裸片衬底上的所述多个连接元件其中之一，以及/或者所述第二引线可以从第二裸片连接至所述裸片衬底上的所述多个连接元件其中之一。所述第二接地层可以与所述第一接地层重叠、或者可以与所述第一接地层不重叠。在重叠的情况下，可以在所述第一接地层和所述第二接地层之间配置维持电气隔离的居间层。
根据本发明的裸片封装体可以是具有第一裸片和第二裸片的堆叠型裸片封装体，所述第一裸片和所述第二裸片各自具有多个连接压焊点；所述第一引线从所述第一裸片的多个连接压焊点其中之一延伸至所述裸片衬底上的所述多个连接元件其中之一或所述第二裸片上的多个连接压焊点其中之一，并且所述第二引线从所述第二裸片的多个连接压焊点其中之一延伸至所述裸片衬底上的所述多个连接元件其中之一或所述第一裸片的多个连接压焊点其中之一。
从属权利要求涉及根据本发明的裸片封装体的有利实施例，并且可以单独地或组合地添加这里所公开的各个特征。
附图说明
特别是在所附权利要求书中，陈述了被认为是新颖的本发明的特征以及本发明的元素特性。附图仅是为了例示目的并且不是按比例绘制的。然而，关于组织和操作方法这两者，可以通过参考以下结合附图所进行的详细说明来最好地理解本发明本身，其中：
图1是包括具有外接地金属的电介质涂布引线的细间距低串扰裸片封装体的例示；
图2示出具有外接地金属的低串扰重叠电介质涂布引线；
图3示出堆叠型裸片封装体中所使用的低串扰引线；
图4示出裸片到裸片的实施例或封装体到封装体的实施例中所使用的低串扰引线；
图5是示出用于制造具有外接地金属的电介质涂布引线的方法步骤的框图；
图6示出用于制造具有外接地金属的电介质涂布引线的减成法；
图7示出包括具有外接地金属的电介质涂布引线的BGA封装体；
图8示出包括具有外接地金属的电介质涂布引线的引线框架封装体的一部分；
图9A和9B示出基于频率的串扰水平的S参数测量；
图10A～10D分别示出与具有电介质涂层和外接地金属层的单端引线和差分引线相关联的EM场；
图11a和11b示出根据本发明的、涂布有电介质和金属的引线连接至可以重叠或者可以不重叠的单独接地层的裸片封装体；
图12示出根据本发明的具有两个接地层的裸片封装体；以及
图13示出两个接地层分别形成RF接地屏蔽件和DC功率屏蔽件的又一示例实施例。
具体实施方式
在说明本发明的优选实施例时，这里将参考附图1～13，其中相同的附图标记指代本发明的相同特征。
可以使用具有电磁屏蔽并且在金属芯和可接地的导电外层之间具有一个或多个中间电介质层的引线来提高封装体电气性能。在图1中示出该情况，其中图1示出引线156具有不同的长度的包括贴装至衬底154的裸片152的封装体150。如显而易见，由于工艺考虑，衬底154上的连接压焊点158通常采用与芯片侧的间距相比更大的间距。裸片压焊点间距通常由引线接合机可实现的间距来定义。在衬底侧，间距由印刷电路板(PCB)类型工艺的平版印刷可重复性以及焊料、引脚或互连元件配置精度来定义。实际上，与在封装体上相比，在芯片上配线更加紧密地间隔开。这意味着，随着裸片大小缩小，在配线上特别是在裸片附近，发生更多不期望的电磁场耦合(串扰)。除降低封装体内电磁干扰(EMI)外，如这里所述构建成的引线对外部(对封装体)EMI的敏感性降低，并且还将大幅降低了电磁辐射。
如从图2看出，半导体裸片封装系统100可被形成为具有由于引线构造所引起的电磁辐射和串扰低的引线110、112和114。衬底102上所安装的裸片120包括裸片120所需的信号、功率或其它功能所用的多个连接压焊点122。衬底102可以包括直接地或者经由导电引线框架、填充通孔、导电走线或第二级互连等提供封装体中的导电路径的导电压焊点104。引线110、112和114连接至导电压焊点104，并且如图所示，可以具有大致不同的长度。如从图2看出，引线狭窄地间隔开，并且能够相互交叉或处于彼此下方(例如，引线110和112被示出为交叉)，从而为不期望的电磁耦合提供了许多机会。
在例示实施例中，引线110、112和114具有内芯和外金属层。例如，引线110、112和114可以沿着其长度具有定义直径的金属芯，其中该金属芯顺次涂布有电介质层和导电金属层。与无附加的电介质涂层和金属涂层的相同大小的裸引线相比，引线110、112和114发出较少的辐射，对外部(对封装体)EMI不太敏感，并且不易发生串扰。在特定实施例中，由于如所公开的引线构造的优良电气特性，因此长度大大不同但芯直径相同的引线与裸线相比具有大致相同的噪声降低。与无电介质和包围的金属层的裸引线相比，从性能上，所测量到的噪声降低已被示出为大于5dB直至高达30dB。在特定实施例中，抗EMI性在引线长度的范围内有效，其中两个引线能够具有相同的截面结构和阻抗，但一个引线高达另一引线的长度的十(10)倍大同时仍具有相同的EMI特性。
导致不想要的串扰的电磁场耦合不仅仅在并排的引线上发生，而且还在堆叠型结构中的彼此靠近的引线上发生。在如图3所示的堆叠型裸片结构中实现该情形，其中图3示出具有示例性引线164a～164d和166a～166d的包含裸片162a～162d的堆叠状裸片封装体160，其中代替如这里所述的涂布有电介质层和导电金属层的引线，在使用裸线的情况下，这些引线164a～164d和166a～166d将从并排的、位于上方和位于下方的引线产生不可接受的串扰。同样，图4示出具有裸片到裸片引线连接174和裸片到衬底连接176的裸片叠层170和172。在串扰降低的单独安装的封装系统180、182中，还可能存在直接裸片到裸片连接178。
半导体裸片封装体中所使用的电介质涂布引线可被形成为具有变化的电介质厚度。可以改变芯直径和电介质厚度这两者。在特定实施例中，还可以改变所沉积的电介质的成分。这样例如使得能够将具有优良的防蒸汽层或抗氧降解性等的高性能电介质薄薄地沉积在低成本的电介质材料所形成的厚的层上。在例示实施例的另一方面中，引线110、112和114(参考图2和3)在内芯和外金属层内具有变化的电介质厚度，从而提供明显不同的阻抗。例如，引线110可以沿着其长度具有定义直径的金属芯，其中该金属芯顺次涂布有薄电介质层和导电金属层。由于如此得到的低阻抗和低电容使功率跌落下降，因此这些引线110适合功率的传送。可选地，引线112具有适合信号数据的传输的厚得多的电介质层，而引线114具有中间厚度的电介质层。在特定实施例中，由于如所公开的引线构造的电气特性优良，因此长度大大不同但芯直径相同的引线尽管长度改变了50％以上，但可以具有大致相同的阻抗(在目标阻抗的10％内)。例如，引线116尽管为引线110的两倍长，但可以具有与引线110约相同的阻抗。在特定实施例中，引线差异可能甚至更大，其中两个引线具有相同的截面结构和阻抗，但一个引线的长度为另一引线的长度的十(10)倍。
通常，薄的电介质层将提供低阻抗，从而有益于功率线应用；厚的电介质通常有益于信号完整性；并且引线上的外金属层可以有利地连接至相同的接地端。芯直径和电介质厚度的组合是可以的，并且可以进行一系列的这些步骤以实现阻抗不同的引线。在特定实施例中，可以期望在功率线上具有大的芯以增加功率处理能力、降低功率线温度、以及/或者进一步降低电源以及将加剧接地反弹或功率跌落的接地线上的任何电感。
由于许多封装体可以受益于具有三(3)个以上的不同电介质厚度的引线，因此中间厚度的电介质层也是有用的。例如，具有中间电介质厚度的引线可用于连接阻抗大大不同的源和负载以使功率传送最大化。例如，10欧姆的源可以连接至具有20欧姆的引线的40欧姆的负载。此外，由于电介质的成本可能高，因此可以使用厚的电介质来使重要的信号路径相互连接，而可以利用厚度与功率引线相比更大但与重要的信号引线相比更小(中间)的电介质层来涂布状况或重置不太重要的引线等。有利地，这样可以减少电介质沉积材料的成本和时间。
可以与焊线直径相组合地选择电介质涂层的精确厚度，以针对各引线实现特别期望的阻抗值。
Z 0 = L C = 138 ϵ r · l o g ( b a ) - - - ( 1 )
在等式(1)中给出同轴线的特性阻抗，其中：L是每单位长度的电感，C是每单位长度的电容，a是焊线的直径，b是电介质的外径，并且εr是同轴电介质的相对介电常数。
如图5所示，在一个实施例中，利用或无需利用一个或多个接地层的具有外接地金属的电介质涂布引线的制造可以使用框图200所示的步骤来进行。在第一步骤202中，清洗裸片和衬底上的连接压焊点。接着，使用引线接合机使裸片连接至连接压焊点(204)。可选地，可以贴装第二直径的配线(206)(例如，适合功率连接的较大直径的配线)，或者可以对裸片的区域进行掩蔽或保护以允许进行选择性沉积(步骤208)。可以沉积成分相同或不同的一层或多层电介质(步骤210)，之后对电介质的一部分进行选择性激光或热烧蚀或者化学去除，以使得能够到达在电介质沉积步骤(210)中所覆盖的接地接点(212)。该步骤是可选的，这是因为，在一些实施例中，不需要接地通孔。由于可以通过电容耦合建立虚拟RF接地、并且由于针对厚度值的频率依赖性(Er的函数)使得能够经由电容耦合进行接地建立，因此这对于以较高频率进行工作的裸片而言尤其如此。之后进行金属化(步骤214)，从而利用形成引线的最外金属化层的金属层覆盖电介质，并且还使引线接地。可以重复多次整个处理(步骤216)，从而用于使用选择性沉积技术的实施例，并且特别用于支撑多裸片或者复杂的且阻抗发生变化的引线的实施例。在最后步骤(步骤218)中，对于非腔体封装体，可以使用包覆成型件来封装引线。封装后的引线可以用在美国专利6,770,822和美国专利公开2012/0066894中所述的高频器件封装体中，其中这两者的内容通过引用全部包含于此。
在特定实施例中，可以对所述的工艺进行修改和添加。例如，可以通过使用化学(电泳)、机械(表面张力)、接触反应(底漆)、电磁[UV,IR]、电子束、其它适当技术的各种方法来实现提供电介质的共形涂层。由于电泳聚合物可以依赖于如下的自限反应，因此这些电泳聚合物特别有利，其中这些自限反应可以通过调整工艺参数以及/或者针对电泳涂捕溶液的简单加成、浓度、化学、热或定时变化，来容易地沉积精确的厚度。
在其它实施例中，可以使用电介质预涂焊线来形成引线。尽管市售的涂布配线通常在电介质厚度方面与创建例如50欧姆的引线所需的配线相比在电介质厚度上更薄，但可以使用以上所论述的电介质沉积步骤来增加电介质厚度以设置期望的阻抗。使用这些预涂配线可以简化创建共轴所需的其它工艺步骤，并且可以使得所需的气相沉积电介质的层更薄且处理时间更快，从而创建接地通孔。可以使用预涂焊线来防止狭窄地间隔开或交叉的引线发生短路。在特定实施例中，预涂焊线可以具有由光敏材料制成的电介质以使得能够进行选择性图案化技术。
在其它实施例中，可以使用电介质聚对二甲苯。聚对二甲苯(Parylene)是用作水分阻挡层和电介质阻抗层的各种化学气相沉积聚(对苯二亚甲基)聚合物的商品名称。可以使用改进的聚对二甲苯沉积系统在生长受限的缩合反应中形成聚对二甲苯，其中在该聚对二甲苯沉积系统中，使裸片、衬底和引线与照相底板对齐，从而使得EM辐射(IR、UV或其它)能够以精确方式入射，这样引起电介质的选择性生长率。有利地，这样使针对用以创建接触通孔、聚对二甲苯的大量去除等的工艺的需求为最低限度或者不需要这些工艺。
已知聚对二甲苯和其它电介质在存在氧、水蒸汽和热的情况下由于氧断裂而发生降解。损坏可能受到形成优良的氧蒸汽阻挡层的金属层所限制，其中厚度为3～5微米的薄层能够形成真正的气密界面。可选地，如果选择性地去除了金属、或者由于电气、热或制造要求因而金属没有沉积在特定区域中，则可以使用各种基于聚合物的蒸汽氧阻挡层，其中聚乙烯醇(PVA)是广泛地使用的聚合物。可以对这些聚合物进行顶部密封、丝网印刷、用蜡纸印刷、门式分配、喷涂到将暴露至氧或水蒸汽环境的聚对二甲苯表面上。有利地，由于可能需要高成本的聚对二甲苯或其它对氧敏感的更厚层，因此使用防蒸汽层聚合物可以是降低成本策略的一部分。
如应当理解，所述的所有方法步骤全部受益于各种选择性沉积技术。选择性沉积可以通过物理掩蔽、直接聚合物沉积、光致抗蚀法、或者用于在沉积时确保金属芯、电介质层或其它最外层上的差分沉积厚度的任何其它适当方法。尽管选择性沉积允许使用加成法来构建引线，但还允许去除电介质或金属以形成阻抗不同的互连件的减成技术。例如，可以适当地对利用一个或多个裸片所填充的封装体进行引线接合，以使所有的封装体和器件压焊点相互连接。如针对例示裸片封装体的制造所用的步骤和结构的图6看出，可以将电介质涂层300以预定厚度沉积到焊线金属导体302上(步骤A)，其中该预定厚度的电介质是二次互连阻抗所需的。例如可以通过蚀刻步骤(步骤B)去除二次阻抗焊线电介质，之后进行第二涂层304的沉积(步骤C)，之后进行这两个互连件的金属化306(步骤D)。该减成工艺将创建两个明显不同的阻抗的焊线。
在针对图7所示的实施例中，说明包括具有所选择的多个阻抗的电介质和金属涂布引线412、414的球栅阵列(BGA)封装体410。BGA是广泛地用于集成电路的表面安装封装，并且由于BGA的底表面整体可用于连接压焊点，因此BGA与双列直插式、引线框架或其它扁平封装体相比通常可以提供更多的互连引脚。在许多类型的BGA封装体中，将裸片416贴装至具有连接至连接压焊点的可填充通孔420的衬底418。焊线412、414可用于使顶侧的裸片416连接至压焊点/通孔420，结果提供从衬底418的顶侧向底部的电气连接。在BGA封装件中，利用粘性焊剂将焊料球422贴装至封装体的底部并且保持在适当位置，直到焊接至印刷电路板或其它衬底为止。如这里所述，可以利用具有电介质层和外部可接地的金属层的改进了的引线来替换传统的BGA封装体的焊线。这些引线可以在内芯和外金属层内具有变化的电介质厚度，并且可以选择性地优化这些引线以具有特定阻抗，从而可被选择成至少部分基于电介质层厚度而不同或良好地匹配。如从图7看出，支撑长的引线412和短的引线414这两者。
更详细地，改进了的BGA封装体的组件可以要求将裸片以面朝上的方式贴装至衬底，从而支撑衬底中的在通孔周围以邻接方式形成的连接压焊点。针对所需的各互连件适当地对该组件进行引线接合，其中在衬底上的连接压焊点和裸片上的连接压焊点之间形成焊线。低频率和功率的输入连接至低频率的信号引线，而高频率的输入和输出连接至高频率的信号引线。在一些实施例中，低频率和功率的输入的厚度可以不同于高频率的信号引线的厚度。然后对组件进行任何基本保形的电介质材料的涂布。由于聚对二甲苯的低成本、便于真空沉积和优良的性能特性，因此可以使用聚对二甲苯。可以通过蚀刻、热降解或激光烧蚀来选择性地去除电介质层的在引线框架贴装点附近的一小部分，从而形成向接地接触点或接地屏蔽层的电气连接。同样，可以在裸片连接压焊点附近去除电介质层的一小部分，以允许接地连接。在将金属化层涂敷到电介质层的顶部之后在结构中接地，从而形成接地屏蔽。应当考虑到趋肤深度和DC电阻问题来选择优选的金属层的厚度，并且该厚度应主要包括诸如银、铜或金等的优良电气导体。对于大多数应用，1微米的涂层厚度对于功能而言是足够的，但更厚的涂层有助于使引线之间的串扰为最低限度。可以通过光刻法或其它掩蔽方法与镀法或其它选择性沉积方法的组合来在定义区域中添加这些涂层。可以通过将包覆成型件或盖放置在裸片上、之后进行切割(切单)并进行测试，来完成封装体。
可选地，在针对图8所示的实施例中，可以通过形成包含单独的封装部位和外侧框架部分的二维阵列的引线框架带材来制造包括从裸片延伸至引线框架的基于低成本的引线框架的裸片封装体440。引线框架制造是传统的，并且可以包括通过蚀刻、冲压或电沉积的单独引线的形成。可以将引线框架带材放置在包括但不限于注塑成型或传递成形设备的模具中。将适当的电介质材料(优选为诸如市售的环氧模塑料)注入、泵入或传递到模具内，以实现引线框架/模具材料复合结构。模具材料的性质对于这些模具材料的介质常数、损耗切线和电色散性质以及这些模具材料的温度、湿度和其它机械性能属性而言很重要。
对如此得到的复合引线框架带材上的各封装部位清洗脱模材料和/或溢料飞边，并且准备好将金属饰面沉积在引线框架的暴露的金属部分上。这可以通过诸如浸没或电镀等的镀技术来实现，并且将选择这些金属以用于腐蚀抑制并且容易进行引线接合。这种涂饰的示例是薄的镍层(以供保护)，之后是金层(向焊线添加保护和能力)。然后，可以利用贴装至基底的所需裸片填充如此得到的模制引线框架带材的各封装部位，其中针对特定封装应用的机械性质和热性质选择裸片贴装材料。然后，针对所需的各互连件适当地对如此得到的组件进行引线接合，其中在引线框架上的引线和裸片上的连接压焊点之间形成焊线。低频率和功率的输入连接至低频率的信号引线，而高频率的输入和输出连接至高频率的信号引线。在一些实施例中，低频率和功率的输入的厚度可以不同于高频率的信号引线的厚度。
如上述的BGA封装体410那样，然后对所填充的引线框架带材进行包括聚对二甲苯的任何基本保形的电介质材料的涂布。在聚对二甲苯的情况下，可以优选利用诸如具有丙烯酸粘合剂的真空兼容的聚酰亚胺等的胶带或者相似材料对封装体的底部进行掩蔽以防止沉积到引线的最终将贴装至PCB的区域上。这将便于在后续步骤进行更容易的焊接。可以通过蚀刻、热降解或激光烧蚀来选择性地去除电介质层的在引线框架贴装点附近的一小部分，从而形成向接地接触点或接地屏蔽层的电气连接。同样，可以在裸片连接压焊点附近去除电介质层的一小部分，以允许接地连接。在将金属化层涂敷到电介质层的顶部之后在结构中接地，从而形成接地屏蔽。应当考虑到趋肤深度和DC电阻问题来选择优选的金属层的厚度，并且该厚度应主要包括诸如银、铜或金等的优良电气导体。对于大多数应用，1微米的涂层厚度对于功能而言是足够的，但更厚的涂层有助于使引线之间的串扰为最低限度。可以通过光刻法或其它掩蔽方法与镀法或其它选择性沉积方法的组合来在定义区域中添加这些涂层。可以通过将包覆成型件或盖放置在裸片上、之后进行切割(切单)并进行测试，来完成封装体。
示例1-串扰性能
图9A是示出作为裸焊线502、30欧姆的同轴线缆504和50欧姆的同轴线缆506的频率的函数的串扰比较的曲线图500。这两个同轴引线相对于无屏蔽的互连线在串扰/隔离方面表现出约25dB的改进。在这方面，根据本发明所制备的甚至不匹配的同轴引线也优于无屏蔽的裸引线。
图9B是示出裸焊线512、514的行为与50欧姆的同轴引线516、518的行为在时域方面的比较的曲线图510。与图9A所示的频率结果一致地，噪声电压下降了高达12倍(串扰/隔离)520，并且解决时间响应提高了7倍522(允许宽度增加)。
图10A～10D分别示出与具有以及不具有电介质涂层和外接地金属层的单端引线和差分引线相关联的EM场振幅的空间振幅标绘图。图10A示出单端焊线602的振幅标绘图600。如图所示，在沿着焊线的y轴的点处的EM场振幅显著。图10B示出单端微同轴线612的振幅标绘图610。如显而易见，同轴引线与裸引线相比具有大幅降低的电磁辐射。
共通地用于裸引线以提高抗噪度的技术对于差分对而言特别实用。通常，利用处于相反极性的信号所驱动的一对引线将经受大致等同的噪声环境。在以差分方式将这两个信号相加到一起的情况下，可以执行抵消共模噪声。然而，如果如针对许多对引线的细微间距配置而可能发生的、噪声环境不等同，则邻近的噪声源在差分对中的最近邻上与在更远邻上相比可能感应更大的信号。由于噪声在到达信号线之前被高度衰减，因此屏蔽的微同轴对如此在更大程度上不受噪声影响。图10C示出差分焊线622的空间振幅标绘图620。图10D示出差分微同轴线632的空间振幅标绘图630。该标绘图呈现几乎完全屏蔽、即电磁辐射的发射可忽略。
如从图11a和11b看出，半导体裸片封装系统1100可被形成为具有多个分离或重叠的接地层。引线1110、1112和1114可被制造成由于引线构造和向接地层的连接因而具有低的电磁辐射和串扰。裸片衬底1102上所安装的裸片1120包括裸片1120所需的信号、功率或其它功能所用的多个连接压焊点1122。裸片衬底可以包括直接地或者经由导电引线框架、填充通孔、导电走线或第二级互连等提供封装体中的导电路径的导电压焊点1104。引线1110、1112和1114连接至导电压焊点1104，并且如图所示，可以具有大致不同的长度。
在例示实施例中，引线1110和1112具有连接至第一接地层1130的内芯和外金属层。作为对比，也具有内芯和外金属层的引线1114连接至与第一接地层1130分开且不同于第一接地层1130的第二接地层1132。同样，图11b示出除接地层1134和1136在物理上重叠外、设计与封装体1100等同的封装体1101。然而，由于可以使用电介质涂层1138(被示出为部分去除)来使接地层1134和1136彼此隔离，因此这些接地层从电气上不同。如应当理解，引线1110、1112和1114可以沿着其长度具有定义直径的金属芯，其中该金属芯顺次涂布有电介质层和导电金属层。
与无附加的电介质涂层和金属涂层的大小相同的裸引线相比，引线1110、1112和1114发射较少的辐射，对外部(对封装体)EMI不太敏感，并且不易发生串扰。在特定实施例中，由于如所公开的引线构造的优良电气特性，因此长度大大不同但芯直径相同的引线与裸线相比可以具有大致相同的噪声降低。与无电介质和包围的金属层的裸引线相比，从性能上，所测量到的噪声降低已被示出为大于5dB直至高达30dB。在特定实施例中，抗EMI性在引线长度的范围内有效，其中两个引线能够具有相同的截面结构和阻抗，但一个引线高达另一引线的长度的十(10)倍大同时仍具有相同的EMI特性。
示例2、3、4-串扰性能
示例2-图12示出两个接地层1200、1202都从封装体衬底1204延伸至裸片1206以允许在这两个引线端部进行连接的示例实施例。
示例3-图13示出两个接地层分别形成RF接地屏蔽件1300和DC功率接地屏蔽件1302的示例实施例。
示例4-在另一实施例中，可以通过上述工艺的变体来实现多个阻抗互连件。针对所有的封装体和器件压焊点的互连，可以适当地利用0.7mil(密尔)的配线对支撑裸片的衬底进行引线接合。利用聚对二甲苯C电介质对如此得到的封装体组件进行1.31微米的涂布。进行用以打开向封装体上的功率所用的接地连接和向器件上的相应功率接地连接的通孔的处理。进行仅在与功率互连件及其关联的接地端相关联的区域中创建金属的第一选择性金属化工艺。通过物理掩蔽、光刻或其它选择性工艺来实现该选择性金属化。因而，形成了完整的5欧姆的同轴互连件。在该接合点处，沉积电介质的第二涂层以实现26.34微米的总电介质厚度。对信号线所需的所有接地端进行第二通孔工艺。在期望的情况下，该步骤还可以包括向电源接地端的连接。进行第二金属化以针对50欧姆的线路创建接地屏蔽件。因而，实现了5欧姆和50欧姆的互连件的组合，其中功率线和信号线所用的单独解耦接地层也是可以的。
尽管已经与特定优选实施例相结合地具体说明了本发明，但显而易见，本领域技术人员鉴于上述说明将明白许多替换、修改和变化。因此，考虑所附权利要求书将包含如落在本发明的真实范围和精神内的许多这些替换、修改和变化。
特别地，本发明涉及一种EMI性能优良的堆叠型裸片封装体，包括：第一裸片和第二裸片，其中各裸片分别具有多个连接压焊点；裸片衬底，其支撑多个连接元件；第一引线，其从第一裸片延伸至裸片衬底上的多个连接元件其中之一，其中该第一引线包括具有第一芯直径的第一金属芯、包围第一金属芯的具有第一电介质厚度的电介质层和贴装接地的外金属层；以及第二引线，其从第二裸片延伸至裸片衬底上的多个连接元件其中之一，其中该第二引线包括具有第二芯直径的第二金属芯、包围第二金属芯的具有第二电介质厚度的电介质层和贴装接地的外金属层，从而降低对第一引线和第二引线之间的EMI和串扰的敏感性。
根据上述的裸片封装体，其中，第一引线与第二引线交叉。
根据上述的裸片封装体，其中，第一引线在第二引线的上方。
裸片衬底可以具有填充通孔以使得能够形成BGA封装体。
裸片衬底可以具有引线框架以形成引线框架封装体。
本发明包括裸片到裸片连接以及裸片到封装体连接。
此外，本发明涉及一种EMI性能优良的BGA封装体，包括：裸片，其具有多个连接压焊点；裸片衬底，其支撑多个连接元件；多个引线，其各自具有金属芯、包围金属芯的电介质层和接地的外金属层，其中与不具有包围金属芯的电介质层并且不具有外金属层的引线相比，串扰噪声降低了大于5dB。
本发明包括串扰降低的差分对、以及串扰降低的位于层外的交叉长型环状引线。
此外，本发明包括一种裸片封装体，包括：裸片，其具有多个连接压焊点；裸片衬底，其支撑多个连接元件；第一引线，其从第一裸片延伸至裸片衬底上的多个连接元件其中之一，其中该第一引线包括具有第一芯直径的第一金属芯、包围第一金属芯的具有第一电介质厚度的电介质层和外金属层；第一接地层，其贴装至第一引线的外金属层；第二引线，其从第二裸片延伸至裸片衬底上的多个连接元件其中之一，其中该第二引线包括具有第二芯直径的第二金属芯和包围第二金属芯的具有第二电介质厚度的电介质层；以及第二接地层，其贴装至第二引线的外金属层。
在上述裸片封装体中，第二接地层可以与第一接地层重叠，其中居间的电介质层维持第一接地层和第二接地层之间的电气隔离。
裸片封装体可以是采用BGA封装体和/或引线框架封装体的形式构建成的。

Claims (18)

1.一种裸片封装体(150；100；160；180；182；410；440；1100)，包括：
裸片(152；120；162a～162d；170；416)，其具有多个连接压焊点；
裸片衬底(154；102；418)，其支撑多个连接元件；
第一引线(156；110；164a；166a；176；412)，其包括具有第一金属芯直径的第一金属芯、包围所述第一金属芯的具有第一电介质厚度的第一电介质层和包围所述第一电介质层的第一外金属层，其中所述第一外金属层贴装至接地端或第一接地层；以及
第二引线(156；112；164b；166b；176；414)，其包括具有第二金属芯直径的第二金属芯、包围所述第二金属芯的具有第二电介质厚度的第二电介质层和包围所述第二电介质层的第二外金属层，其中所述第二外金属层贴装至接地端或第二接地层，
使得对所述第一引线和所述第二引线之间的电磁干扰即EMI和串扰的敏感性降低。
2.根据权利要求1所述的裸片封装体，其特征在于，所述裸片封装体包括第一裸片和第二裸片，所述第一裸片和所述第二裸片各自具有多个连接压焊点，
其中，所述第一引线从所述第一裸片延伸至所述裸片衬底上的所述多个连接元件其中之一或所述第二裸片的多个连接压焊点其中之一，并且所述第二引线从所述第二裸片延伸至所述裸片衬底上的所述多个连接元件其中之一或所述第一裸片的多个连接压焊点其中之一。
3.根据权利要求2所述的裸片封装体，其特征在于，所述裸片封装体是堆叠型裸片封装体。
4.根据权利要求1至3中任一项所述的裸片封装体(1100)，其中，所述第一引线(1110,1112)从第一裸片延伸至所述裸片衬底(1102)上的所述多个连接元件其中之一，并且所述第二引线(1114)从第二裸片延伸至所述裸片衬底(1102)上的所述多个连接元件其中之一，其中所述第一接地层(1130,1136)贴装至所述第一外金属层，并且所述第二接地层(1132,1134)贴装至所述第二外金属层。
5.根据权利要求4所述的裸片封装体(1100)，其中，所述第二接地层(1134)与所述第一接地层(1136)重叠、优选所述第二接地层(1134)和所述第一接地层(1136)之间具有维持所述第一接地层和所述第二接地层之间的电气隔离的居间层(1138)。
6.根据权利要求1至5中任一项所述的裸片封装体，其中，所述第一金属芯直径不同于所述第二金属芯直径。
7.根据权利要求1或5所述的裸片封装体，其中，所述第一金属芯直径与所述第二金属芯直径相同。
8.根据权利要求1至7中任一项所述的裸片封装体，其中，所述第一电介质层的厚度不同于所述第二电介质层的厚度。
9.根据权利要求1至7中任一项所述的裸片封装体，其中，所述第一电介质层的厚度与所述第二电介质层的厚度相同。
10.根据权利要求1至9中任一项所述的裸片封装体，其中，所述裸片衬底包括填充通孔以使得能够形成球栅阵列封装体即BGA封装体。
11.根据权利要求1至9中任一项所述的裸片封装体，其中，所述裸片衬底具有引线框架以形成引线框架封装体。
12.根据权利要求1至11中任一项所述的裸片封装体，其中，所述第一引线与所述第二引线交叉、以及/或者在所述第二引线的上方。
13.根据权利要求1至12中任一项所述的裸片封装体，其中，所述第一引线具有第一长度和第一阻抗，并且所述第二引线具有第二长度和第二阻抗，
其中，所述第一长度不同于所述第二长度、以及/或者所述第一阻抗不同于所述第二阻抗。
14.根据权利要求1至13中任一项所述的裸片封装体，其中，所述第一金属芯和/或所述第二金属芯顺次被涂布电介质层和导电金属层。
15.根据权利要求1至14中任一项所述的裸片封装体，其中，所述第一引线和所述第二引线提供裸片到裸片连接和/或裸片到衬底连接所用的电气通路。
16.根据权利要求1至15中任一项所述的裸片封装体，其中，所述多个引线提供至少一个差分对。
17.根据权利要求1至16中任一项所述的裸片封装体，其中，所述多个引线包括串扰降低的位于层外的交叉长型环状引线。
18.一种电磁干扰性能即EMI性能优良的球栅阵列封装体即BGA封装体，包括根据权利要求1至17中任一项所述的裸片封装体，所述裸片封装体包括多个引线，所述多个引线各自具有金属芯、包围所述金属芯的电介质层和接地的外金属层，其中与不具有包围所述金属芯的电介质层且不具有外金属层的引线相比，串扰噪声降低了至少5dB。
CN201480038222.0A 2013-07-03 2014-07-02 电磁干扰互连低的裸片封装体 Active CN105474388B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361842944P 2013-07-03 2013-07-03
US201361842943P 2013-07-03 2013-07-03
US61/842,943 2013-07-03
US61/842,944 2013-07-03
PCT/EP2014/001825 WO2015000596A1 (en) 2013-07-03 2014-07-02 Die package with low electromagnetic interference interconnection

Publications (2)

Publication Number Publication Date
CN105474388A true CN105474388A (zh) 2016-04-06
CN105474388B CN105474388B (zh) 2018-06-19

Family

ID=51134004

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480038222.0A Active CN105474388B (zh) 2013-07-03 2014-07-02 电磁干扰互连低的裸片封装体

Country Status (9)

Country Link
US (1) US9824997B2 (zh)
EP (1) EP3017471B1 (zh)
JP (1) JP6285021B2 (zh)
KR (1) KR101812594B1 (zh)
CN (1) CN105474388B (zh)
CA (1) CA2915900C (zh)
HK (1) HK1217569A1 (zh)
TW (1) TWM509429U (zh)
WO (1) WO2015000596A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652886A (zh) * 2020-12-15 2021-04-13 江苏惠通集团有限责任公司 一种引线结构以及引线结构的形成方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101815754B1 (ko) * 2016-03-10 2018-01-08 앰코 테크놀로지 코리아 주식회사 반도체 디바이스
JP2018201138A (ja) * 2017-05-29 2018-12-20 セイコーエプソン株式会社 電子部品、および電子機器
WO2019026975A1 (en) * 2017-08-02 2019-02-07 Sumitomo Electric Device Innovations, Inc. METHOD FOR ASSEMBLING SEMICONDUCTOR DEVICE
JP2019169504A (ja) * 2018-03-22 2019-10-03 日本電信電話株式会社 ワイヤボンディング構造
WO2019241737A1 (en) * 2018-06-14 2019-12-19 Caprice Gray Haley Coaxial wire
US11676922B2 (en) 2019-10-28 2023-06-13 Qualcomm Incorporated Integrated device comprising interconnect structures having an inner interconnect, a dielectric layer and a conductive layer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030159262A1 (en) * 2002-02-22 2003-08-28 Eliezer Pasternak High frequency device packages and methods
US20090159320A1 (en) * 2007-12-19 2009-06-25 Bridgewave Communications, Inc. Low Cost High Frequency Device Package and Methods
TW201316477A (zh) * 2011-10-06 2013-04-16 Adl Engineering Inc 具電磁干擾屏蔽之封裝模組

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0412538A (ja) * 1990-05-01 1992-01-17 Hitachi Ltd 半導体装置
FR2674680B1 (fr) * 1991-03-26 1993-12-03 Thomson Csf Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions.
TW214631B (zh) * 1992-02-25 1993-10-11 American Telephone & Telegraph
JPH06120286A (ja) * 1992-10-02 1994-04-28 Matsushita Electron Corp 半導体装置
JPH0766236A (ja) * 1993-08-31 1995-03-10 Tanaka Denshi Kogyo Kk 半導体素子用多層被覆ボンディングワイヤ及び半導体装置
US5625235A (en) 1995-06-15 1997-04-29 National Semiconductor Corporation Multichip integrated circuit module with crossed bonding wires
US5921818A (en) * 1997-06-23 1999-07-13 Lucent Technologies Inc. Low crosstalk electrical connector
US20020079572A1 (en) * 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6894398B2 (en) 2001-03-30 2005-05-17 Intel Corporation Insulated bond wire assembly for integrated circuits
DE102005002707B4 (de) 2005-01-19 2007-07-26 Infineon Technologies Ag Verfahren zur Herstellung elektrischer Verbindungen in einem Halbleiterbauteil mittels koaxialer Mikroverbindungselemente
JP4316607B2 (ja) 2006-12-27 2009-08-19 株式会社東芝 アンテナ装置及び無線通信装置
JP2008227126A (ja) * 2007-03-13 2008-09-25 National Institute Of Advanced Industrial & Technology 微細同軸ワイヤー、その製造方法、及び半導体装置
JP2009111010A (ja) 2007-10-26 2009-05-21 Renesas Technology Corp 半導体装置およびその製造方法
US8377749B1 (en) * 2009-09-15 2013-02-19 Applied Micro Circuits Corporation Integrated circuit transmission line
JP5752026B2 (ja) * 2011-12-16 2015-07-22 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030159262A1 (en) * 2002-02-22 2003-08-28 Eliezer Pasternak High frequency device packages and methods
US20090159320A1 (en) * 2007-12-19 2009-06-25 Bridgewave Communications, Inc. Low Cost High Frequency Device Package and Methods
TW201316477A (zh) * 2011-10-06 2013-04-16 Adl Engineering Inc 具電磁干擾屏蔽之封裝模組

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112652886A (zh) * 2020-12-15 2021-04-13 江苏惠通集团有限责任公司 一种引线结构以及引线结构的形成方法

Also Published As

Publication number Publication date
WO2015000596A1 (en) 2015-01-08
HK1217569A1 (zh) 2017-01-13
US20160379954A1 (en) 2016-12-29
CN105474388B (zh) 2018-06-19
CA2915900A1 (en) 2015-01-08
JP2016524338A (ja) 2016-08-12
US9824997B2 (en) 2017-11-21
JP6285021B2 (ja) 2018-02-28
CA2915900C (en) 2020-01-21
KR20160029760A (ko) 2016-03-15
EP3017471B1 (en) 2020-03-11
EP3017471A1 (en) 2016-05-11
TWM509429U (zh) 2015-09-21
KR101812594B1 (ko) 2018-01-30

Similar Documents

Publication Publication Date Title
CN105474388A (zh) 电磁干扰互连低的裸片封装体
CN105359268B (zh) 高带宽互连所用的隔热结构
US10770451B2 (en) Thin-film ESD protection device
CN105359267B (zh) 包括具有至少部分被电介质层包围的多个金属芯的互连件的互连系统
CN105518856A (zh) 具有选择性地修改的电气性质的引线的电子器件
CN105359263A (zh) 包括具有电介质涂层和金属涂层的配线的无衬底裸片封装体及其制造方法
CN105378915B (zh) 混合阻抗的焊线连接及其连接方法
CN105408998A (zh) 裸片封装体所用的涂布焊线和所述涂布焊线的制造方法
CN111081696A (zh) 半导体封装和制造半导体封装的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1217569

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant