TWM509429U - 具低電磁干擾互連結構的晶粒封裝 - Google Patents

具低電磁干擾互連結構的晶粒封裝 Download PDF

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Publication number
TWM509429U
TWM509429U TW103211709U TW103211709U TWM509429U TW M509429 U TWM509429 U TW M509429U TW 103211709 U TW103211709 U TW 103211709U TW 103211709 U TW103211709 U TW 103211709U TW M509429 U TWM509429 U TW M509429U
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Taiwan
Prior art keywords
layer
die
leads
package
dielectric
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Application number
TW103211709U
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English (en)
Inventor
Sean S Cahill
Eric A Sanjuan
Original Assignee
Rosenberger Hochfrequenztech
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Application filed by Rosenberger Hochfrequenztech filed Critical Rosenberger Hochfrequenztech
Publication of TWM509429U publication Critical patent/TWM509429U/zh

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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
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Description

具低電磁干擾互連結構的晶粒封裝
本創作涉及一種連接至晶粒的新型引線結構，藉以降低電磁干擾。透過本發明所實施的方法，降低了引線之間的串音效應以及封裝內部及外部電磁放射所產生的雜訊敏感度。
進一步地，本創作涉及新型多個接地平面的構成，以連接塗覆介電質的引腳引線，同時連結至一個或多個晶粒。
電磁干擾導致封装晶粒性能降低已是日趨嚴重的問題，特別是晶粒在千兆赫頻率下輸入/輸出(IO)的操作，影響尤甚。許多積體電路產生一種不希望的EMI干擾源。通常情況下，積體電路所產生的雜訊源於晶粒及其經由封裝連結的引線。當EMI被耦合至鄰近元件和積體電路時，它可能會干擾個別組件的性能，進而影響整體系統的效能。由於EMI的負面效應，以及受制於嚴格限定EMI輻射可接受水準的規範，積體電路最好能夠遏制或抑制電磁干擾(EMI)的產生。
藉由分隔引線或採用遮蔽物隔離的解決方案，並非總是有效或足以防護。此外，IC封裝級的EMI解決方案常被忽視，因為該級別主要考量的是信號完整性和功能性。然這將有益於封裝級的EMI解決方案，因為有助於減少「後端工程」或附加解決方案的需求。
謹記問題所在以及現有技術的不足之處，因此本創作目的旨在提供一種小型化的晶粒封裝，尤其是一種堆疊式晶粒封裝和/或具有兩個 或多個引線的BGA封裝，以提供優異的信號完整性和功能性。
本創作實現上述和其它相關的目的，對那些熟練的技術人員而言是顯而易見的，本創作針對EMI衰減的晶粒封裝，包含一顆具有多個連接墊片的晶粒；一支承多個連接元件的晶粒基板；第一層引線，具有第一層金屬芯及其第一層金屬芯直徑、第一介電質層環繞於前述具有第一層介電質厚度的第一層金屬芯，和第一外部金屬層環繞於前述第一介電質層，且該第一外部金屬層連接到接地；以及第二層引線，具有第二層金屬芯及其第二層金屬芯直徑、第二介電質層環繞於前述具有第二介電質厚度的第二層金屬芯，和第二外部金屬層環繞於前述第二介電質層，且該第二外部金屬層連接到接地；因此，前述第一層和第二層引線得以降低EMI的敏感度及第一層與第二層引線之間的串音效應。
進一步地，本創作係針對一種晶粒封裝，包含一顆具有多個連接墊片的晶粒；一支承多個連接元件的晶粒基板；第一層引線，具有第一層金屬芯及其第一層金屬芯直徑、第一介電質層環繞於前述具有第一層介電質厚度的第一層金屬芯，和第一外部金屬層環繞於前述第一介電質層以及連接第一外部金屬層的第一層接地平面；以及第二層引線，具有第二層金屬芯及其第二層金屬芯直徑、第二介電質層環繞於前述具有第二層介電質厚度的第二層金屬芯，和第二外部金屬層環繞於前述第二介電質層以及連接第二外部金屬層的第二層接地平面；因此，前述第一層和第二層引線得以降低EMI的敏感度及第一層和第二層引線之間的串音效應。該第一層引線可以從第一晶粒延伸至晶粒基板上多個連接元件之一，和/或第二層引線可以從第二晶粒延伸至晶粒基板上多個連接元件之一。第二層接地平面可能會或不會覆蓋第一層接地平面。在覆蓋的情況下，可在第一層和第二層接地平面之間安置一插入層以保持電氣絕緣。
根據本創作的晶粒封裝可藉由第一層和第二層晶粒形成堆疊式晶粒封裝，每顆前述的晶粒皆具有多個連接墊片；第一層引線從前述第一晶粒的多個連接墊片之一延伸至前述晶粒基板上多個連接元件之一或 前述第二晶粒的多個連接墊片之一，和第二層引線從前述第二晶粒的多個連接墊片之一延伸至前述晶粒基板上多個連接元件之一或前述第一晶粒的多個連接墊片之一。
根據本創作，附屬項係針對晶粒封裝有利的實施例，且其中揭露的各自特徵可以單獨或組合地併入。
100‧‧‧半導體晶粒封裝系統
102‧‧‧基板
104‧‧‧導電墊片
110‧‧‧引線
112‧‧‧引線
114‧‧‧引線
116‧‧‧引線
120‧‧‧晶粒
122‧‧‧連接墊片
150‧‧‧封裝
152‧‧‧晶粒
154‧‧‧基板
156‧‧‧引線
158‧‧‧連接墊片
160‧‧‧堆疊式晶粒封裝
162a‧‧‧晶粒
162b‧‧‧晶粒
162c‧‧‧晶粒
162d‧‧‧晶粒
164a‧‧‧引線
164b‧‧‧引線
164c‧‧‧引線
164d‧‧‧引線
166a‧‧‧引線
166b‧‧‧引線
166c‧‧‧引線
166d‧‧‧引線
170‧‧‧第一晶粒
172‧‧‧第二晶粒
174‧‧‧引線連接
173‧‧‧晶粒基板
176‧‧‧第一層引線
178‧‧‧直接連接
177‧‧‧第二層引線
180‧‧‧封裝系統
182‧‧‧封裝系統
200‧‧‧方塊圖
202‧‧‧第一步驟(清洗)
204‧‧‧連接墊片
206‧‧‧第二直徑電線
208‧‧‧遮蔽(選擇性沈積步驟)
210‧‧‧介電質沈積步驟
212‧‧‧接地連接
214‧‧‧金屬化
216‧‧‧以金屬層覆蓋介電質，同時連接引線至接地
218‧‧‧最後步驟(包覆成型)
300‧‧‧介電質塗層
302‧‧‧金屬導體(步驟A)
304‧‧‧第二次塗層(步驟C)
306‧‧‧金屬化(步驟D)
410‧‧‧球柵陣列封裝
412‧‧‧長引線
414‧‧‧短引線
416‧‧‧晶粒
418‧‧‧基板
420‧‧‧填充過孔
422‧‧‧焊球
440‧‧‧晶粒封裝
500‧‧‧串音效應曲線圖
502‧‧‧無遮蔽打線接合
504‧‧‧30歐姆同軸電纜
506‧‧‧50歐姆同軸電纜
510‧‧‧曲線圖
512‧‧‧裸膠
514‧‧‧裸膠
516‧‧‧50歐姆同軸引線
518‧‧‧50歐姆同軸引線
520‧‧‧雜訊電壓降低12倍
522‧‧‧允許更高的頻寬(穩定時間縮減7倍)
600‧‧‧振幅圖
602‧‧‧單端打線接合
610‧‧‧振幅圖
612‧‧‧單端微型同軸線
620‧‧‧空間幅度圖
622‧‧‧差分打線接合
630‧‧‧空間振幅圖
632‧‧‧差分微型同軸線
1100‧‧‧半導體晶粒封裝系統
1101‧‧‧等效設計的封裝
1102‧‧‧晶粒基板
1104‧‧‧導電墊片
1110‧‧‧引線
1112‧‧‧引線
1114‧‧‧引線
1120‧‧‧晶粒
1122‧‧‧連接墊片
1130‧‧‧第一層接地地面
1132‧‧‧第二層接地地面
1134‧‧‧接地平面
1136‧‧‧接地平面
1138‧‧‧介電質塗佈
1200‧‧‧接地平面
1202‧‧‧接地平面
1204‧‧‧封裝基板
1206‧‧‧晶粒
1300‧‧‧RF接地遮蔽
1302‧‧‧DC電源的接地遮蔽
本創作之特徵被認為具新穎性，且本新型元件特徵與特殊性一起公布於所附權利要求中。數字僅用於圖解說明的目的，並未按照比例繪製。然而，創作自身結構，藉由參照結合下列附圖的詳細說明，以獲致最佳的理解，其中：圖1為細間距的示意圖，說明低串音晶粒封裝具有塗覆介電質引線及其外部接地與金屬噴敷相連；圖2說明重疊塗覆介電質引線及其外部接地連結金屬噴敷的低串音示意圖；圖3說明堆疊式晶粒封裝中使用低串音引線的示意圖；圖4說明晶粒對晶粒或封裝對封裝實施例中使用低串音引線的示意圖；圖5為一方塊流程圖，說明塗覆介電質引線及其外部接地連結金屬噴敷的製造方法和步驟；圖6為一減成製程法，說明塗覆介電質引線及其外部接地連結金屬噴敷的製造方法；圖7說明具有塗覆介電質引線及其外部接地連結金屬噴敷的BGA封裝示意圖；圖8說明塗覆介電質引線及其外部接地連結金屬噴敷的部分引線框架封裝示意圖；圖9A和9B說明依據串音級別量測頻率顯示S參數的示意圖； 圖10A-D說明與電磁場相關之單端和差分引線，分別具有介電質塗佈和外部接地連結金屬噴敷層；圖11a和11b是根據本創作的晶粒封裝示意圖，說明具有介電質和金屬塗層的引線可能重疊或不重疊地連接至分隔的接地平面；圖12是根據本創作的晶粒封裝示意圖，說明具有兩個接地平面；和圖13是進一步地實施例示意圖，說明兩個接地平面分別形成RF接地遮蔽結構和DC電源遮蔽結構。
在描述本創作的最佳實施例中，本文將參照附圖1-13，其中提及的相似標號表示本創作的相似特徵。
具有電磁遮蔽的引線，以及在金屬芯和接地連結導電外層之間一個或多個中間介電質層，皆可改善封裝的電性能。如圖1所述的封裝150，其中晶粒152以不同長度的引線156連接至基板154。顯而易見地，基於流程的考量，基板154上的連接墊片158通常比晶片端有較大的間距。晶粒墊片的間距通常是由打線接合組件所完成的間距來定義。在基板端上的間距可由平版印刷重複性定義之，便於印刷電路板(PCB)製程類型與焊接、引線，或互連元件來定位精度。實際上，晶片端的導線間距較封裝更為緊密。意即隨著晶粒尺寸的降低，更不希望在電線上發生電磁場耦合(串音效應)的現象，尤其是晶粒附近。除了降低封裝內的電磁干擾(EMI)外，本文所述的引線構造具有降低外部(封裝)EMI的敏感度，並可大幅減少電磁放射。
如圖2所示，形成一個具有引線110、112和114的半導體晶粒封裝系統100，由於引線的構造，使其具有低電磁放射和串音效應。晶粒120安裝於基板102，包括多個連接墊片122，依據晶粒120需求提供信號、電源或其他功能。基板102可能包括導電墊片104，可直接提供封裝外的導電通路，或穿過導電引線框架、填充過孔、導電線跡、與第二層互連或類似通 路等。如圖所示，引線110、112和114可能以實質上不同的長度連結至導電墊片104。如圖2所示，引線的間距狹窄，且能夠交叉或彼此互壓(例如，引線110和112呈交叉狀)，為不希望存在的電磁耦合提供許多機會。
在圖示的實施例中，引線110、112和114具有一個內芯和外金屬層。例如，引線110、112和114具有沿其長度限定直徑的金屬芯，該金屬芯依序塗覆介電質層和導電金屬層。相較於未附加介電質和金屬塗佈的同尺寸裸引線，引線110、112和114的發射輻射較少，對外部(封裝)EMI的敏感度較低，且不易產生串音效應。在某些實施例中，如揭露所示，引線構造具有優越的電氣特性，相較於裸導線，基本上不同長度但相同芯徑的引線，具有大體上相同的雜訊抑制功能。雜訊抑制的量測值介於5dB至30dB之間，相較之下，其性能超越無介電質層與環繞金屬層的裸引線。在某些實施例中，引線長度在一定範圍內的抗電磁干擾是有效的，採用兩隻具有相同橫斷面結構和阻抗的引線，但其中一隻引線必須十(10)倍於另一隻引線的長度，與此同時，仍具有相同EMI特性。
電磁場耦合會導致不必要的串音效應，這不只發生在並列的引線，亦發生於堆疊式配置中彼此相鄰的引線。圖3顯示一個實現堆疊式晶粒配置的案例，說明了堆疊式晶粒封裝160具有晶粒162a-d與範例引線164a-d和166a-d，然此並列、上層和下層的引線，如果採用裸線而不是採用如本文所述塗覆一介電質層和導電性金屬層的引線，將造成不可接受的串音效應。同樣地，圖4顯示了晶粒堆疊之第一晶粒170和第二晶粒172，具有晶粒至晶粒的引線連接174，和晶粒至基板的連接176。它們也可能個別安裝在封裝系統180、182中，讓晶粒至晶粒直接連接178，以降低串音效應。換句話說，圖4顯示了在封裝系統180中，包含一第一晶粒170與一第二晶粒172，一第一層引線176係從該第一晶粒170延伸至一晶粒基板173上多個連接元件之一，或至該第二晶粒172的多個連接墊片之一；一第二層引線177係從該第二晶粒172延伸至該晶粒基板173上多個連接元件之一，或至該第一晶粒170的多個連接墊片之一；其中，晶粒基板173上多個連接元件之一我們可從圖 2之元件代表符號104，看出該連接元件即為導電墊片104；第二晶粒172的多個連接墊片之一與該第一晶粒170的多個連接墊片之一，我們也可從圖2之元件代表符號122，看出該連接墊片即為連接墊片122。
將塗覆介電質的引線運用在半導體晶粒封裝中，可形成各種介電層厚度。芯徑和介電層厚度兩者皆可改變。在某些實施例中，沉積介電質的組合物也可以改變。例如，提供一種具有優異蒸氣隔絕、耐氧降解性或類似性能的高性能介電質，使其薄薄的沉積在低成本的厚介電質上。圖示實施例的另一層面顯示，引線110、112和114(參照圖2和圖3)的內芯和外部金屬層上具有各種介電質厚度，提供了全然不同的阻抗。例如，引線110可能具有沿其長度限定直徑的金屬芯，將該金屬芯依序塗覆一層薄薄的介電質層和導電金屬層。這樣的引線110適用於電源傳輸，因為隨之發生的低電阻和低電容特性可減少壓降。或者，引線112具有更厚的介電質層，適用於信號數據的傳輸，而引線114則具有中厚度的介電質層。在某些實施例中，如揭露所示，引線構造具有優越的電氣特性，基本上不同長度但相同芯徑的引線，在阻抗差異在目標阻抗10%範圍內，儘管有50%或以上的長度變化，仍具有實質上相同阻抗的可能性。例如，引線116的長度儘管是引線110的兩倍，仍約略具有相同阻抗。在某些實施例中，引線的差異可能更大，使用兩條具有相同橫斷面結構和阻抗的引線，但其中一隻引線長度是另一隻引線的十(10)倍。
一般而言，薄介電質層提供低阻抗，有利於電力線的應用；厚介電質層，一般有利於信號的完整性；而引線上的外部金屬層，則可能有利於連結到相同的接地。一種結合芯徑和介電層厚度的方式是可能的，可能進行這一系列的步驟，以完成具有不同阻抗的引線。在某些實施例中，可能期望電力線具有較大的線芯，以提升電源的處理能力、降低電力線的溫度，和/或進一步降低電源電感，以減少接地線加劇接地反彈或壓降的可能。
中等厚度的介電質層也是有用的，因為許多的封裝可受惠於 具有3種或以上不同介電層厚度的引線。具有中厚度介電質的引線可被用來連接不同阻抗的源與負載，以提供最大化功率傳輸。例如，10歐姆電源用20歐姆的引線加至40歐姆的負載。另外，由於介電質的成本可能很高，重大的信號通路或可使用厚的介電質互連，而較不重要的或復位引線、重置、或類似等引線，則可塗覆一層厚度大於電源引線的介電質層，但小於(中厚)臨界信號引線。如此一來，可降低介電質沉積材料的成本和時間。
介電質塗佈的精確厚度是決定的，可結合打線接合直徑，提供每根引線完成特定期望的阻抗值。
方程式(1)中，可求得同軸線的特性阻抗，其中L為每單位長度的電感，C是每單位長度的電容，a是打線接合直徑，b是介電質的外徑，εr 是同軸介電質的相對介電常數。
如圖5所示，在一製造實例中，可依循方塊圖200所示的步驟，使用或不使用一個或多個接地面來連接塗有介電質及金屬化外層的引線。引線。在第一步驟202中，先清洗晶粒和基板上的連接墊片。接著，使用打線接合器連接晶粒至連接墊片204。或者，連接至第二直徑電線206(例如，較大的直徑電線適用於電源連接)，或步驟208，遮蔽晶粒區域或以其他防護方式來進行選擇性沉積。在介電質沉積步驟210中，可沉積一個或多個相同或不相同組合物的介電質層(步驟210)，隨後選擇雷射或熱燒蝕，或化學的方式去除介電質的部分，以提供通道至覆蓋的接地連接(步驟212)。此步驟是非必要性的，因為在某些實施例中，可能無接地過孔的需求。尤以較高頻率下的晶粒操作，更是如此，因為一個虛擬的RF接地可以透過電容耦合來完成，由於厚度值(Er功能)的頻率依賴性，考量透過電容耦合來完成接地。隨後進行金屬化(步驟214)，以金屬層覆蓋介電質，形成於引線最外側的金屬化層，同時連接引線至接地。整個過程可重複多次(步驟216)，有助於那些實施例利用選擇性沉積技術，特別是支承多個晶 粒或複雜且多式樣阻抗引線的那些實施例。在最後步驟中(步驟218)，就非凹槽式封装而言，封裝引線可使用一種包覆成型的方式。該封裝引線可能用於高頻率裝置封裝，被描述於美國專利6，770，822號及美國專利公開號2012/0066894，其揭露的內容透過參考文獻完全併入本文。
在某些實施例中，變更和附加至所述的過程是可能的。例如，介電質共形塗佈可使用化學(電泳)、機械(表面張力)、催化底漆、電磁(UV、IR)、電子束等各種方法或者其他適合的技術來完成。電泳聚合物特別有利，因為它們可依賴自我限制反應，針對電泳塗佈解決方案調整製程參數和/或簡單的添加劑、濃度、化學、熱或改變時間，迅速地沉積精確的厚度。
在其它的實施例中，使用介電質預塗的打線接合的方式來形成引線。而市售可用的塗料電線，通常薄於介電質厚度，需要增厚，例如，50歐姆引線，使用上述論及的介電質沉積步驟來增加介電質的厚度，以設定所需的阻抗。使用這些預塗電線可以簡化其他所需的製程步驟，以構建同軸引線，並可顧及薄層需要以氣相沉積介電質，以及更快的處理時間來構建接地過孔。使用預塗打線接合可防止窄間距或交叉引線的短路。在某些實施例中，為考量所選的圖案技術，預塗打線接合亦有以感光材料製成介電質。
在其他實施例中，使用聚對二甲苯做為介電質材料。聚對二甲苯為一商業用名稱，在各種化學氣相的沉積中，使用聚對二甲苯聚合物有防濕和介電絕緣的作用。可在增長有限的縮合反應中使用改良的聚對二甲苯的沉積系統來形成聚對二甲苯，其中晶粒、基板和引線對齊感光板，讓EM輻射(IR，UV或其他)以精確的方式照射，使其發生選擇性的介電質增長率。有利地，此舉可最小化或消除構建接觸過孔，移除大量聚對二甲苯等所需的程序。
已知聚對二甲苯和其它介電質在氧、水蒸汽和熱的存在下，由於氧鍵斷裂而導致降解。可藉由良好的氧蒸氣隔絕層所形成的金屬層來 減少傷害，利用3-5微米的金屬層薄層厚度形成真正的密封界面。或者，如果因電、熱或加工要求，必須選擇性地剔除金屬，或無法沉積於某些區域，則可使用範圍廣泛的防氧蒸氣聚合物，聚乙烯醇(PVA)就是一種廣泛使用的聚合物。這些聚合物可以用圓頂封裝體、網印、鋼印、龍門式分配、噴塗至聚對二甲苯表面的方式，使其得以外露於氧氣或水蒸汽環境中。有利地，使用防蒸氣聚合物可以策略性的降低部分成本，否則，可能需求高成本聚對二甲苯厚層或其他對氧敏感性的材質。
正如將理解的是，所有陳述的方法步驟皆受惠于各種選擇性沉積技術。選擇性沉積可以藉由物理掩蔽法、定向聚合物沉積法、光阻劑法或任何其它合適的方法確保當時在金屬芯、介電質層或其它最外層的沉積具有差分的沉積厚度。在選擇性沉積考量以加成法來構建引線的同時，亦需考量減成法，去除介電質或金屬，形成不同的阻抗互連。例如，封裝藉由能夠打線接合的方式填充一顆或多顆晶粒，以提供所有的封裝和裝置墊片互連。至於圖6說明了晶粒封裝製造的步驟和構造，介電質塗層300可以在打線接合金屬導體302(步驟A)上沉積至預定厚度，其中介電質的預定厚度是的第二層互連阻抗的需求。第二層阻抗打線接合介電質可被去除，例如，透過蝕刻步驟(步驟B)，接著進行第二次塗層304沉積(步驟C)，隨後是兩種互連的金屬化306(步驟D)。這個減性法的過程將構建兩個不同阻抗的打線接合。
至於圖7的實施例說明了球柵陣列(BGA)封裝410，包括具有多個選定阻抗的介電質和金屬塗層引線。BGA是一種表面安裝的封裝，廣泛用於積體電路，通常比雙列式、引線框架或其他扁平封裝提供更多的互連引線，因為BGA整個底面皆可用來連接墊片。BGA封裝有多種類型，晶粒416連接至具有填充過孔420的基板418再連至連接墊片。可能使用引線接合連接晶粒416頂端至墊片/過孔420，從而提供基板418頂側至底部的電氣連接。在BGA封裝中，焊球422被附著至封裝底部，並以粘性助焊劑保持在適當位置，直到焊接至印刷電路板或其他基板上。如本文所述，可採用具 有介電質層和外部接地連結金屬層的改善引線來替換傳統BGA封裝的打線接合。該引線具有遍及內芯和外金屬層的各種介電層厚度，並可優化選擇特定的阻抗，其中部份介質層厚度可以有不同選擇或相匹配。如圖7所示，無論是長引線412和短引線414皆予以支持。
更詳細地，一種改善BGA封裝的組件，要求正面朝上連接晶粒至基板，毗連於支承連接墊片，並繞過基板中的過孔。這個打線接合的組件，適用於每個互連的要求，打線接合形成於基板連接墊片和晶粒連接墊片之間。連接低頻率和電源輸入至低頻信號引線，同時連接高頻率輸入和輸出至高頻信號引線。在某些實施例中，低頻率和電源輸入的引線厚度與高頻信號的引線厚度不同。此外，該組件取決於任何實質上共形介電質材料的塗佈。最適宜使用聚對二甲苯，因其成本低，易於真空沉積，且有卓越的性能特性。為了在接地點或接地遮蔽層形成電氣連接，靠近引線框架連接點的少部分介電質層可選擇以蝕刻、熱降解或雷射燒蝕的方式予以去除。同樣地，為了提供接地連接，靠近晶粒連接墊片的少部分介電質層亦需予以去除。在結構中接地，從適用的金屬化層覆蓋介電層頂端，形成一個接地遮蔽。最適宜的金屬層厚度必須慎選，考量透入深度和直流電阻的問題，以及優良電導體的主要組成，例如銀、銅或金等。就多數的應用而言，1微米的塗佈厚度即有足夠功能，但是更厚的塗層有助於引線之間串音效應的最小化。這些塗層可以透過平版印刷或其他遮蔽方法的組合、電鍍或其它選擇性沉積方法增添於指定區域內。該封裝可按照包覆成型或覆蓋晶粒的方式完成布置，隨後進行切晶(切單/去框)和測試。
或者，圖8實施例說明了以低成本引線框架為基礎的晶粒封裝440，包括從晶粒延伸至引線框架的打線接合，依據內含個別封裝位置的二維陣列和外框架部分所形成的引線框架條來製造。引線框架是常見的構造，可透過蝕刻、沖壓，或電沉積形成個別的引線。引線框架條可置於模具中，包括但不限於，一種射出成型或轉移成型的裝置。塑料是最適用的介電質材料，例如市售的環氧模壓樹脂，藉由射出、泵送或其他方式轉移 至模具中，以完成引線框架/模材料的複合結構。模材料特性對其介電常數、損耗正切和電色散特性及其溫度、濕度和其他機械性能的屬性等非常重要。
清洗複合引線框架條上每個封裝位置的脫模劑和/或溢料，並為引線框架外露的金屬部分製備金屬表面鍍層。這可透過電鍍技術如浸漬或電鍍來完成，並選用耐腐蝕和易於打線接合的金屬。類似這種加工的案例是先鍍一層薄薄的鍍鎳層(保護用)，接著再鍍一層鍍金層(增加打線接合的保護能力)。然後，在成型引線框架條上的每個封裝位置填充所需的晶粒，並將其連接至基座與所選的固晶材料上，提供特定封裝用的機械性能和熱性能。然後打線接合此組合組件，以適用於每個互連的需求，該打線接合形成於引線框架的引線和晶粒的連接墊片之間。連接低頻率和電源輸入至低頻信號引線，同時連接高頻率輸入和輸出至高頻信號引線。在某些實施例中，低頻率和電源輸入的引線厚度與高頻信號的引線厚度不同。
如上述的BGA封裝410，填充引線框架條接下來進行任何實質共形介電質材料的塗佈，包括聚對二甲苯。在聚對二甲苯的案例中，它可能最適宜與膠帶一起遮蔽封裝底部，如真空相容的聚醯亞胺與丙烯酸類黏著劑，或類似材料等，以避免沉積於引線區域上，導致最終附著於PCB上。在其後的步驟中，這將有助於更容易的焊接。為了在接地點或接地遮蔽層形成電氣連接，靠近引線框架連接點的少部分介電質層可選擇以蝕刻、熱降解或雷射燒蝕的方式予以去除。同樣地，為了提供接地連接，靠近晶粒連接墊片的少部分介電質層亦需予以去除。在結構中接地，從適用的金屬化層覆蓋介電層頂端，形成一個接地遮蔽。最適宜的金屬層厚度必須慎選，考量透入深度和直流電阻的問題，以及優良電導體的主要組成，例如銀、銅或金等。就多數的應用而言，1微米的塗佈厚度即有足夠功能，但是更厚的塗層有助於引線之間串音效應的最小化。這些塗層可以透過平版印刷或其他遮蔽方法的組合、電鍍或其它選擇性沉積方法增添於指定區域內。該封裝可按照包覆成型或覆蓋晶粒的方式完成布置，隨後進行切晶(切單/去框)和測試。
實施例1-串音性能
圖9A為一描述串音效應曲線圖500，對比了無遮蔽打線接合502、30歐姆同軸電纜504和50歐姆同軸電纜506三者的頻率函數，兩個同軸引線在串音/隔絕的非遮蔽互連上，顯示約有25分貝的改善效果。就此點而言，根據本發明製備的不匹配同軸引線甚至優於無遮蔽的裸引線。
圖9B為一曲線圖510，對比了裸膠512、514和50歐姆同軸引線516、518在時域的性能。與圖9A所示的頻率結果一致。雜訊電壓降低高達12倍(串音/隔絕)520，穩定時間回應提高7倍522(允許更高的頻寬)。
圖10A-D顯示電磁場振幅的空間振幅圖，分別與單一與差分引線及其有無電介質塗佈和外部接地金屬層有關。圖10A顯示了單端打線接合602的振幅圖600，如圖所示，電磁場振幅沿打線接合y軸上的點是顯著的。圖10B顯示了單端微型同軸線612的振幅圖610。顯然地，相較於裸引線，同軸引線可大幅地降低電磁輻射。
這對於差分對而言特別實用，通常使用裸引線技術來改善雜訊免除力。通常情況下，一對引線在相反極性下驅動信號將面臨大致相同的雜訊環境。當這兩個信號加在一起差分，通常可消除雜訊。然而，如果雜訊環境不等同，這可能發生在許多引線對的細間距位置，則相鄰的雜訊源可在最近鄰的差分對上誘導一個比更遠鄰一個更大的信號。遮蔽式微型同軸對因而具備更大的雜訊免疫力，因為雜訊在到達信號線之前，已高度衰減。圖10C顯示了差分打線接合622的空間幅度圖620。圖10D顯示了差分微型同軸線632的空間振幅圖630。該圖顯示幾乎完全遮蔽，亦即電磁輻射排放可忽略不計。
如圖11a和11b所示，成型的半導體晶粒封裝系統1100具有多個分開或重疊的接地平面。由於引線構造連接至接地平面，故可製造出具有低電磁排放和串音效應的引線1110、1112和1114。將晶粒1120連同多個連接墊片1122安裝在晶粒基板1102上，由晶粒1120提供信號、電源或其他所需的功能。晶粒基板包括導電墊片1104，可直接提供封裝外的導電通路，或穿 過導電引線框架、填充過孔、導電線跡、第二層互連或類似通路等。引線1110、1112和1114可能以實質上不同的長度連接至導電墊片1104，如圖所示。
在圖示的實施例中，引線1110和1112具有一內芯和一外金屬層連接至第一層接地地面1130。相對地，引線1114亦具有一內芯和一外金屬層，分別從第一層接地地面1130區隔連接至第二層接地平面1132。同樣地，圖11b除了接地平面1134和1136物理重疊外，顯示了與封裝11a等效設計的封裝1101，然而，接地平面電性相異，因為介電質塗佈1138(顯示移除部分)可被用來區隔接地1134和1136。正如將理解的是，引線1110、1112和1114可以具有沿其長度限定直徑的金屬芯，該金屬芯依序塗佈介電質層和導電金屬層。
相較於未塗佈介電質和金屬的同尺寸裸引線，引線110、112和114發射的輻射較少，對外部(封裝)EMI的敏感度較低，且不易產生串音效應。在某些實施例中，如揭露所示，引線構造具優越的電氣特性，相較於裸導線，基本上不同長度但相同芯徑的引線，具有大體上相同的雜訊抑制功能。雜訊抑制的量測值介於5dB至30dB之間，相較之下，其性能超越無介電質及環繞金屬層的裸引線。在某些實施例中，引線長度在一定範圍內的抗電磁干擾是有效的，採用兩隻具有相同橫斷面結構和阻抗的引線，但其中一隻引線必須十(10)倍於另一隻引線的長度，與此同時，仍具有相同EMI特性。
實施例2，3，4-串音性能
實施例2-圖12具體實施例顯示兩個接地平面1200，1202，兩者皆從封裝基板1204延伸至晶粒1206，以便於在兩個引線端提供連結。
實施例3-圖13具體實施例顯示兩個接地平面分別形成RF接地遮蔽1300和DC電源的接地遮蔽1302。
實施例4-在另一個實施例中，可透過上述各種製程來實現多個互連阻抗。基板支承晶粒的打線接合以0.7mil(密爾)電線最適合所有封裝和裝置墊片的互連。將組合的封裝組件進行聚氯代對二甲苯(Parylene C) 介電質1.31微米的塗佈。進行打開過孔至接地連接的過程，提供封裝上的電源和裝置上相應的電源接地連結。執行第一層選擇性金屬噴敷的過程，該金屬只噴敷與電源互連及其相關接地的相關區域。這種選擇性的金屬噴敷是透過物理遮蔽、平版印刷術或其它選擇性的製程來完成的。因此，形成完整的5歐姆同軸互連。值此之際，沉積第二塗層的介電質，讓總介電層厚度達到26.34微米。在所有需要接地處進行第二次過孔加工，以提供信號線。如果需要的話，此步驟還可連接到電源接地。執行第二層金屬噴敷，為50歐姆線產生接地遮蔽。因此，實現了5歐姆和50歐姆互連的組合，藉由分隔去耦接地平面的選項，提供電源線和信號線。
雖然已具體描述本創作連同一個特定的最佳實施例，顯然地，根據先前所述，對於本領域的技術人員而言，許多替換，修改和變化將是顯而易見的。因此可預期的是所附權利要求將包括落入本發明真實範圍和精神內的所有替換、修改和變化。
本創作特別針對：一種具有卓越EMI性能的堆疊式晶粒封裝，其中包含第一和第二晶粒，每顆晶粒分別具有多個連接墊片，晶粒基板支承多個連接元件，第一層引線從第一層晶粒延伸至晶粒基板上多個連接元件之一，第一層引線具有第一層金屬芯及其第一層金屬芯直徑，和一介電質層環繞具有第一層介電厚度的第一層金屬芯，以及一外部金屬層連結至接地，而第二層引線從第二層晶粒延伸至晶粒基板上多個連接元件之一，第二層引線具有第二層金屬芯及其第二層金屬芯直徑，和一介電質層環繞具有第二層介電厚度的第二層金屬芯，以及一外部金屬層連接至接地，以減少第一層和第二層引線之間的EMI敏感度和串音效應。
上述的晶粒封裝，其中第一層引線跨越第二層引線。
上述的晶粒封裝，其中第一層引線在第二層引線的上方。
晶粒基板具有填充過孔，便於形成BGA封裝。
晶粒基板具有引線框架，便於形成引線框架封裝。
本創作包括晶粒對晶粒的連接以及晶粒對基板的連接。
更進一步地，本創作係針對具有卓越EMI性能的BGA封裝，包含一顆晶粒具有多個連接墊片、一晶粒基板支承多個連接元件，多隻引線，每隻都具有一金屬芯、一介電質層環繞該金屬芯，和連接至接地的一外部金屬層，相較於無介電質層環繞金屬芯和外部金屬層的引線，其串音雜訊降低5分貝以上。
進一步地，本創作包括一具有降低串音效應的差分對，以及在平面外交叉、長線圈的引線，以減少串音效應。
本創作進一步包括一晶粒封裝，包含一顆具有多個連接墊片的晶粒，一支承多個連接元件的晶粒基板，第一層引線從第一晶粒延伸至晶粒基板上多個連接元件之一，該第一層引線具有第一層金屬芯及其第一層金屬芯直徑，一介電質層環繞具有第一層介電厚度的第一層金屬芯，和一外部金屬層，以及第一層接地平面連接至第一層引線的外部金屬層，第二層引線從第二晶粒延伸至晶粒基板上多個連接元件之一，第二層引線具有第二層金屬芯及其第二層金屬芯直徑，且一介電質層環繞具有第二層介電厚度的第二層金屬芯，以及第二層接地平面連接至第二層引線的外部金屬層。
上述的晶粒封裝，第二層接地平面可能覆蓋第一層接地平面，可在第一層和第二層接地平面之間插入一介電層以保持電氣隔離。
晶粒封裝可能以BGA封裝和/或引線框架封裝的形式建構。
150‧‧‧封裝
152‧‧‧晶粒
154‧‧‧基板
156‧‧‧引線
158‧‧‧連接墊片

Claims (17)

  1. 一種晶粒封裝，包含：一第一晶粒與一第二晶粒，且該第一晶粒與該第二晶粒都各自具有多個連接墊片；一晶粒基板，支承多個連接元件；一第一層引線，該第一層引線具有一第一層金屬芯，該第一層金屬芯具有一第一層金屬芯直徑，一第一介電質層環繞該第一層金屬芯，該第一層金屬芯具有一第一層介電層厚度，一第一外部金屬層環繞於該第一介電質層，且該第一外部金屬層連接至接地或連接至一第一層接地平面，該第一層引線係從該第一晶粒延伸至該晶粒基板上多個連接元件之一，或至該第二晶粒的多個連接墊片之一；一第二層引線，該第二層引線具有一第二金屬芯，該第二金屬芯具有一第二層金屬芯直徑，一第二介電質層環繞該第二層金屬芯，該第二層金屬芯具有一第二層介電層厚度，一第二外部金屬層環繞於該第二介電質層，且該第二外部金屬層連接至接地或連接至一第二層接地平面，該第二層引線係從該第二晶粒延伸至該晶粒基板上多個連接元件之一，或至該第一晶粒的多個連接墊片之一；以降低EMI的敏感度和該第一層引線與該第二層引線之間的串音效應。
  2. 如申請專利範圍第1項所述的晶粒封裝，其特徵在於該晶粒封裝是一種堆疊式晶粒封裝。
  3. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層引線係從該第一晶粒延伸至該晶粒基板上多個連接元件之一，該第二層引線係從該第二晶粒延伸至該晶粒基板上的多個連接元件之一，該第一層接地平面係連接至該第一外部金屬層，該第二層接地平面係連接至該第二外部金屬層。
  4. 如申請專利範圍第3項所述的晶粒封裝，其中該第二層接地平面覆蓋該第一層接地平面，且在該第一層接地平面和該第二層接地平面之間有一插入 層以保持電氣隔離。
  5. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層金屬芯直徑與該第二層金屬芯直徑不同。
  6. 如申請專利範圍第1項或第2項中任一項所述的晶粒封裝，其中該第一層金屬芯直徑與該第二層金屬芯直徑相同。
  7. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層介電層厚度與該第二層介電層厚度不同。
  8. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層介電層厚度與該第二層介電層厚度相同。
  9. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該晶粒基板包括填充過孔，便於形成一BGA封裝。
  10. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該晶粒基板包括一引線框架，便於形成引線框架封裝。
  11. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層引線跨越該第二層引線，或該第一層引線在該第二層引線的上方。
  12. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層引線具有一第一層長度和一第一層阻抗，該第二層引線具有一第二層長度和一第二層阻抗，其中該第一層長度與該第二層長度不同或該第一層阻抗與該第二層阻抗不同。
  13. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層金屬芯或該第二層金屬芯係依序地塗佈一介電質層和一導電金屬層。
  14. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層引線與該第二層引線係為晶粒至晶粒的連結，或晶粒至基板的連結，提供電氣通信。
  15. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一層引線與該第二層引線包括至少一個差分對。
  16. 如申請專利範圍第1項至第2項中任一項所述的晶粒封裝，其中該第一 層引線與該第二層引線包括在平面外交叉、長線圈的引線，以減少串音效應。
  17. 一具有卓越EMI性能的BGA封裝，包括申請專利範圍第1項至第2項中任一項所述的晶粒封裝，該晶粒封裝包含多根引線，每根該引線都有一金屬芯，一介電質層環繞該金屬芯，一外部金屬層連接到接地。
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