CN105408998A - 裸片封装体所用的涂布焊线和所述涂布焊线的制造方法 - Google Patents

裸片封装体所用的涂布焊线和所述涂布焊线的制造方法 Download PDF

Info

Publication number
CN105408998A
CN105408998A CN201480038198.0A CN201480038198A CN105408998A CN 105408998 A CN105408998 A CN 105408998A CN 201480038198 A CN201480038198 A CN 201480038198A CN 105408998 A CN105408998 A CN 105408998A
Authority
CN
China
Prior art keywords
lead
wire
dielectric
metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201480038198.0A
Other languages
English (en)
Other versions
CN105408998B (zh
Inventor
S·S·卡希尔
E·A·圣胡安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rosenberger Hochfrequenztechnik GmbH and Co KG
Original Assignee
Rosenberger Hochfrequenztechnik GmbH and Co KG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rosenberger Hochfrequenztechnik GmbH and Co KG filed Critical Rosenberger Hochfrequenztechnik GmbH and Co KG
Publication of CN105408998A publication Critical patent/CN105408998A/zh
Application granted granted Critical
Publication of CN105408998B publication Critical patent/CN105408998B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/564Details not otherwise provided for, e.g. protection against moisture
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/43Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6611Wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/438Post-treatment of the connector
    • H01L2224/4382Applying permanent coating, e.g. in-situ coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4556Disposition, e.g. coating on a part of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4557Plural coating layers
    • H01L2224/45572Two-layer stack coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/4557Plural coating layers
    • H01L2224/45573Three-layer stack coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45639Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45647Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/4569Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/46Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48235Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4901Structure
    • H01L2224/4903Connectors having different sizes, e.g. different diameters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/4917Crossed wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Chemically Coating (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本发明涉及一种引线,其具有金属芯(202)、电介质层(200,204)和可接地的金属(206),其中,所述引线还具有一个或多个防潮涂层。此外,本发明涉及具有根据本发明的至少一个引线的裸片封装体。

Description

裸片封装体所用的涂布焊线和所述涂布焊线的制造方法
技术领域
说明用于利用电介质涂布金属芯以在金属化之后形成可接地的引线的改进方法。
背景技术
电子器件和组件正以不断增加的速度并且在越来越高的频率范围内进行工作。普及的半导体封装体类型使用可以连接至衬底或引线框架的焊线,而该衬底或引线框架可以连接至第二级互连件、通孔、衬底或封装体走线或者焊球等,从而连接至电子器件的印刷电路板(PCB)。
制造可能很昂贵,并且由于材料沉积错误所引起的故障可能会破坏裸片功能。需要降低制造成本并且提高可靠性的方法。
发明内容
考虑到现有技术的这些问题和不足,本发明的目的是提供可以在降低制造成本并且提高可靠性的情况下进行制造的引线和具有至少一个引线的裸片封装体。
在本发明中实现本领域技术人员将明白的上述和其它目的,其中本发明涉及一种引线,其具有金属芯、电介质层和可接地的金属(外金属层),其特征在于,所述引线附加具有至少一个防潮涂层。
此外,本发明涉及一种裸片封装体,包括:裸片,其具有多个连接压焊点;裸片衬底,其支撑多个连接元件;以及根据本发明的一个或多个引线,其连接在所述裸片和所述裸片衬底之间。
此外,本发明涉及用于制造根据本发明的裸片封装体的方法。
从属权利要求涉及本发明的有利实施例。
利用根据本发明的包括防潮层的涂敷的引线,可以保护由于选择性金属沉积或去除因而没有被金属覆盖的区域。因此,可以防止由于材料沉积错误破坏裸片功能因而导致裸片封装体故障。
附图说明
图1是用于形成针对各种要求而优化的具有防潮层的电介质和金属涂布引线的所选方法的例示;
图2示出用于制造具有外接地金属的电介质涂布引线的方法步骤;
图3示出用于制造具有外接地金属的电介质涂布引线的减成法;
图4示出包括具有外接地金属的电介质涂布引线的BGA封装体;以及
图5示出包括具有外接地金属的电介质涂布引线的引线框架封装体的一部分。
具体实施方式
如针对图1所示的方法看出,使用引线接合(10)来提供引线的金属芯与裸片和衬底连接压焊点这两者之间的互连。利用电介质涂布(11)金属芯。蚀刻去除(12)电介质层以使接地压焊点暴露,之后进行金属化(13)以使金属化层连接至接地压焊点。根据需要,还可以去除(14)附加金属层,之后沉积(15)附加的电介质或防潮层以提高抗氧降解性。在需要的情况下,可以涂敷附加涂布以促进粘附于塑封料,并且可以对裸片进行包覆成型(16)、固化和切单,以供使用。
在特定实施例中,可以通过使半导体裸片封装中所使用的电介质涂布引线形成为具有变化的电介质厚度来调整电气特性。通过改变电介质涂布次数和制造步骤可以实现厚的厚度、薄的厚度和中间厚度。可以改变芯直径和电介质厚度这两者。在特定实施例中,还可以改变所沉积的电介质的成分,其中例如,明显不同的电介质的材料包围金属芯,反过来电介质由可接地的金属涂层包围。这样例如允许高性能的电介质具有优良的防潮层或抗氧降解性等,以薄薄地沉积在厚的低成本的电介质材料的层上。在其它实施例中,厚度发生改变的多个层的电介质可以经由薄的金属层隔开,其中在最外侧金属层接地。
通常,薄的电介质层将提供低阻抗,从而适合功率线,厚的电介质有利于信号完整性,并且外金属层连接至相同的接地端。注意,芯直径和电介质厚度的组合是可以的,并且可以进行一系列的这些步骤以实现两个以上的阻抗。在特定实施例中,可以期望在功率线上具有大的芯以增加功率处理能力、降低功率线温度、以及/或者进一步降低电源以及将加剧接地反弹或功率跌落的接地线上的任何电感。由于许多封装体可以受益于具有三(3)个以上的不同电介质厚度的引线,因此中间厚度的电介质层也是有用的。例如,具有中间电介质厚度的引线可用于连接阻抗大大不同的源和负载以使功率传送最大化。例如,10欧姆的源可以连接至具有20欧姆的引线的40欧姆的负载。此外,由于电介质的成本可能高,因此可以使用厚的电介质来使重要的信号路径相互连接,其中可以利用厚度与功率引线相比更大但与重要的信号引线相比更小(中间)的电介质层来涂布状况或重置等不太重要的引线。有利地,这样可以减少电介质沉积材料的成本和时间。
可以与焊线直径相组合地选择电介质涂层的精确厚度,以针对各引线实现特别期望的阻抗值。
Z 0 = L C = 138 ϵ r · log ( b a ) - - - ( 1 )
在等式(1)中给出同轴线的特性阻抗,其中:L是每单位长度的电感,C是每单位长度的电容,a是焊线的直径,b是电介质的外径,并且εr是同轴电介质的相对介电常数。
如图2所示,在一个实施例中,具有外接地金属的电介质涂布引线的制造可以使用以下步骤来进行。清洗(50)裸片和衬底上的连接压焊点,并且使用引线接合机使裸片连接至连接压焊点(51)。可选地,可以贴装(52)第二直径的配线(例如,适合功率连接的较大直径的配线),或者可以对裸片的区域进行遮掩(53)或保护以允许进行选择性沉积。可以沉积(54)成分相同或不同的电介质的一个或多个层,之后对电介质的一部分进行选择性激光或热烧蚀或者化学去除,以使得能够到达在电介质沉积步骤中所覆盖的接地接点(55)。该步骤是可选的,这是因为,在一些实施例中,不需要接地通孔。由于可以通过电容耦合建立虚拟RF接地,因此这对于以较高频率进行工作的裸片而言尤其如此。之后进行金属化(57),从而利用形成引线的最外金属化层的金属层覆盖电介质,并且还使引线接地。可以重复多次整个处理(58),从而用于使用选择性沉积技术的实施例,并且特别用于支撑多裸片或者复杂的且阻抗发生变化的引线的实施例。在最后步骤中,对于非腔体封装体,可以使用包覆成型来封装引线(59)。在US20120066894和美国专利6,770,822中还描述了替代实施例和附加或变体的方法步骤,其中这两者的内容通过引用全部包含于此。
在特定实施例中,可以对所述的工艺进行修改和添加。例如,可以通过使用化学(电泳)、机械(表面张力)、接触反应(底漆)、电磁[UV,IR]、电子束、其它适当技术的各种方法来实现提供电介质的共形涂层。由于电泳聚合物可以依赖于如下的自限反应,因此这些电泳聚合物特别有利,其中这些自限反应可以通过调整工艺参数以及/或者针对电泳涂捕溶液的简单加成、浓度、化学、热或定时变化,来容易地沉积精确的厚度。
在其它实施例中,可以使用电介质预涂焊线来形成引线。尽管市售的涂布配线通常在电介质厚度方面与创建例如50欧姆的引线所需的配线相比在电介质厚度上更薄,但可以使用以上所论述的电介质沉积步骤来增加电介质厚度以设置期望的阻抗。使用这些预涂配线可以简化创建共轴所需的其它工艺步骤,并且可以使得所需的气相沉积电介质的层更薄且处理时间更快,从而创建接地通孔。可以使用预涂焊线来防止狭窄地间隔开或交叉的引线发生短路。在特定实施例中,预涂焊线可以具有由光敏材料制成的电介质以使得能够进行选择性图案化技术。
在其它实施例中,可以使用电介质聚对二甲苯。聚对二甲苯(Parylene)是用作水分阻挡层和电介质阻抗层的各种化学气相沉积聚(对苯二亚甲基)聚合物的商品名称。可以使用改进的聚对二甲苯沉积系统在生长受限的缩合反应中形成聚对二甲苯,其中在该聚对二甲苯沉积系统中,使裸片、衬底和引线与照相底板对齐,从而使得EM辐射(IR、UV或其它)能够以精确方式入射,这样引起电介质的选择性生长率。有利地,这样使针对用以创建接触通孔、聚对二甲苯的大量去除等的工艺的需求为最低限度或者不需要这些工艺。
已知聚对二甲苯和其它电介质在存在氧、水蒸汽和热的情况下由于氧断裂而发生降解。损坏可能受到形成优良的氧蒸汽阻挡层的金属层所限制,其中厚度为3~5微米的薄层能够形成真正的气密界面。可选地,如果选择性地去除了金属、或者由于电气、热或制造要求因而金属没有沉积在特定区域中,则可以使用各种基于聚合物的蒸汽氧阻挡层,其中聚乙烯醇(PVA)是广泛地使用的聚合物。可以对这些聚合物进行顶部密封、丝网印刷、用蜡纸印刷、门式分配、喷涂到将暴露至氧或H2O蒸汽环境的聚对二甲苯表面上。有利地,由于可能需要高成本的聚对二甲苯或其它对氧敏感的更厚层,因此使用防潮层聚合物可以是降低成本策略的一部分。
如应当理解,所述的所有方法步骤全部受益于各种选择性沉积技术。选择性沉积可以通过物理遮掩、直接聚合物沉积、光致抗蚀法、或者用于在沉积时确保金属芯、电介质层或其它最外层上的差分沉积厚度的任何其它适当方法。尽管选择性沉积允许使用加成法来构建引线,但还允许使用去除电介质或金属以形成多个阻抗互连件的减成技术。例如,可以适当地对利用一个或多个裸片所填充的封装体进行引线接合,以使所有的封装体和器件压焊点相互连接。如针对例示裸片封装体的制造所用的步骤和结构的图3看出,可以将电介质涂层200以厚度X~A沉积(步骤A)到焊线金属导体202上,其中A是二次互连阻抗所需的电介质的厚度。例如可以通过蚀刻步骤去除(步骤B)二次阻抗焊线电介质,之后进行第二涂层204的沉积(步骤C),之后进行这两个互连件的金属化(步骤D)。该减成工艺将创建两个明显不同的阻抗的焊线。
在针对图4所示的实施例中,说明包括具有良好定义的且可调整的引线电气特性的电介质和金属涂布引线的球栅阵列(BGA)封装体。
BGA是广泛地用于集成电路的表面安装封装,并且由于BGA的底表面整体可用于连接压焊点,因此与双列直插、引线框架或其它扁平封装体相比,BGA通常可以提供更多的互连引脚。在许多类型的BGA封装体中,将裸片216贴装至具有连接至连接压焊点的可填充通孔220的衬底218。焊线212、214可用于使顶侧的裸片216连接至压焊点/通孔220,结果提供从衬底的顶侧向底部的电气接线。在BGA封装件中,利用粘性焊剂将焊料球222贴装至封装体的底部并且保持在适当位置,直到焊接至印刷电路板或其它衬底为止。如这里所述,可以利用具有电介质层和可外接地金属层的改进了的引线来替换传统的BGA封装体的焊线。这些引线可以在内芯和外金属层内具有变化的电介质厚度,并且可以选择性地优化这些引线以具有特定阻抗,从而可被选择成至少部分基于电介质层厚度而不同或良好地匹配。如从图6看出,支撑长的引线212和短的引线214这两者。
更详细地,改进了的BGA封装体的组件可以要求将裸片以面朝上的方式贴装至衬底,从而支撑衬底中的在通孔周围以邻接方式形成的连接压焊点。针对所需的各互连件适当地对该组件进行引线接合,其中在衬底上的连接压焊点和裸片上的连接压焊点之间形成焊线。低频率和功率的输入连接至低频率的信号引线,而高频率的输入和输出连接至高频率的信号引线。在一些实施例中,低频率和功率的输入的厚度可以不同于高频率的信号引线的厚度。然后对组件进行任何基本保形的电介质材料的涂布。由于聚对二甲苯的低成本、便于真空沉积和优良的性能特性,因此可以使用聚对二甲苯。可以通过蚀刻、热降解或激光烧蚀来选择性地去除电介质层的在引线框架贴装点附近的一小部分,从而形成向接地接触点或接地屏蔽层的电气连接。同样,可以在裸片连接压焊点附近去除电介质层的一小部分,以允许接地连接。在将金属化层涂敷到电介质层的顶部之后在结构中接地,从而形成接地屏蔽。应当考虑到趋肤深度和DC电阻问题来选择优选的金属层的厚度,并且该厚度应主要包括诸如银、铜或金等的优良电气导体。对于大多数应用,1微米的涂层厚度对于功能而言是足够的,但更厚的涂层有助于使引线之间的串扰为最低限度。可以通过光刻法或其它掩蔽方法与镀法或其它选择性沉积方法的组合来在定义区域中添加这些涂层。可以通过将包覆成型件或盖放置在裸片上、之后进行切割(切单)并进行测试,来完成封装体。
可选地,在针对图5所示的实施例中,可以通过形成包含单独的封装部位和外侧框架部分的二维阵列的引线框架带材来制造包括从裸片延伸至引线框架的基于低成本的引线框架的裸片封装体300。引线框架制造是传统的,并且可以包括通过蚀刻、冲压或电沉积的单独引线的形成。可以将引线框架带材放置在包括但不限于注塑成型或传递成形设备的模具中。将适当的电介质材料(优选为诸如市售的环氧模塑料)注入、泵入或传递到模具内,以实现引线框架/模具材料复合结构。模具材料的性质对于这些模具材料的介质常数、损耗切线和电色散性质以及这些模具材料的温度、湿度和其它机械性能属性而言很重要。
对如此得到的复合引线框架带材上的各封装部位清洗脱模材料和/或溢料飞边,并且准备好将金属饰面沉积在引线框架的暴露的金属部分上。这可以通过诸如浸没或电镀等的镀技术来实现,并且将选择这些金属以用于腐蚀抑制并且容易进行引线接合。这种涂饰的示例是薄的镍层(以供保护),之后是金层(向焊线添加保护和能力)。然后,可以利用贴装至基底的所需裸片填充如此得到的模制引线框架带材的各封装部位,其中针对特定封装应用的机械性质和热性质选择裸片贴装材料。然后,针对所需的各互连件适当地对如此得到的组件进行引线接合,其中在引线框架上的引线和裸片上的连接压焊点之间形成焊线。低频率和功率的输入连接至低频率的信号引线,而高频率的输入和输出连接至高频率的信号引线。在一些实施例中,低频率和功率的输入的厚度可以不同于高频率的信号引线的厚度。
如上述的BGA封装体210那样,然后对所填充的引线框架带材进行包括聚对二甲苯的任何基本保形的电介质材料的涂布。在聚对二甲苯的情况下,可以优选利用诸如具有丙烯酸粘合剂的真空兼容的聚酰亚胺等的胶带或者相似材料对封装体的底部进行掩蔽以防止沉积到引线的最终将贴装至PCB的区域上。这将便于在后续步骤进行更容易的焊接。可以通过蚀刻、热降解或激光烧蚀来选择性地去除电介质层的在引线框架贴装点附近的一小部分,从而形成向接地接触点或接地屏蔽层的电气连接。同样,可以在裸片连接压焊点附近去除电介质层的一小部分,以允许接地连接。在将金属化层涂敷到电介质层的顶部之后在结构中接地,从而形成接地屏蔽。应当考虑到趋肤深度和DC电阻问题来选择优选的金属层的厚度,并且该厚度应主要包括诸如银、铜或金等的优良电气导体。对于大多数应用,1微米的涂层厚度对于功能而言是足够的,但更厚的涂层有助于使引线之间的串扰为最低限度。可以通过光刻法或其它掩蔽方法与镀法或其它选择性沉积方法的组合来在定义区域中添加这些涂层。可以通过将包覆成型件或盖放置在裸片上、之后进行切割(切单)并进行测试,来完成封装体。
特别地,本发明涉及具有金属芯、电介质层、可接地的金属以及一个或多个防潮涂层(或塑封胶料)的引线。
此外,本发明涉及一种裸片封装体,包括:裸片,其具有多个连接压焊点;裸片衬底,其支撑多个连接元件;引线,其连接在所述裸片和所述裸片衬底之间,所述引线包括具有所定义的芯直径的第一金属芯、包围所述第一金属芯的具有第一电介质厚度的电介质层、至少部分包围所述电介质层的外金属层、以及防潮涂层。
此外,本发明涉及一种参考图1所述的制造方法。

Claims (15)

1.一种引线,其具有金属芯、电介质层和可接地的金属,其特征在于,所述引线还包括至少一个防潮涂层。
2.根据权利要求1所述的引线,其特征在于,所述引线具有用以促进粘附于塑封料的附加涂层。
3.根据权利要求1或2所述的引线,其特征在于,电介质至少部分包围所述金属芯,而所述电介层至少部分由可接地的金属涂层包围。
4.根据权利要求1至3中任一项所述的引线,其特征在于,所述金属涂层仅部分包围所述电介质层。
5.根据权利要求1至4中任一项所述的引线,其特征在于,所述引线还具有附加金属层和/或附加电介质层。
6.根据权利要求1至5中任一项所述的引线,其特征在于,所述引线还具有经由薄的金属层分隔开的具有不同厚度的多层电介质,其中最外层接地。
7.根据权利要求1至6中任一项所述的引线,其特征在于,用于提供优良的防潮层和/或抗氧降解性的高性能电介质薄薄地沉积在其它电介质材料形成的厚的层上。
8.一种裸片封装体,包括:
裸片,其具有多个连接压焊点;
裸片衬底,其支撑多个连接元件;以及
根据权利要求1至7中任一项所述的一个或多个引线,其连接在所述裸片和所述裸片衬底之间。
9.根据权利要求8所述的裸片封装体,其特征在于,所述引线包括具有所定义的芯直径的第一金属芯、包围所述第一金属芯的具有第一电介质厚度的电介质层、以及至少部分包围所述电介质层的外金属层,其特征在于,所述引线还具有防潮外涂层。
10.根据权利要求8或9所述的裸片封装体,其特征在于,对所述裸片进行包覆成型、固化和/或切单以供使用。
11.一种用于制造根据权利要求8至10中任一项所述的裸片封装体的方法,包括以下步骤:
使用引线接合以提供引线的金属芯与裸片和衬底连接压焊点这两者之间的互连;
利用电介质涂布所述金属芯;
进行金属化;以及
沉积至少一个防潮层。
12.根据权利要求11所述的方法,其中,还包括以下步骤:涂敷附加涂层以促进粘附于塑封料。
13.根据权利要求11或12所述的方法,其中,还包括以下步骤:对所述裸片进行包覆成型、固化和/或切单。
14.根据权利要求11至13中任一项所述的方法,其中,还包括以下步骤:去除所述电介质的至少一部分以使接地压焊点暴露,之后进行金属化以使金属化层连接至所述接地压焊点。
15.根据权利要求11至14中任一项所述的方法,其中,还包括以下步骤:去除金属层和/或附加金属层的至少一部分,之后沉积附加电介质层和/或所述至少一个防潮层。
CN201480038198.0A 2013-07-03 2014-07-02 裸片封装体所用的涂布焊线和所述涂布焊线的制造方法 Active CN105408998B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361842951P 2013-07-03 2013-07-03
US61/842,951 2013-07-03
PCT/EP2014/001821 WO2015000592A1 (en) 2013-07-03 2014-07-02 Coated bond wires for die packages and methods of manufacturing said coated bond wires

Publications (2)

Publication Number Publication Date
CN105408998A true CN105408998A (zh) 2016-03-16
CN105408998B CN105408998B (zh) 2018-07-24

Family

ID=51062772

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480038198.0A Active CN105408998B (zh) 2013-07-03 2014-07-02 裸片封装体所用的涂布焊线和所述涂布焊线的制造方法

Country Status (9)

Country Link
US (2) US9997489B2 (zh)
EP (1) EP3017468B1 (zh)
JP (1) JP6730182B2 (zh)
KR (1) KR102038022B1 (zh)
CN (1) CN105408998B (zh)
CA (1) CA2915404C (zh)
HK (1) HK1224431A1 (zh)
TW (1) TWM506372U (zh)
WO (1) WO2015000592A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016109349A1 (de) * 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120286A (ja) * 1992-10-02 1994-04-28 Matsushita Electron Corp 半導体装置
US6107690A (en) * 1995-09-26 2000-08-22 Micron Technology, Inc. Coated semiconductor die/leadframe assembly and method for coating the assembly
US20030090001A1 (en) * 2001-11-13 2003-05-15 Kulicke And Soffa Investments, Inc. Wirebonded semiconductor package structure and method of manufacture

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61287155A (ja) 1985-06-14 1986-12-17 Hitachi Ltd 半導体装置及び半導体装置の製造方法
JPH0276249A (ja) 1988-09-10 1990-03-15 Semiconductor Energy Lab Co Ltd 電子装置およびその作製方法
US5276351A (en) * 1988-10-17 1994-01-04 Semiconductor Energy Laboratory Co., Ltd. Electronic device and a manufacturing method for the same
US5355016A (en) * 1993-05-03 1994-10-11 Motorola, Inc. Shielded EPROM package
US5685071A (en) * 1995-06-05 1997-11-11 Hughes Electronics Method of constructing a sealed chip-on-board electronic module
AU1310399A (en) * 1997-11-05 1999-05-24 Robert A. Martin Chip housing, methods of making same and methods for mounting chips therein
US6444501B1 (en) * 2001-06-12 2002-09-03 Micron Technology, Inc. Two stage transfer molding method to encapsulate MMC module
US7723162B2 (en) * 2002-03-22 2010-05-25 White Electronic Designs Corporation Method for producing shock and tamper resistant microelectronic devices
US6873049B2 (en) * 2003-07-31 2005-03-29 The Boeing Company Near hermetic power chip on board device and manufacturing method therefor
DE102004032605B4 (de) * 2004-07-05 2007-12-20 Infineon Technologies Ag Halbleiterbauteil mit einem Halbleiterchip und elektrischen Verbindungselementen zu einer Leiterstruktur
JP2008227126A (ja) * 2007-03-13 2008-09-25 National Institute Of Advanced Industrial & Technology 微細同軸ワイヤー、その製造方法、及び半導体装置
US8581113B2 (en) * 2007-12-19 2013-11-12 Bridgewave Communications, Inc. Low cost high frequency device package and methods
KR101155904B1 (ko) * 2010-01-04 2012-06-20 삼성모바일디스플레이주식회사 유기 발광 표시 장치
US9508622B2 (en) * 2011-04-28 2016-11-29 Freescale Semiconductor, Inc. Method for protecting copper wire bonds on aluminum pads of a semiconductor device from corrosion

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120286A (ja) * 1992-10-02 1994-04-28 Matsushita Electron Corp 半導体装置
US6107690A (en) * 1995-09-26 2000-08-22 Micron Technology, Inc. Coated semiconductor die/leadframe assembly and method for coating the assembly
US20030090001A1 (en) * 2001-11-13 2003-05-15 Kulicke And Soffa Investments, Inc. Wirebonded semiconductor package structure and method of manufacture

Also Published As

Publication number Publication date
US9997489B2 (en) 2018-06-12
HK1224431A1 (zh) 2017-08-18
US20170271296A1 (en) 2017-09-21
WO2015000592A1 (en) 2015-01-08
KR20160029759A (ko) 2016-03-15
EP3017468B1 (en) 2020-09-02
TWM506372U (zh) 2015-08-01
CA2915404C (en) 2020-06-23
JP6730182B2 (ja) 2020-07-29
JP2016526792A (ja) 2016-09-05
EP3017468A1 (en) 2016-05-11
KR102038022B1 (ko) 2019-11-26
US20170125370A1 (en) 2017-05-04
CN105408998B (zh) 2018-07-24
CA2915404A1 (en) 2015-01-08

Similar Documents

Publication Publication Date Title
CN105359268B (zh) 高带宽互连所用的隔热结构
CN105474388B (zh) 电磁干扰互连低的裸片封装体
CN105359267A (zh) 包括具有至少部分被电介质层包围的多个金属芯的互连件的互连系统
CN105518856A (zh) 具有选择性地修改的电气性质的引线的电子器件
CN105359263A (zh) 包括具有电介质涂层和金属涂层的配线的无衬底裸片封装体及其制造方法
CN105408998A (zh) 裸片封装体所用的涂布焊线和所述涂布焊线的制造方法
CN105378915B (zh) 混合阻抗的焊线连接及其连接方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant