JP6730182B2 - ダイパッケージ用の被覆されたボンドワイヤおよび被覆されたボンドワイヤの製造方法 - Google Patents
ダイパッケージ用の被覆されたボンドワイヤおよび被覆されたボンドワイヤの製造方法 Download PDFInfo
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- JP6730182B2 JP6730182B2 JP2016522334A JP2016522334A JP6730182B2 JP 6730182 B2 JP6730182 B2 JP 6730182B2 JP 2016522334 A JP2016522334 A JP 2016522334A JP 2016522334 A JP2016522334 A JP 2016522334A JP 6730182 B2 JP6730182 B2 JP 6730182B2
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- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
- H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/85444—Gold (Au) as principal constituent
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Chemically Coating (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
Claims (11)
- 金属コアと、前記金属コアを少なくとも部分的に被覆し、さらに、接地接続可能な金属被覆によって少なくとも部分的に被覆される誘電体層とを有するリード線であって、
前記リード線は、前記金属被覆されていない領域を保護するための少なくとも1つの蒸気バリア被覆をさらに有し、且つ、前記リード線は、モールドコンパウンドへの接着を促進するための付加的な被覆を有し、
前記リード線は、薄い金属層によって隔てられた厚さの異なる複数の誘電体層を有し、最外層は接地接続されていることを特徴とするリード線。 - 前記金属被覆は、前記誘電体層を部分的にのみ被覆することを特徴とする請求項1に記載のリード線。
- 前記リード線は、付加的な金属層および付加的な誘電体層の少なくとも一方を有することを特徴とする請求項1または2に記載のリード線。
- 蒸気バリアおよび酸素分解耐性の少なくとも一方を提供する誘電体が別の誘電体材料の厚い層の上に薄く被着されることを特徴とする請求項1から3のいずれか一項に記載のリード線。
- 複数の接続パッドを有するダイと、
複数の接続素子を支持するダイ基板と、
前記ダイと前記ダイ基板との間に接続された請求項1から4のいずれか一項に記載の1以上のリード線と、
を備えたダイパッケージ。 - 前記リード線は、規定のコア径を持つ第1の金属コアと、前記第1の金属コアを被覆する第1の誘電体厚を持つ誘電体層と、前記誘電体層を少なくとも部分的に被覆する外側金属層とを備え、前記リード線は、蒸気バリアオーバーコートを有することを特徴とする請求項5に記載のダイパッケージ。
- 前記ダイは、オーバーモールドが施され、さらに硬化およびシンギュレーションの少なくとも一方が施されて使用されることを特徴とする請求項5または6に記載のダイパッケージ。
- ワイヤボンディングを使用して、リード線の金属コアをダイおよび基板の両方の接続パッドへの相互接続を行うステップと、
前記金属コアを誘電体で被覆するステップと、
金属層で被覆するステップと、
少なくとも1つの蒸気バリアの被覆を施すステップと、
モールドコンパウンドへの接着を促進するための付加的な被覆を施すステップと、
を有する請求項5から7のいずれか一項に記載のダイパッケージの製造方法。 - 前記ダイにオーバーモールドを施し、硬化およびシンギュレーションの少なくとも一方を施すステップをさらに有する請求項8に記載の方法。
- 前記誘電体の少なくとも一部を除去して前記ダイの前記接続パッドを露出し、続いて、前記リード線の前記金属層を前記ダイの前記接続パッドに接続するための金属被覆を施すステップをさらに有する請求項8または9に記載の方法。
- 前記金属層の少なくとも部分的な除去と、それに続く付加的な誘電体層および少なくとも1つの蒸気バリアの被覆の少なくとも一方を施すステップをさらに有する請求項8から10のいずれか一項に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361842951P | 2013-07-03 | 2013-07-03 | |
US61/842,951 | 2013-07-03 | ||
PCT/EP2014/001821 WO2015000592A1 (en) | 2013-07-03 | 2014-07-02 | Coated bond wires for die packages and methods of manufacturing said coated bond wires |
Publications (2)
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JP2016526792A JP2016526792A (ja) | 2016-09-05 |
JP6730182B2 true JP6730182B2 (ja) | 2020-07-29 |
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JP2016522334A Active JP6730182B2 (ja) | 2013-07-03 | 2014-07-02 | ダイパッケージ用の被覆されたボンドワイヤおよび被覆されたボンドワイヤの製造方法 |
Country Status (9)
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US (2) | US9997489B2 (ja) |
EP (1) | EP3017468B1 (ja) |
JP (1) | JP6730182B2 (ja) |
KR (1) | KR102038022B1 (ja) |
CN (1) | CN105408998B (ja) |
CA (1) | CA2915404C (ja) |
HK (1) | HK1224431A1 (ja) |
TW (1) | TWM506372U (ja) |
WO (1) | WO2015000592A1 (ja) |
Families Citing this family (1)
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DE102016109349A1 (de) * | 2016-05-20 | 2017-11-23 | Infineon Technologies Ag | Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts |
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JPS61287155A (ja) | 1985-06-14 | 1986-12-17 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
JPH0276249A (ja) | 1988-09-10 | 1990-03-15 | Semiconductor Energy Lab Co Ltd | 電子装置およびその作製方法 |
US5276351A (en) * | 1988-10-17 | 1994-01-04 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and a manufacturing method for the same |
JPH06120286A (ja) | 1992-10-02 | 1994-04-28 | Matsushita Electron Corp | 半導体装置 |
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WO1999023700A1 (en) * | 1997-11-05 | 1999-05-14 | Martin Robert A | Chip housing, methods of making same and methods for mounting chips therein |
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US6608390B2 (en) * | 2001-11-13 | 2003-08-19 | Kulicke & Soffa Investments, Inc. | Wirebonded semiconductor package structure and method of manufacture |
US7723162B2 (en) * | 2002-03-22 | 2010-05-25 | White Electronic Designs Corporation | Method for producing shock and tamper resistant microelectronic devices |
US6873049B2 (en) * | 2003-07-31 | 2005-03-29 | The Boeing Company | Near hermetic power chip on board device and manufacturing method therefor |
DE102004032605B4 (de) * | 2004-07-05 | 2007-12-20 | Infineon Technologies Ag | Halbleiterbauteil mit einem Halbleiterchip und elektrischen Verbindungselementen zu einer Leiterstruktur |
JP2008227126A (ja) * | 2007-03-13 | 2008-09-25 | National Institute Of Advanced Industrial & Technology | 微細同軸ワイヤー、その製造方法、及び半導体装置 |
US8581113B2 (en) * | 2007-12-19 | 2013-11-12 | Bridgewave Communications, Inc. | Low cost high frequency device package and methods |
KR101155904B1 (ko) * | 2010-01-04 | 2012-06-20 | 삼성모바일디스플레이주식회사 | 유기 발광 표시 장치 |
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2014
- 2014-07-02 TW TW103211713U patent/TWM506372U/zh not_active IP Right Cessation
- 2014-07-02 KR KR1020157037288A patent/KR102038022B1/ko active IP Right Grant
- 2014-07-02 US US14/902,183 patent/US9997489B2/en active Active
- 2014-07-02 CN CN201480038198.0A patent/CN105408998B/zh active Active
- 2014-07-02 WO PCT/EP2014/001821 patent/WO2015000592A1/en active Application Filing
- 2014-07-02 CA CA2915404A patent/CA2915404C/en active Active
- 2014-07-02 EP EP14734743.9A patent/EP3017468B1/en active Active
- 2014-07-02 JP JP2016522334A patent/JP6730182B2/ja active Active
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2016
- 2016-11-03 HK HK16112688.4A patent/HK1224431A1/zh unknown
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Also Published As
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EP3017468A1 (en) | 2016-05-11 |
EP3017468B1 (en) | 2020-09-02 |
CA2915404C (en) | 2020-06-23 |
KR102038022B1 (ko) | 2019-11-26 |
US20170271296A1 (en) | 2017-09-21 |
HK1224431A1 (zh) | 2017-08-18 |
CN105408998B (zh) | 2018-07-24 |
US9997489B2 (en) | 2018-06-12 |
CN105408998A (zh) | 2016-03-16 |
CA2915404A1 (en) | 2015-01-08 |
JP2016526792A (ja) | 2016-09-05 |
WO2015000592A1 (en) | 2015-01-08 |
TWM506372U (zh) | 2015-08-01 |
KR20160029759A (ko) | 2016-03-15 |
US20170125370A1 (en) | 2017-05-04 |
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