CN105393237B - 多相位时钟生成方法 - Google Patents

多相位时钟生成方法 Download PDF

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Publication number
CN105393237B
CN105393237B CN201480041353.4A CN201480041353A CN105393237B CN 105393237 B CN105393237 B CN 105393237B CN 201480041353 A CN201480041353 A CN 201480041353A CN 105393237 B CN105393237 B CN 105393237B
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China
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received
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CN201480041353.4A
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English (en)
Chinese (zh)
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CN105393237A (zh
Inventor
C·李
G·A·威利
R·D·韦斯特费尔特
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Qualcomm Inc
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Qualcomm Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/50—Systems for transmission between fixed stations via two-conductor transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0041—Delay of data signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN201480041353.4A 2013-07-22 2014-07-22 多相位时钟生成方法 Active CN105393237B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361857212P 2013-07-22 2013-07-22
US61/857,212 2013-07-22
US14/336,977 US9130735B2 (en) 2013-07-22 2014-07-21 Multi-phase clock generation method
US14/336,977 2014-07-21
PCT/US2014/047586 WO2015013259A1 (en) 2013-07-22 2014-07-22 Multi-phase clock generation method

Publications (2)

Publication Number Publication Date
CN105393237A CN105393237A (zh) 2016-03-09
CN105393237B true CN105393237B (zh) 2019-03-01

Family

ID=52343572

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480041353.4A Active CN105393237B (zh) 2013-07-22 2014-07-22 多相位时钟生成方法

Country Status (5)

Country Link
US (1) US9130735B2 (cg-RX-API-DMAC7.html)
EP (1) EP3025242B1 (cg-RX-API-DMAC7.html)
JP (1) JP6185171B2 (cg-RX-API-DMAC7.html)
CN (1) CN105393237B (cg-RX-API-DMAC7.html)
WO (1) WO2015013259A1 (cg-RX-API-DMAC7.html)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9215063B2 (en) * 2013-10-09 2015-12-15 Qualcomm Incorporated Specifying a 3-phase or N-phase eye pattern
US9621332B2 (en) 2015-04-13 2017-04-11 Qualcomm Incorporated Clock and data recovery for pulse based multi-wire link
US9812057B2 (en) 2015-08-05 2017-11-07 Qualcomm Incorporated Termination circuit to reduce attenuation of signal between signal producing circuit and display device
JP2019503789A (ja) * 2016-01-25 2019-02-14 アダプティックス エルティーディー 分散ｘ線発生器のアレイを有する医療撮像システム
CN106385251A (zh) * 2016-09-14 2017-02-08 豪威科技(上海)有限公司 时钟数据恢复电路
US10630295B2 (en) * 2018-04-23 2020-04-21 Synaptics Incorporated Device and method for detecting signal state transition
US10313068B1 (en) * 2018-04-24 2019-06-04 Qualcomm Incorporated Signal monitoring and measurement for a multi-wire, multi-phase interface
US11095425B2 (en) * 2019-10-25 2021-08-17 Qualcomm Incorporated Small loop delay clock and data recovery block for high-speed next generation C-PHY
KR20210088807A (ko) 2020-01-06 2021-07-15 삼성전자주식회사 전자 장치 및 전자 장치의 동작 방법
US11018658B1 (en) 2020-01-06 2021-05-25 Samsung Electronics Co., Ltd. Electronic device and operating method of electronic device
US11092646B1 (en) * 2020-02-18 2021-08-17 Qualcomm Incorporated Determining a voltage and/or frequency for a performance mode
US11545980B1 (en) * 2021-09-08 2023-01-03 Qualcomm Incorporated Clock and data recovery for multi-phase, multi-level encoding

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2453185A (en) * 2007-09-26 2009-04-01 Xintronix Ltd Clock recovery in a sampled received signal including removal of ISI effects from data samples used to detect zero-crossing
CN101551990A (zh) * 2008-04-02 2009-10-07 东部高科股份有限公司 数据接收装置
US20090296867A1 (en) * 2007-12-12 2009-12-03 Viet Linh Do ISI Pattern-Weighted Early-Late Phase Detector with Jitter Correction

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3992581A (en) * 1975-09-02 1976-11-16 Sperry Rand Corporation Phase locked loop NRZ data repeater
US4419760A (en) * 1982-01-29 1983-12-06 Motorola Inc. Augmented phase-locked loop for very wide range acquisition and method therefor
JP2000307561A (ja) * 1999-04-21 2000-11-02 Hitachi Ltd バスシステム装置
JP2001339376A (ja) * 2000-05-26 2001-12-07 Nec Yamagata Ltd 同期回路
US7512848B1 (en) 2004-09-29 2009-03-31 Xilinx, Inc. Clock and data recovery circuit having operating parameter compensation circuitry
JP2007318807A (ja) * 2006-04-27 2007-12-06 Matsushita Electric Ind Co Ltd 多重差動伝送システム
WO2007145160A1 (ja) * 2006-06-16 2007-12-21 Panasonic Corporation データ送信装置及びデータ送信方法
US20080129357A1 (en) * 2006-11-30 2008-06-05 Chlipala James D Adaptive Integrated Circuit Clock Skew Correction
US9231790B2 (en) 2007-03-02 2016-01-05 Qualcomm Incorporated N-phase phase and polarity encoded serial interface
WO2008151251A1 (en) 2007-06-05 2008-12-11 Rambus, Inc. Techniques for multi-wire encoding with an embedded clock
KR100898305B1 (ko) * 2007-10-08 2009-05-19 주식회사 티엘아이 3라인 차동 신호법을 위한 클락 임베디드 차동 데이터수신장치
KR101606402B1 (ko) 2009-12-29 2016-03-28 주식회사 동부하이텍 클록 복원 회로
JP2011188042A (ja) * 2010-03-05 2011-09-22 Nec Corp デジタル信号処理回路、デジタル信号処理方法、及び、プログラム
US8624645B2 (en) 2011-08-15 2014-01-07 Nanya Technology Corp. Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
TW201404105A (zh) 2012-07-06 2014-01-16 Novatek Microelectronics Corp 時脈資料回復電路及方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2453185A (en) * 2007-09-26 2009-04-01 Xintronix Ltd Clock recovery in a sampled received signal including removal of ISI effects from data samples used to detect zero-crossing
US20090296867A1 (en) * 2007-12-12 2009-12-03 Viet Linh Do ISI Pattern-Weighted Early-Late Phase Detector with Jitter Correction
CN101551990A (zh) * 2008-04-02 2009-10-07 东部高科股份有限公司 数据接收装置

Also Published As

Publication number Publication date
US9130735B2 (en) 2015-09-08
CN105393237A (zh) 2016-03-09
JP6185171B2 (ja) 2017-08-23
EP3025242B1 (en) 2017-04-05
JP2016528813A (ja) 2016-09-15
EP3025242A1 (en) 2016-06-01
WO2015013259A1 (en) 2015-01-29
US20150023454A1 (en) 2015-01-22

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