GB2453185A

GB2453185A - Clock recovery in a sampled received signal including removal of ISI effects from data samples used to detect zero-crossing

Info

Publication number: GB2453185A
Application number: GB0802303A
Authority: GB
Inventors: Nicholas Weiner
Original assignee: Xintronix Ltd
Current assignee: Xintronix Ltd
Priority date: 2007-09-26
Filing date: 2008-02-07
Publication date: 2009-04-01
Also published as: GB0802303D0; TW200922252A; GB0718831D0; WO2009040371A1

Abstract

A zero-crossing of a sampled received signal can be determined by looking at the values and polarities of successive samples using, e.g., the Gardner algorithm. However where the signal is subject to inter-symbol interference (ISI) these values are affected by "contributions" from previous and following symbols in the signal (fig.15, not shown). The present invention seeks to compensate for ISI by subtracting these contributions from a sample between first and second samples having opposite polarities, and therefore potentially a zero-crossing point. The values of the first and second samples are not included in the caalculation. The contribution may be expressed as, e.g., a weighted summation, hash function or other function of samples immediately preceding and following the first and second samples. The calculation is done in an equaliser (171) and the output may be applied to a PLL for clock recovery.

Description

CLOCK RECOVERY

BACKGROUND OF THE INVENTION

This invention relates to the sampling of a data signal, recovery of data from a data signal, and to techniques for the improved recovery of a clock signal from a data signal.

Digital data is typically transmitted over a baseband communications channel as a sequence of distinct "symbols'. Two symbol types are used in the case of binary communications systems, although a larger number may be used in other systems. As a waveform representing a sequence of symbols travels along a communications channel, the waveform becomes distorted due a spreading of the energy transmitted in respect of each distinct symbol. The symbols arriving at the receiving end of the channel therefore overlap in time. This is known as inter-symbol-interference (lSl). ISI makes it difficult to recover the digital data from the received waveform.

Both optical and electrical transmission media suffer from inter-symbol interference, which is caused by dispersion, reflection and filtering effects in electrical and optical cables and associated interface components. It may also result from the close proximity of elemental storage regions on magnetic and optical storage devices.

ISI becomes more severe as data rates are increased and as communication channel lengths increase. For example, for electrical cables used within computing facilities and for circuit board traces, severe ISI typically limits channel lengths/speeds once data rates reach multiple giga-bits-per-second (Gbps).

Similarly, ISI provides a limit on the maximum distance between repeaters on long stretches of fibre optic cable. For both electrical and optical communications, the severity of the ISI and the consequent speed/length limitation depends upon the precise make-up of the communications medium.

Over recent years much attention has been paid to overcoming lSl speed/length limitations by the use of signal processing at the receiver. Receiver signal processing techniques may be divided into two categories: i) time sampled and ii) continuous-time. It is generally believed that time sampled techniques provide superior results (fewer receive errors), but such techniques depend upon the availability of a clock signal synchronous with the data represented by the received waveform. Typically the clock signal is recovered from the received waveform, but this is problematic in the case of a received waveform that suffers from severe ISI since there is no clear separation of the symbols comprising the waveform.

The recovery of a clock signal from a received waveform is generally performed using a phase locked loop (PLL). Figure 1 shows the basic components of a PLL.

These are: a phase detector (PD) 11; a filter 13; and a voltage controlled oscillator (VCO) or phase rotator 15 (throughout this document, the term VCO should be read as "VCO or phase rotator"). The phase detector measures the difference between the current phase of the recovered clock and an ideal phase for sampling the received waveform. Figure 2 shows a typical arrangement in which such a PLL 21 is used within a clock and data recovery unit (a "CDR"). The recovered data-rate clock signal 23 is used to clock a sampling unit such as a flip-flop 25 so that the received signal is sampled at the frequency and phase of the recovered clock signal.

It is straightforward to recover a clock from a received waveform that does not suffer from ISI. A portion of such a waveform 33, along with the recovered clock signal 31 is shown in figure 3. The rising edges of the clock 35 determine the times at which the waveform is to be sampled and from the figure can be seen to coincide with the maxima 37 and minima 39 of the waveform that represent the binary data bits.

Figure 4 shows the received waveform of figure 3 as an eye diagram, illustrating that the phase of the waveform at each of the "zero crossings" is the same. This makes the zero crossings 41 particularly useful points at which to make measurements so as to establish the frequency and phase of the clock signal. A widely used class of clock recovery PLLs operate by aligning a recovered clock edge with the zero-crossings of the received waveform. Such clock recovery PLLs use "zero-crossing phase detectors" to measure the time difference between recovered clock edges and waveform zero-crossings. Zero-crossing phase detectors may measure these time differences using continuous time circuitry or by sampling the waveform. Sampling phase detectors typically use either one sample per unit clock (baud rate phase detectors) or two samples per unit clock (Nyquist rate phase detectors). Examples of conventional Nyquist rate and baud rate phase detectors are described below.

Zero-crossing phase detectors can use the Gardner algorithm for zero-crossing phase detection when receiving waveforms over a binary channel. The algorithm uses Nyquist rate samples to provides phase error estimates, errork, and may be expressed as follows: errork = (samplek+ -samplek..yjsamplek In the algorithm, samplek�% and samplek. are data samples taken at times separated by I unit interval, and samplek is a phase sample taken midway between them. The term "data sample" refers to a sample of the waveform which is used (or could be used) for data recovery and the term "phase sample" refers to a sample which is useful for clock recovery. In other words, when the clock signal is correctly aligned with the received waveform, the data samples are taken at the midpoint of each symbol and the phase samples at the point between symbols.

Thus, when the two adjacent data samples, samplek.% and sampIek, have opposite signs, the phase sample, samplek, occurs at a data transition and will be zero (this is a zero-crossing point of the waveform).

In variants of this algorithm, recovered data may be used instead of data samples.

This may be expressed as: errork = (btk+ -bit)samplek where bitk+y. and bitk..y. are consecutive recovered bits, each having value +1 or -1.

In this case no phase error information is provided when the two recovered bits have the same value. When they differ, the value of (btk+% -bitk) indicates whether the transition is positive-going or negative-going. This, together with the value of the phase sample, samplek, provides the estimate of the phase error.

Figure 5 illustrates the use of this Gardner algorithm variant in a CDR. The inversion circle on the sampler input represents the fact that the "phase" samples are taken out of phase with the data samples.

In a simplified variant of the algorithm, the phase sample value may be one-bit quantized: errork = (bitk+l, -bit1A).sign(sampIek) The value of errork is -1, 0 or +1. Using this simplified algorithm for phase detection allows ease of implementation at the expense of performance. An implementation of this algorithm is illustrated in figure 6, which shows a schematic diagram of a CDR and a logic diagram of the function of the phase detector logic.

Figure 7 illustrates the use of a Gardner phase detector in a CDR. Data 71 and clock recovery 73 lines are shown separately.

Figure 8 shows an example received waveform 81 suffering from severe ISI with an example synchronous clock signal 83. It is apparent from the figure that a phase cannot be chosen for the clock signal such that the falling edges of the clock 85 always occur at the zero-crossings 87 of the received waveform. Figure *1 9 shows the same received waveform as an eye diagram, illustrating that the phase of the waveform at each zero-crossing is no longer the same.

Conventional phase detectors cannot therefore be used to recover a high quality clock signal directly from this received waveform.

Various techniques have been proposed to improve the recovery of a clock signal from a waveform suffering from severe ISI. These techniques have taken three different approaches to the problem: (i) high-pass filtering for equalization of the received waveform prior to clock recovery; (ii) clock recovery within the processing loop of a data-recovery decision feedback equalizer (DEE); (iii) estimating phase errors at particular zero crossings only, selected in dependence on the recovered data sequence.

Figure 10 shows a conventional CDR preceded by a high-pass filter equalizer 101. Such an equalizer can under certain conditions provide a waveform that sufficiently matches the originally transmitted waveform. This is the approach taken by Yasuo Hidaka in "A 4-Channel 3.1/10.3Gb/s Transceiver Macro with Pattern-Tolerant Adaptive Equalizer", IEEE International Solid-State Circuits Conference, pp. 442-443, 2007. However, in the case of a waveform suffering from severe 1St, and in particular from severe post-cursor ISI, such receivers do not perform as well as DFE receivers.

An example of the second approach is shown in Figure 11, which illustrates clock recovery using a signal taken from within a decision-feedback equalizer (DEE) receiver. In a DEE receiver, post- cursor ISI associated with data already recovered is cancelled from the received waveform. For a waveform without pre-cursor ISI, the resulting waveform matches the originally transmitted waveform at the data sampling instances. Although ISI is not completely cancelled at points between the data sampling instances, the pattern dependence is reduced, allowing conventional zero-crossing CDR techniques to be applied. The general receiver arrangement of Figure 11 has been reported by Bang-Sup Song et al. in "NRZ Timing Recovery Technique for Band-Limited Channels", IEEE International Solid-State Circuits Conference, pp. 194 -195, 1996. These documents describe the use of a Nyquist rate phase detector. Refinements to the approach are described in United States patent 7,242,712. These techniques are limited to use with channels not suffering from pre-cursor 151.

Figure 12 illustrates the third known means of clock recovery in the presence of ISI. By making use of the recovered data sequence, the phase detector estimates phase errors only for selected zero-crossings. Such a receiver is described in Brian S. Leibowitz et al, "A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2'-Order Data-Filtered CDR", IEEE International Solid-State Circuits Conference, pp. 228 -119, 2007; and Hyeon-Min Bae et al, "An MLSE Receiver for Electronic Dispersion Compensation of OC-1 92 Fiber Links", IEEE Journal of Solid-State Circuits, Vol 41, No 11, November 2006.

Two limitations of this approach are: (i) phase error updates are available for only a subset of the zero-crossings, which limits the severity of ISI that can be accommodated and may also limit the ability of the PLL to follow phase variations (jitter) in the received waveform; and (ii) the phase of the recovered clock may not be suitable for data sampling without further processing.

A variation on the second approach is shown in Figure 13 in which the receiver only takes one sample per unit (or symbol) interval -i.e. it uses a baud rate phase detector 131. This variant is described in Balan et al, "A 4.8-6.4Gb/s Serial Lock for Backplane Applications Using Decision Feedback Equalization", IEEE Journal of Solid-State Circuits, Vol 40, No 9, September 2005; and Harwood et al, "A 1 2.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery", IEEE International Solid-State Circuits Conference, 2007, pp. 436-437. In such receivers the sequence of samples is used for data recovery using equalization, and the equalizer output is used for clock phase optimization using the Mueller-Muller algorithm described in K. Mueller, M. Muller "Timing Recovery in Digital Synchronous Data Receivers" IEEE Trans. on Communications, pp. 516-531, May, 1976. This algorithm causes each symbol to be sampled at the phase for which the interference from the previous symbol is equal to that from the next. For symmetrical symbols, this balance occurs when sampling at symbol peaks.

The receivers described by Balan and Harwood combine DFE equalization with Mueller-Muller timing recovery. For correct operation, both depend upon the removal of precursor ISI from the received signal prior to this processing. This is accomplished using linear feed-forward equalization (FFE) for removal of pre-cursor ISI. Two limitations of the approach are (i) the FFE coefficient can not be made auto-adaptive; and (ii) the phase detection method is data pattern dependent, and the recovered clock may suffer for pattern-dependent jitter.

Conventional methods of clock recovery suffer from significant limitations, as described above. There is a need for an improved method of recovering a high quality clock from a received signal suffering from both severe pre-cursor and post-cursor ISI.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention there is provided a method for recovering a clock from a received data signal, the method comprising: receiving a data signal carrying a series of symbols; generating a clock signal in dependence on the data signal; sampling the received data signal at the frequency of the clock signal so as to form a sequence of values dependent on the sampled level of the received data signal, the sequence including first and second values that are adjacent in the sequence; sampling the signal at a further sample time between the times of the first and second samples to form a further value; forming a phase error indicator by estimating the difference between the further value and a representation of the contributions of the symbols indicated by at least some of the values of the sequence to the signal at the further sample time; and adjusting the phase of the clock signal in dependence on the phase error indicator.

Preferably the representation is a weighted aggregate of the at least some of the sequence of values. Preferably the weighted aggregate does not include contributions from the first and second values. The weights applied to the first and second values could be less than the weights applied to one or more other values of the sequence. The one or more other values of the sequence could include all those values within a first predetermined number of values preceding the first and second values and a second predetermined number of values following the first and second values. The first and second predetermined number of values could be equal.

The weight applied to a value of the one or more other values of the sequence could depend upon the position of that value in the sequence relative to the position of the first and second values of the sequence. Preferably the weights are greater for values at positions in the sequence closer to the first and second values of the sequence. The weights applied to the first and second values could be less than the greatest weight applied to any of the one or more other values of the sequence. Preferably the weights applied to the first and second values are zero.

Preferably the weights applied to values of the sequence are adapted in dependence on the phase error indicator. Preferably the weights are adapted using an adaptation algorithm such that the phase error indicator is substantially independent of the one or more other values of the sequence. A zero-forcing adaptation algorithm could be used. A minimum mean square error adaptation algorithm could be used.

Suitably the weights applied to the first and second values are adapted in dependence upon a quality metric of the sequence of values. The quality metric could be an eye opening measure or a bit error rate counter, to give two

examples.

Alternatively, the weights applied to the values of the sequence are predetermined weights.

Suitably the representation is determined by a look-up function using the combined samples of the sequence of samples as a lookup key. The representation determined by the look-up function may be equal to any of the representations determined as specified above.

Preferably the representation is formed by combining values of the sequence in such a way that the representation is insensitive to the first and second values.

Preferably the representation is formed by combining values of the sequence in such a way that the individual contributions of the first and second values to the representation are less than the contributions of one or more other values of the sequence. Preferably the representation is formed by combining values of the sequence in such a way that the individual contributions of the first and second values to the representation have a lower significance than those of one or more other values of the sequence. Suitably the individual contributions of the values of the sequence to the representation are average contributions over a predetermined number of clock cycles.

Suitably the number of non-zero contributions to the representation from the values following the first and second values in the sequence is not equal to the number of non-zero contributions to the representation of the received data signal from the values preceding the first and second values in the sequence. Suitably the only non-zero contributions to the representation are from the three values following the first and second values in the sequence and from the one value preceding the first and second values in the sequence.

Preferably the individual contributions of the first and second values to the representation are zero.

Preferably the step of adjusting the phase of the clock signal is further performed in dependence on the symbols indicated by the first and second values of the sequence. Preferably the phase error indicator and the symbols indicated by the first and second values of the sequence are combined in accordance with a Gardner algorithm.

Preferably the step of sampling the received data signal is performed in-phase with the generated clock signal. Preferably the step of sampling the signal at a further sample time is performed out-of-phase with the generated clock signal.

Preferably the representation is formed by combining values of the sequence in accordance with a predetermined function. Preferably the phase error indicator is determined in a manner such that it is substantially independent of the values of the sequence other than the first and second data values.

Preferably the step of adjusting the phase of the clock signal in dependence on at least the phase error indicator is performed only if the symbols indicated by the first and second values together represent a data transition.

Suitably the symbols are binary symbols or multi-level symbols.

According to a second aspect of the present invention there is provided a receiver arranged to perform a method in accordance with the first aspect of the present and having any of the features described above. Preferably the receiver is further arranged to recover the series of symbols from the data signal.

According to a third aspect of the present invention there is provided a method for recovering a clock from a received data signal, the method comprising: receiving a data signal representing a data sequence; sampling the data signal at the frequency of a local clock signal so as to form a first sequence of values dependent on sampled levels of the received data signal; sampling the data signal at the frequency of the local clock signal and between the samples of the first sequence, so as to form a second sequence of values dependent on sampled levels of the received data signal; the thus sampled data signal having a sampled pulse response composed of interleaved samples corresponding in phase to the first and second sequences, the cursor sample of those samples corresponding in phase to the first sequence and the two samples adjacent to the cursor sample, which correspond in phase to the second sequence, being referred to herein as the central samples; applying a filter to the second sequence to form an output sequence of samples that corresponds to the second sequence, represents the said data sequence and has a pulse response, referred to herein as the output response, with the following properties, in comparison to the pulse response of the received data signal, referred to herein as the input response: (I) the samples of the output response corresponding to the two central samples of the input response are substantially unchanged in value relative to each other; and (ii) the magnitudes of the samples of the output response corresponding to one or more of the other samples of the input response are reduced such that their energy is small relative to the energy of the samples of the output response corresponding to the two central samples of the input response; and adjusting the phase of the local clock signal in dependence on the output sequence.

The method may also comprise adapting the filter in dependence upon the data signal such that the properties (I) and (ii) are satisfied. That step of adapting the filter is preferably performed whilst the data signal is being received. In that way the said properties (i) and (ii) can be satisfied whilst reception is in progress.

The filter may be such as to make use of samples of the first sequence to compute the values of the output sequence.

The filter may be such as to make use of recovered values of data represented by the said received data signal to compute the values of the output sequence.

The phase of the local clock signal may be adjusted in accordance with a Gardner algorithm, and preferably in dependence on the output sequence.

The method may comprise forming each sample of the output sequence from the filter as an estimate of the difference between a sampled value in the second sequence and a representation of the contributions to said sampled value of symbols, representing data in the said data sequence, indicated by at least some of the values of the first sequence.

The received data signal may comprise the summation of symbols representing said data sequence, and the method comprises, for at least some of those symbols, recovering a representation of the respective symbol from the received data signal using the said cursor sample as a cursor sample for that recovery step.

Each member of the said data sequence may have or be permitted to take one of two values. Each member of the said data sequence may have or be permitted to take one of three or more values.

Other features of the third aspect of the invention may be as described above in relation to the first aspect of the invention.

DESCRIPTION OF THE DRAWINGS

The present invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows the components of a typical PLL.

Figure 2 shows a typical arrangement of a PLL within the clock and data recovery unit of a receiver.

Figure 3 shows a portion of a received waveform conveying binary-valued data.

Figure 4 shows the received waveform of figure 3 as an eye diagram.

Figure 5 is a block diagram illustrating a first variation of the Gardner algorithm.

Figure 6 is a block diagram of a second variation of the Gardner algorithm together with a logic diagram illustrating the function of the phase detector logic.

Figure 7 illustrates the use of a Gardner phase detector in a CDR.

Figure 8 shows a received waveform suffering from severe lSl.

Figure 9 shows the received waveform of figure 8 as an eye diagram.

Figure 10 shows a conventional CDR preceded by a high-pass filter equalizer.

Figure 11 is a block diagram of a conventional CDR employed within the processing loop of a data-recovery decision-feedback equalizer (DEE).

Figure 12 is a block diagram of a conventional CDR that estimates phase errors only for selected zero-crossings.

Figure 13 is a block diagram of a conventional CDR that uses the Mueller-Muller algorithm.

Figure 14 illustrates the shape of two symbols (each considered in isolation) received over a binary channel suffering from severe ISI.

Figure 15 illustrates an example waveform received over a channel suffering from severe lSl and its component symbols.

Figure 16 illustrates a positive symbol with the contribution of the symbol to neighbouring phase samples shown.

Figure 17 is a block diagram showing the position of a clock recovery equalizer (GRE) according to the present invention within a receiver.

Figure 18 is a block diagram illustrating clock recovery equalization using weighted recovered data bits.

Figure 19 is a block diagram illustrating clock recovery equalization using a function of recovered data bits.

Figure 20 shows a simulated output from a clock recovery equalizer.

Figure 21 is a block diagram illustrating clock recovery equalization using weighted recovered data bits, including those bits adjacent in the recovered data sequence to the kth phase sample.

Figure 22 is a block diagram illustrating clock recovery equalization using weighted data samples.

Figure 23 is a block diagram illustrating clock recovery equalization using a combination of weighted data samples and recovered data bits.

Figure 24 is a schematic diagram illustrating the position of a CRE with respect to a clock recovery PLL.

Figure 25 is a schematic diagram illustrating the implementation of automatic gain control with a clock recovery PLL.

Figure 26 is a schematic diagram of a receiver configured in accordance with the present invention.

Figure 27 illustrates samples of a received signal.

DETAILED DESCRIPTION OF THE DRAWINGS

The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art.

The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention.

Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. The present invention has general application to receiver systems and provides an improved method for sampling data or recovering symbols from a received data signal. The invention is not limited to binary systems and the term "symbol" is used herein to include all manner of digital representations of signal values known in the art.

The present invention may find application in any system in which it is necessary to recover a clock signal from a time varying signal carrying a data stream and is not limited to systems that recover a clock by means of a PLL. Furthermore, the methods described herein apply equally to the recovery of digital signals and clocked analogue signals.

Embodiments of the invention described herein can address the problem of how to recover a high quality clock signal from a received waveform that suffers from severe ISI. Of course, such embodiments also allow the recovery of high quality clock signals from received waveforms that do not suffer from severe lSl or suffer from ISI to a lesser degree. Conventional clock recovery techniques cannot generate a high quality clock signal from waveforms that suffer from severe ISI.

A waveform received over a linear channel may be expressed as the superposition of receive d symbols. For channels suffering from severe lSl, each received symbol has its energy spread over more than one unit-interval (i.e. clock period). Thus, at any point in time the value of the received waveform is the sum of contributions of several received symbols.

For binary data signals the two types of received symbols are usually of identical shape and differ only in polarity (because the transmitted symbols are identical in shape and differ only in polarity). Figure 14 illustrates the effect of severe ISI on a received symbol of each polarization 141, 143 when considered in isolation. Each symbol was simulated as being transmitted as a square pulse of width one unit.

At the receiver the energy associated with each pulse has been stretched out over several time units (the vertical time division lines 145 are spaced at one unit interval) and there is a long trailing-edge 147 in this example.

A typical data signal comprises a sequence of received symbols, one for each unit interval. In the presence of severe ISI, the energy from multiple symbols overlaps one another such that the received waveform is a superposition of the symbols, as shown in figure 15. The solid lines are the component symbols which contribute to the received waveform 151, shown as a dashed line. The time divisions 153 are spaced one unit interval apart and are shown at the peaks of the individual symbols 155. The time divisions therefore coincide with a properly synchronized clock recovered from the received signal.

Figure 15 also indicates the contributions made by the successive symbols to a phase sample, samplek, taken exactly out-of-phase with the inferred clock signal and between data sample points for symbolk..l,2 and symbo!k+1,2. In a waveform received without any distortion, the position of the phase sample would be a zero-crossing point of the waveform in the case in which the adjacent bits/data are of opposite sign.

The value of a kth phase sample, samplek, may be expressed as: Equation I

P F

samplek = Ck.k -(a +0.5) + [Ck.k -Os -I-Ck,k + ]+ Ck,k + (a + 05) 1=1 i=1 where ck. is the contribution to samplek from the symboI, i.e from the symbol conveying data, and P and F are selected to include all those symbols which make a non-zero contribution at phase sample point k.

The second term (on the right) in Equation 1 is the sum of contributions from the two symbols immediately adjacent to samplek. The first term is the sum of contributions from P symbols preceding those adjacent symbols and the third term is the sum of contributions from F symbols following those adjacent symbols.

Figure 16 illustrates one of the positive symbols shown in figure 15 and its contribution to neighbouring phase samples 161 (marked by solid circles).

For channels that do not suffer from severe ISI, samplek is almost equal to the second term of Equation 1. For channels that do suffer from severe lSl, the first and/or third terms are also significant.

Figures 15 and 16 and the analyses presented herein omit noise contributions.

Noise will, however, be present in actual receivers..

Embodiments of the present invention provide an estimate of the phase error in a clock signal recovered from a received waveform. The phase error estimate may be provided to a clock generator or similar means for producing or controlling the recovered clock signal so as to allow the clock generator or similar means to adjust the recovered clock output to better match the received signal. For example, the received signal or a signal derived from it (e.g. by quantisation of the received signal) may be sampled at the frequency of the recovered clock signal.

In a preferred embodiment of the invention, the Gardner phase detection algorithm (or its variants) is used for clock recovery from a received waveform suffering from severe ISI.

Embodiments of the present invention use signal processing to reduce or eliminate pattern dependency from the phase samples and will be referred to herein as "clock recovery equalization" (CRE). An example of the position of a clock recovery equalizer 171 within a receiver is illustrated schematically in figure 17.

The inputs of a clock recovery equalizer (CRE) include: (i) recovered data 173 (bits in a binary receiver) and/or waveform data samples 175; (ii) phase samples 177 taken between the recovered data/data samples; which the CRE processes so as to form an output value, 179, used for phase error estimation at at least some of the phase sample points.

In a first embodiment of the present invention, the function of a CRE is to cancel the contributions to a phase sample that are due to symbols other than the two symbols immediately adjacent to the phase sample under consideration. The kth output from the CRE, OUtpUtk, corresponding to input samplek may be written: Equation 2

P F

OUtJUtk = -(i + 05) + [C'k.k -0.5+ C'k.k + Ck.k + ( + 05) 1=1 i=1 where C'k.x is the resulting contribution to OUtPUtk from the symboI. When operating in accordance with a first embodiment of the present invention, the CRE output is approximately equal to the second term of equation 2. This is because an estimate of the contributions from the first and third terms of equation 1, represented by signals 181, 183 are cancelled from a phase sample 185, as shown in the example implementations of figures 18 and 19. Furthermore, other than a possible constant gain factor, the second term of equation 2 is approximately equal to the second term of equation 1.

Therefore, OUtpUtk may be expressed: Equation 3 outputk [Ck.k_os+Ck.k+os] The value of OUtPUtk will be approximately zero if: (i) the immediately adjacent two symbols (symboIk and symbo!k+1,) are of opposite sign; and (ii) the sample phase is such that ck,k..O.5 and ck,k+O.5 are of equal magnitude.

This output may be compared to a reference value for use as a measure of phase error whenever symbolk.o.5 and symbolk+o.5 differ. For the binary case, the reference is zero. Using a phase locked loop to control the sampling phase such that OUtPUtk has (average) value of zero when symbolk.5 and symbolk+o.5 differ, then Ck,k0.5 and ck.k+O.5 will have the same magnitudes. Referring to this magnitude as M, the output of the CRE given in equation 3 will be equal to: * 2M when symbo!k and symboIk+., are both positive; * -2M when symboIk and symbolk+',c are both negative; * 0 when symbolk..y. and symbolk+lh are of opposite sign.

As in the example of figure 16, a received symbol is often approximately symmetrical in the region of the peak (although the outlying portions of the symbol may be asymmetrical). This is especially the case for the bandwidth limited channels typical of many channels having severe ISI. Thus, when the contributions to OUtPUtk by the immediately adjacent symbols, ck,k.5 and Ck.k+O.5, have the same magnitude, the timings of the phase and data samples are properly synchronized with the received waveform and the recovered clock signal is generally close to optimum.

Figure 20 shows the simulated output from a clock recovery equalizer on a binary channel suffering from severe ISI (the simulation includes noise). The received symbol shape used in the simulation is shown in figure 16. As the equalizer coefficients are adapted from their initial values the output of the CRE settles into three distinct bands at approximately zero, -0.8 and +0.8 (201, 203 and 205 in figure 20). This agrees with the analysis set out in relation to equation 3 above: the magnitude of the received waveform at the phase sample points shown in figure 16 is approximately 0.4 (the "M" value). The values of the +0.8 and -0.8 bands (i.e. U+/2M) will be referred to herein as the 1outer" values. There will be further bands if multi-level (rather than binary) signalling is used.

A receiver 260 incorporating a clock recovery equalizer in accordance with the present invention is shown in figure 26. A received waveform 262 feeds a data recovery line 263 and a clock recovery line comprising phase sample 264, CRE 261 and clock recovery module 265. The recovered clock 267 is provided to the data recovery line and the phase sampler. The receiver provides data recovered by the data recovery line at 266.

For binary data, a CRE may be implemented as described by equation 4, which is represented schematically in Figure 18.

Equation 4

P F

Outputk 1Vk _(I+os).bitk_(I+05)+W'k.samplek + 147k�(1+O5)bitk+s+o5) i=1 i=1 where, * bltk..(,+o 5) is the recovered bit corresponding to the data samples preceding samplek by (1+0.5) unit intervals. Each bltk..(j+O.5) has value of +1 or -1; * bitk+(!+o.5) is the recovered bit corresponding to the data samples following samplek by (1+0.5) unit intervals. Each bitk+(,+o.5) has value of +1 or -1; * Wkj+o5) and Wk+(j+o.5) are multiplication coefficients. These are adapted according to the received waveform to match the shape of the received symbols; * Wk is a multiplication coefficient.

The multiplication coefficients W, are often (but not always) greater for those bits closer in time to the phase sample, samplek, since these bits typically make a greater contribution to the phase sample. Preferably four bits of the recovered data are fed into the CRE (P = F = 2), but it may be six bits (P = F = 3) or any other number. The number of bits (values) fed into the CRE from the preceding side (in time) of the phase sample may not be equal to the number of bits fed into the CRE from the following side. If the received individual data pulses are highly asymmetrical it can minimise the complexity of the CRE if a greater number of bits are fed into the CRE from the side of a phase sample that is likely to overlap to a greater extent with its neighbouring data bits. These comments apply equally to the embodiments of the present invention in which the bits are data samples or multi-level data.

Figure 18 is a schematic diagram illustrating the operation of a clock recovery equalizer in accordance with the first embodiment of the present invention for which P = 2 and F = 2 in equation 4. The inputs to the CRE are the phase samples 185 of the received waveform together with the values 187 (in this case recovered data bits). The mechanism by which the data bits are recovered from the received waveform is not shown in the figure. Data recovery may be performed in accordance with any of the data recovery techniques known in the art -for example, by equalization or maximum likelihood sequence detection.

The signal processing of a clock recovery equalizer operating in accordance with embodiments of the present invention may be expressed as: Equation 5 OUtPUtk = Wksamp!ek -function(.. Vk..2y3, Vk, Vk+1. Vk+2%.) where each value V may be the value of a data sample or the value of the corresponding recovered data (binary or multi-level). Figure 19 illustrates this schematically in block diagram form for the case in which the values V are recovered bits. The function 191 may be a weighted summation, look-up table, hash function, a function defined in a digital signal processor, or any combination thereof or indeed any means for combining or aggregating the recovered bits so as to yield an estimate of the contribution of those bits at the relevant phase sample point. In the case of a look-up table, for example, the decision bits may make up the look-up address.

In the above examples, which illustrate a first embodiment of the present invention, the two data values immediately adjacent to the phase sample being processed (i.e. Vk and Vk+14) are not involved in the signal processing. In further embodiments of the present invention, any number of samples or any number of items of recovered data may be used by the GRE in forming its phase error estimate. The GRE may use a combination of samples and recovered data. The number of samples and/or recovered data preceding each phase sample may not be equal to the number of samples and/or recovered data following each phase sample.

The signal processing performed by a CRE in accordance with further embodiments of the invention may be expressed: Equation 6 OUtPUtk = WksampIek -function(.. Vk..2, Vk..1, Vk, Vk+, Vk+1y, Vk+2y3..) Equation 6 is similar to Equation 5, but last term is now additionally dependent upon Vkand Vk+.

In embodiments of the present invention, the first and third terms of equation 2 to CRE output, OUtPUtk, are much less significant than the contributions of the first and third terms of equation I to CRE input, samplek. This is because the CRE causes cancellation of an estimate of the contributions of symbols non-adjacent to the phase sample under consideration.

Processing of the recovered data/data samples and the phase sample may be performed at a digital signal processor supporting suitable software, at a set of logic elements specifically configured for the task, or in any analogue or digital circuitry.

The GRE processes the data values (recovered data or samples) and the phase sample so as to generate a phase error estimate. The processing performed by the GRE is defined generally by the function set out in equation 6. The GRE may combine the data values with an envelope so as to scale the contribution from each recovered datum/sample in accordance with the shape of the envelope. The CRE may filter the data values so as to select a predetermined number of values and then, optionally, apply a multiplier to each datum/sample. The parameters or coefficients described herein (W in the case of a linear function, but more generally could be the parameters of any function) are the parameters or coefficients of the function applied by the CRE. Note that the term function is used herein in its most general sense to refer to the set of operations performed on the recovered data/samples.

In a second embodiment of the present invention, a clock recovery equalizer may also include weighted sum contributions from one or both of the data values immediately adjacent to the phase sample under consideration, e.g. bltk.',c and/or bjtk+%. The output of a GRE operating in accordance with the second embodiment could be described by equation 6. An example implementation according to the second embodiment is expressed in Equation 7 for the binary data case and is particularly suitable for recovering a high quality clock from a waveform comprising asymmetric received symbols.

Equation 7 outputk = -+ os.bjt -(i + O.5)+ Wk.samplek + Wk + (i + 0.5) .bitk +(t+O5) i=O i=O Using this GRE, the phase at which samplek equals zero (during data transitions) may be manipulated by adjusting Wk..a5 and Wk+o.5. This provides a means of optimizing the phase of the recovered clock.

A CRE in accordance with this implementation of the second embodiment of the present invention is shown schematically in figure 21. Preferably, an initial estimate of the phase error will be achieved in accordance with the first embodiment of the present invention (i.e. without using the bits or samples 211 immediately adjacent to each phase sample under consideration). Once the GRE coefficients have settled, the second embodiment may be applied as a second step so as to improve the estimate of the phase error.

Auto-adaptation of the coefficients may continue in accordance with the first embodiment, and a second "outer loop" adaptation process may be applied to the two additional inner coefficients of the data values immediately adjacent to the phase sample under consideration. Thus, a small contribution from one or both of the "inner" data values may be included in the processing performed by the CRE and the effect of the change determined by a suitable quality metric such as an eye opening measure or a bit error rate counter. This mechanism permits adaptation of the CRE coefficients corresponding to the inner" data values by monitoring the quality of the recovered data signal or clock. Preferably, this adaptation occurs at a slower rate than the adaptation of the other CRE coefficients in accordance with the first embodiments. This method can provide a high quality clock signal from a received waveform suffering from severe asymmetric ISI (and therefore having symbols suffering from asymmetric distortion).

If Wk% is set equal to Wk+, then (Wk..%bitk + Wk+,bItk+,) will be zero whenever bjtk..i,c and bltk+% are of opposite sign. In other words, only the difference between Wk.1, and Wk+y. affects the steady-state phase of the recovered clock.

A clock recovery equalizer operating in accordance with the present invention may make use of data recovered from a received signal (such as binary data bits) or data samples of a received signal. The latter case is described in equation 8 and a CRE arranged to make use of data samples is shown schematically in figure 22. Note that data samples 221 may be provided by a stage of the receiver prior to data recovery. The signal could be a binary digital, multi-level digital, or clocked analogue signal.

Equation 8

P F

Outputk = Wk -(a + 05) Samplek -(a + 0.5) + Wk samplek + W + + O.5)* samplek + (a + 0.5) i=1 1=1 A combination of data samples 231 and recovered data 232 may be used, as shown in Figure 23. Equation 9 describes this configuration.

Equation 9 outputk= Wk-cI+o.5).bitk-(I+os+Wh.samplek+ Wk+(.+O5).samplek++o5 i=1 i=1 In Equation 9 recovered data is used for samples preceding the phase sample along with data samples that follow. Other arrangements are possible and will be apparent to those skilled in the art.

The figures provided show CRE processing using data samples and/or recovered bits over the range from k-2Y2 to k+2%. This range is given by way of explanatory example -a larger or smaller range may be used. The number of samples/bits preceding the phase sample being processed need not match the number of samples/bits following the phase sample.

In a preferred embodiment of the present invention, the coefficients of the function applied to the recovered data or data samples (such as bit/sample weightings W) are adapted during operation of the receiver. This may be achieved through the use of a zero forcing algorithm. For example, referring to equation 4 and the adaptation of Wk..2 in particular: * If OUtpUtk has the same sign as bItk..2ç more often than it has the opposite sign then Wk..2 is made incrementally smaller (less positive or more negative).

* If OUtpUtk has the same sign as b!tk..2 less often than it has the opposite sign then Wk..2% is made incrementally larger.

Assuming that bItk..2 and OUtPUtk are not correlated, in the steady state OUtPUtk and bItk..2 therefore have the same sign and opposite signs in equal proportion.

In this example, the adaptation processing requires only the sign of the CRE output together with the recovered bit sequence. Two simple counters may be used to measure the frequency of occurrence of (i) OUtPUtk and b!tk.2% having the same sign, and (ii) OUtPUtk and bitk..2y. having the opposite sign. By comparing these, Wk..2y. may be adapted in accordance with the example algorithm.

Any other method of auto-adaptation known in the art, such as the least mean square error algorithm, may be used to adapt the coefficients of the function applied to the recovered data/data samples. Suitable algorithms include those which best match the recovered data sequence/data samples to the phase sample and hence force the CRE output to zero at a zero-crossing (i.e. where consecutive recovered bits have opposite sign). The auto-adaptation algorithm could be applied only in respect of phase samples that the recovered data indicates coincide with a data transition. Alternatively, it could be applied in respect of all phase samples.

In other embodiments, the coefficients of the function applied to the recovered data/data samples may be fixed during data/clock recovery and are not adapted.

For example, the coefficients may be predetermined at the receiver, or may be set during installation or calibration of the receiver for use with a particular data channel.

In a preferred embodiment, the output from a clock recovery equalizer is used for clock recovery in accordance with the Gardner algorithm, or its variants. In the variants described herein, the output of the clock recovery equaliser is used only for phase samples taken at data transitions. The present invention is not limited to using the Gardner algorithm and may be implemented with any other suitable algorithm that could be used to provide an estimate of the phase error between the recovered clock and the received waveform.

Implementations of these variants of the Gardner algorithm in conventional CDRs are described above with reference to figures 5 to 7. By detecting when symbol transitions occur, and comparing phase sample values with ideal values, the variations of the Gardner algorithm may also be applied to clock recovery from multi-level waveforms.

The phase detector output, errork may be updated on the occurrence of data transitions only, with the output being maintained throughout runs of recovered data not having any data transitions. This mechanism helps to eliminate phase detector gain dependency upon the density of data transitions. Alternatively, the output of a CRE of the present invention could be used at or provided to a phase detector only when the recovered data indicates that the phase sample occurs approximately at a data transition.

In a preferred embodiment of the present invention, a phase locked loop (PLL) 241 is used for clock recovery, as shown in Figure 24. The output of the CRE 243 is provided to the phase detector 245 of the PLL. PLLs can acquire phase lock if the VCO frequency is within its "pull-in" frequency range. Initialisation of clock recovery PLLs therefore typically includes a frequency centring step to ensure that this is the case. When coupled with a CRE of the present invention, it may be further advantageous to use edge selective phase locking. This reduces the range of zero-crossing phases whilst the GRE coefficients are adapting, aiding initial phase acquisition.

For a phase detector, the relationship between the input phase error and the output is referred to as the phase detector gain. This is an important parameter as its value determines PLL performance. For a phase detector having gain that scales with the amplitude of its input signal, it is therefore desirable for the input signal to be of a controlled (or known) amplitude.

The magnitudes of "outer" values may be used for gain control, making the phase detector gain approximately independent of the amplitude of the received waveform and also of the channel response (i.e. of the shape of the received symbols). Specifically, the waveform gradient at the phase sampling will be smaller for larger "outer" values, and larger for smaller "outer" values. For example, automatic gain control may be implemented as illustrated in Figure 25: gain controller 251 uses the output of the CRE 253 to control the gain of the phase detector 255.

In order for the CRE to produce a useful phase error estimate output as quickly as possible after turn-on it is preferred that the CRE or receiver stores an initial set of initialisation coefficients. These may be predetermined or could be a set of coefficients previously used by the receiver. Initialization of coefficient values may also be necessary for correct coefficient adaptation.

For high-speed implementations of the present invention (gigabits per second at current technology levels), it is preferred that parallel data paths are used. A person skilled in the art of high speed circuit design will understand that the schematic figures are merely illustrative of the signal processing and do not present the actual implementation of a CRE in hardware.

To assist in understanding the operation of the GRE, another way of regarding the CRE will be described below. It will be understood that the description below is of operations that are functionally equivalent to those described above.

A data signal (whether continuous-time or formed of a sequence of samples) from a linear communications channel may be considered to be the superposition of pulse responses, one per unit interval, and each pulse being identical other than being scaled to an appropriate level. That level may represent a transmitted data value. For binary transmission, the scale factors may be +1 and -1, for the two different data values. The pulse response is dependent on the channel from which the data signal is received. In this sense, we may refer to a pulse response of a signal and the pulse response of a sequence.

When a received signal is being sampled for data recovery it is conventional to sample it at intervals, with each one of those samples being used for recovery of a respective symbol in the signal. If the received signal is additionally sampled at times between those samples then the resulting set of samples may be considered to comprise "data" samples (those used for data recovery) and "phase" samples that are interleaved with the data samples. When the samples in the region of a particular pulse response are considered, they may be viewed as a set including interleaved phase and data samples, with one central data sample -known as the "cursor" sample -that will normally be close to the peak of the particular continuous-time pulse response.

For all practical communication channels the two phase samples that lie immediately before and immediately after the cursor sample will be expected typically to have non-zero values. Those two phase samples are referred to herein as the "central" samples. Further phase samples may also have non-zero values.

Figure 27 gives an example of this situation. In the figure the curve represents the continuous-time pulse response of a received signal (determined by the channel response). The squares show the data samples, with the "cursor" sample indicated. The circles show the phase sample, with the "central" samples indicated.

The CRE receives the set of data and phase samples that represents a particular pulse response, and outputs a modified version of those samples. The modification is dependent on the data samples and/or recovered data. Based on that information the CRE can determine how to modify the phase samples of the set that represents the received waveform. The modification is performed with the objective that, compared to the pulse response of the received signal, the pulse response that is output from the CRE has reduced magnitudes of phase samples other than the "central" phase samples, whilst substantially retaining the magnitudes of the central phase samples.

In Figure 27, the crosses show the samples making up the pulse response of the CRE output sequence.

As indicated above, the CRE output sequence may be used for clock recovery.

One example of how this may be done is by using one of the variants of the Gardner algorithm for phase detection. An advantage of using the output of the CRE for clock recovery is that the CRE can reduce or even eliminate the extentd to which the output of the phase detector is dependent on the data that is received.

The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being camed out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the forego ing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

Claims

1. A method for recovering a clock from a received data signal, the method comprising: receiving a data signal carrying a series of symbols; generating a clock signal in dependence on the data signal: sampling the received data signal at the frequency of the clock signal so as to form a sequence of values dependent on the sampled level of the received data signal, the sequence including first and second values that are adjacent in the sequence; sampling the signal at a further sample time between the times of the first and second samples to form a further value; forming a phase error indicator by estimating the difference between the further value and a representation of the contributions of the symbols indicated by at least some of the values of the sequence to the signal at the further sample time; and adjusting the phase of the clock signal in dependence on the phase error indicator.

2. A method as claimed in claim 1, wherein the representation is a weighted aggregate of the at least some of the sequence of values.

3. A method as claimed in claim 2, wherein the weighted aggregate does not include contributions from the first and second values.

4. A method as claimed in claim 2, wherein the weights applied to the first and second values are less than the weights applied to one or more other values of the sequence.

5. A method as claimed in claim 4, wherein the said one or more other values of the sequence includes all those values within a first predetermined number of values preceding the first and second values and a second predetermined number of values following the first and second values.

6. A method as claimed in claim 5, wherein the first and second predetermined number of values are equal.

7. A method as claimed in any of claims 2 to 6, wherein the weight applied to a value of the one or more other values of the sequence depends upon the position of that value in the sequence relative to the position of the first and second values of the sequence.

8. A method as claimed in claim 7, wherein the weights are greater for values at positions in the sequence closer to the first and second values of the sequence.

9. A method as claimed in any of claims 5 to 8, wherein the weights applied to the first and second values are less than the greatest weight applied to any of the one or more other values of the sequence.

10. A method as claimed in any of claims 4 to 9, wherein the weights applied to the first and second values are zero.

11. A method as claimed in any of claims 2 to 10, wherein the weights applied to values of the sequence are adapted in dependence on the phase error indicator.

12. A method as claimed in claim 11, wherein the adaptation is performed in accordance with a zero-forcing adaptation algorithm.

13. A method as claimed in claim 11 or 12, wherein adaptation is performed in accordance with a minimum mean square error adaptation algorithm.

14. A method as claimed in any of claims 11 to 13 as dependent on claim 2, wherein the weights applied to the first and second values are adapted in dependence upon a quality metric of the sequence of values.

15. A method as claimed in claim 14, wherein the quality metric is an eye opening measure or a bit error rate counter.

16. A method as claimed in any of claims 2 to 10, wherein the weights applied to the values of the sequence are predetermined weights.

17. A method as claimed in claim 1, wherein the representation is determined by a look-up function using the combined samples of the sequence of samples as a lookup key.

18. A method as claimed in claim 17, wherein the representation determined by the look-up function is equal to a representation determined as specified in any of claims 2 to 16.

19. A method as claimed in any preceding claim, wherein the representation is formed by combining values of the sequence in such a way that the representation is insensitive to the first and second values.

20. A method as claimed in any preceding claim, wherein the representation is formed by combining values of the sequence in such a way that the individual contributions of the first and second values to the representation are less than the contributions of one or more other values of the sequence.

21. A method as claimed in any preceding claim, wherein the representation is formed by combining values of the sequence in such a way that the individual contributions of the first and second values to the representation have a lower significance than those of one or more other values of the sequence.

22. A method as claimed in claim 20 or 21, wherein the individual contributions of the values of the sequence to the representation are average contributions over a predetermined number of clock cycles.

23. A method as claimed in any of claims 20 to 22, wherein the number of non-zero contributions to the representation from the values following the first and second values in the sequence is not equal to the number of non-zero contributions to the representation of the received data signal from the values preceding the first and second values in the sequence.

24. A method as claimed in any of claims 20 to 22, wherein the only non-zero contributions to the representation are from the three values following the first and second values in the sequence and from the one value preceding the first and second values in the sequence.

25. A method as claimed in any of claims 20 to 22, wherein the individual contributions of the first and second values to the representation are zero.

26. A method as claimed in any preceding claim, wherein the step of adjusting the phase of the clock signal is further performed in dependence on the symbols indicated by the first and second values of the sequence.

27. A method as claimed in claim 26, wherein the phase error indicator and the symbols indicated by the first and second values of the sequence are combined in accordance with a Gardner algorithm.

28. A method as claimed in any preceding claim, wherein the step of sampling the received data signal is performed in-phase with the generated clock signal.

29. A method as claimed in any preceding claim, wherein the step of sampling the signal at a further sample time is performed out-of-phase with the generated clock signal.

30. A method as claimed in any preceding claim, wherein the representation is formed by combining values of the sequence in accordance with a predetermined function.

31. A method as claimed in any preceding claim, wherein the phase error indicator is determined in a manner such that it is substantially independent of the values of the sequence other than the first and second data values.

32. A method as claimed in claim 31 as dependent on claim 11, wherein the weights are adapted using an adaptation algorithm such that the phase error indicator is substantially independent of the one or more other values of the sequence.

33. A method as claimed in any preceding claim, wherein the step of adjusting the phase of the clock signal in dependence on at least the phase error indicator is performed only if the symbots indicated by the first and second values together represent a data transition.

34. A method as claimed in any preceding claim, wherein the symbols are binary symbols.

35. A method as claimed in any of claims I to 33 wherein the symbols are multi-level symbols.

36. A receiver arranged to perform a method as claimed in any preceding claim.

37. A receiver for recovering a clock from a received data signal, the receiver comprising: an input for receiving a data signal carrying a series of symbols; a clock signal generator for generating a clock signal in dependence on the data signal; sampling means for sampling the received data signal at the frequency of the clock signal so as to form a sequence of values dependent on the sampled level of the received data signal, the sequence including first and second values that are adjacent in the sequence, and for sampling the signal at a further sample time between the times of the first and second samples to form a further value; means for forming a phase error indicator by estimating the difference between the further value and a representation of the contributions of the symbols indicated by at least some of the values of the sequence to the signal at the further sample time; and means for adjusting the phase of the clock signal in dependence on the phase error indicator.

38. A receiver as claimed in claim 36 or 37, wherein the receiver is further arranged to recover the series of symbols from the data signal.

39. A method for recovering a clock from a received data signal, the method comprising: receiving a data signal representing a data sequence; sampling the data signal at the frequency of a local clock signal so as to form a first sequence of values dependent on sampled levels of the received data signal; sampling the data signal at the frequency of the local clock signal and between the samples of the first sequence, so as to form a second sequence of values dependent on sampled levels of the received data signal; the thus sampled data signal having a sampled pulse response composed of interleaved samples corresponding in phase to the first and second sequences, the cursor sample of those samples corresponding in phase to the first sequence and the two samples adjacent to the cursor sample, which correspond in phase to the second sequence, being referred to herein as the central samples; applying a filter to the second sequence to form an output sequence of samples that corresponds to the second sequence, represents the said data sequence and has a pulse response, referred to herein as the output response, with the following properties, in comparison to the pulse response of the received data signal, referred to herein as the input response: i) the samples of the output response corresponding to the two central samples of the input response are substantially unchanged in value relative to each other; and ii) the magnitudes of the samples of the output response corresponding to one or more of the other samples of the input response are reduced such that their energy is small relative to the energy of the samples of the output response corresponding to the two central samples of the input response; and adjusting the phase of the local clock signal in dependence on the output sequence.

40. A method as claimed in claim 39, comprising adapting the filter in dependence upon the data signal such that the properties (i) and (ii) are satisfied.

41. A method as claimed in claim 40, wherein the step of adapting the filter is performed whilst the data signal is being received so as to satisfy the said properties (I) and (ii) whilst reception is in progress.

42. A method as claimed in any of claims 39 to 41, wherein the filter is such as to make use of samples of the first sequence to compute the values of the output sequence.

43. A method as claimed in any of claims 39 to 42, wherein the filter is such as to make use of recovered values of data represented by the said received data signal to compute the values of the output sequence.

44. A method as claimed in any of claims 39 to 43, wherein the phase of the local clock signal is adjusted in accordance with a Gardner algorithm.

45. A method as claimed in any of claims 39 to 44, wherein the method comprises forming each sample of the output sequence from the filter as an estimate of the difference between a sampled value in the second sequence and a representation of the contributions to said sampled value of symbols, representing data in the said data sequence, indicated by at least some of the values of the first sequence.

46. A method as claimed in any of claims 39 to 45, wherein the received data signal comprises the summation of symbols representing said data sequence, and the method comprises, for at least some of those symbols, recovering a representation of the respective symbol from the received data signal using the said cursor sample as a cursor sample for that recovery step.

47. A method as claimed in any of claims 39 to 46, wherein each member of the said data sequence has one of two values.

48. A method as claimed in any of claims 39 to 46, wherein each member of the said data sequence has one of three or more values.

49. A receiver substantially as described herein and shown in any of figures 17 to 19 and 21 to 26.