GB0802303D0 - Clock recovery - Google Patents

Clock recovery

Info

Publication number
GB0802303D0
GB0802303D0 GBGB0802303.8A GB0802303A GB0802303D0 GB 0802303 D0 GB0802303 D0 GB 0802303D0 GB 0802303 A GB0802303 A GB 0802303A GB 0802303 D0 GB0802303 D0 GB 0802303D0
Authority
GB
United Kingdom
Prior art keywords
clock recovery
clock
recovery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB0802303.8A
Other versions
GB2453185A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xintronix Ltd
Original Assignee
Xintronix Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xintronix Ltd filed Critical Xintronix Ltd
Publication of GB0802303D0 publication Critical patent/GB0802303D0/en
Priority to PCT/EP2008/062756 priority Critical patent/WO2009040371A1/en
Priority to TW097136859A priority patent/TW200922252A/en
Publication of GB2453185A publication Critical patent/GB2453185A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
GB0802303A 2007-09-26 2008-02-07 Clock recovery in a sampled received signal including removal of ISI effects from data samples used to detect zero-crossing Withdrawn GB2453185A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/EP2008/062756 WO2009040371A1 (en) 2007-09-26 2008-09-24 Clock recovery using a tapped delay line
TW097136859A TW200922252A (en) 2007-09-26 2008-09-25 Clock recovery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB0718831.1A GB0718831D0 (en) 2007-09-26 2007-09-26 Clock recovery

Publications (2)

Publication Number Publication Date
GB0802303D0 true GB0802303D0 (en) 2008-03-12
GB2453185A GB2453185A (en) 2009-04-01

Family

ID=38701725

Family Applications (2)

Application Number Title Priority Date Filing Date
GBGB0718831.1A Ceased GB0718831D0 (en) 2007-09-26 2007-09-26 Clock recovery
GB0802303A Withdrawn GB2453185A (en) 2007-09-26 2008-02-07 Clock recovery in a sampled received signal including removal of ISI effects from data samples used to detect zero-crossing

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GBGB0718831.1A Ceased GB0718831D0 (en) 2007-09-26 2007-09-26 Clock recovery

Country Status (3)

Country Link
GB (2) GB0718831D0 (en)
TW (1) TW200922252A (en)
WO (1) WO2009040371A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101926121A (en) * 2008-02-01 2010-12-22 拉姆伯斯公司 Receiver with enhanced clock and data recovery
CN101610083B (en) * 2009-06-19 2012-10-10 中兴通讯股份有限公司 High-speed multi-channel clock data recovery circuit
JP5936926B2 (en) * 2012-06-07 2016-06-22 ルネサスエレクトロニクス株式会社 Reception circuit, clock recovery circuit, and communication system
US9130735B2 (en) 2013-07-22 2015-09-08 Qualcomm Incorporated Multi-phase clock generation method
US10491367B2 (en) 2018-02-17 2019-11-26 Synopsys, Inc. Clock and data recovery (CDR) circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5581585A (en) * 1994-10-21 1996-12-03 Level One Communications, Inc. Phase-locked loop timing recovery circuit
TW329493B (en) * 1997-06-18 1998-04-11 Winbond Electronics Corp Data processing device
US6414990B1 (en) * 1998-09-29 2002-07-02 Conexant Systems, Inc. Timing recovery for a high speed digital data communication system based on adaptive equalizer impulse response characteristics
US6986080B2 (en) * 2002-05-21 2006-01-10 Zenith Electronics Corporation Timing error detector for digital signal receiver
GB2397980B (en) * 2003-01-28 2005-11-23 Phyworks Ltd Receiver
KR101019481B1 (en) * 2004-08-16 2011-03-07 엘지전자 주식회사 Apparatus of timing recovery system and Recovering method of the same
US7817712B2 (en) * 2006-05-30 2010-10-19 Fujitsu Limited System and method for independently adjusting multiple compensations applied to a signal

Also Published As

Publication number Publication date
GB0718831D0 (en) 2007-11-07
GB2453185A (en) 2009-04-01
TW200922252A (en) 2009-05-16
WO2009040371A1 (en) 2009-04-02

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)