KR102032370B1 - Data recovery circuit and adaptive equalizer coefficients methods the same - Google Patents
Data recovery circuit and adaptive equalizer coefficients methods the same Download PDFInfo
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- KR102032370B1 KR102032370B1 KR1020120070337A KR20120070337A KR102032370B1 KR 102032370 B1 KR102032370 B1 KR 102032370B1 KR 1020120070337 A KR1020120070337 A KR 1020120070337A KR 20120070337 A KR20120070337 A KR 20120070337A KR 102032370 B1 KR102032370 B1 KR 102032370B1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03248—Arrangements for operating in conjunction with other apparatus
- H04L25/03254—Operation with other circuitry for removing intersymbol interference
- H04L25/03267—Operation with other circuitry for removing intersymbol interference with decision feedback equalisers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
- H04L25/063—Setting decision thresholds using feedback techniques only
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03445—Time domain
- H04L2025/03471—Tapped delay lines
- H04L2025/03484—Tapped delay lines time-recursive
- H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
Abstract
A plurality of sampling signals are generated by over-sampling a receiver input signal in response to a plurality of clock signals that are sequentially delayed in phase, and output a plurality of pre recovery signals adjusted according to a DFE control signal in response to the plurality of sampling signals. An over-sampling receiver; A data recovery unit generating a plurality of transition detection signals by the plurality of clock signals based on the plurality of prerecovery signals, and outputting a lowest data transition signal and a highest data transition signal based on the plurality of transition detection signals; And a data recovery circuit including a DFE controller for outputting the DFE control signal by using any one or more of the lowest data transition signal and the highest data transition signal, and an adaptive equalization coefficient adjusting method using the same.
Description
The present invention relates to a data recovery circuit and an adaptive equalization coefficient adjusting method using the same.
The frequency spectrum of a signal generally degrades as it passes through a transmission medium such as a cable. This degradation of quality usually results in attenuation of high frequency components in the frequency spectrum of the signal. As a result of this degradation in quality, since narrow signal pulses have lower peak amplitudes than wide signal pulses, it is difficult to recover the bit information encoded in each pulse. In addition, the signal flowing into the receiver through the transmission medium may include jitter. Signals containing jitter also have difficulty recovering. Signal processing called equalization is performed to compensate for frequency degradation of the frequency. Equalization refers to a technique that reduces jitter in incoming signals and returns attenuated frequency components to near full amplitude.
In transceivers, which are commonly used in high-speed serial interfaces, serial data speeds are gradually increasing to more than a few Gbps. As such, as the transmission speed of data increases, jitter noise of the receiver becomes a major factor in recovering data without error in a data recovery block of the receiver. If long cable or PCB routing is the primary medium, add equalizers to the receiver to reduce inter-symbol-interference (ISI).
It is an object of the present invention to provide a data recovery circuit.
An object of the present invention is to provide a data recovery circuit and an adaptive equalization coefficient adjusting method using the same.
The problem to be solved by the present invention is not limited to the above-mentioned problem, another task that is not mentioned will be clearly understood by those skilled in the art from the following description.
According to an embodiment of the inventive concept, the data recovery circuit generates a plurality of sampling signals by over-sampling a receiver input signal in response to a plurality of clock signals that are sequentially delayed, and responds to the plurality of sampling signals. An over-sampling receiver for outputting a plurality of pre recovery signals adjusted according to the DFE control signal; A data recovery unit generating a plurality of transition detection signals by the plurality of clock signals based on the plurality of prerecovery signals, and outputting a lowest data transition signal and a highest data transition signal based on the plurality of transition detection signals; And a DFE controller configured to output the DFE control signal by using any one or more of the lowest data transition signal and the highest data transition signal.
The transition detection signal may include the position of the data transition and the number of data transitions occurring in the sampling interval between the sampling time points of two adjacent clock signals during the data transition detection period.
The lowest data transition signal may include information about the position of the data transition and the number of data transitions having the least occurrence of the data transition occurring between the sampling intervals on average.
The highest data transition signal may include information about the position of the data transition in which the occurrence of the data transition occurring between the sampling intervals is on average and the number of the data transitions.
And a plurality of unit over-sampling receivers respectively corresponding to the plurality of clock signals, wherein the unit over-sampling receiver outputs the plurality of sampling signals by sampling the receiver input signal in response to the plurality of clock signals. An over-sampler portion; A DFE unit for equalizing the sampling signal according to an equalization coefficient adjusted by the DFE control signal in response to a feedback pre-recovery signal and outputting an equalizing signal; And a latch unit configured to output the plurality of prerecovery signals in response to the equalizing signal.
The DFE unit may include an equalization coefficient adjusting unit for adjusting the equalization coefficient according to the DFE control signal.
The equalization coefficient may represent a voltage drop rate of the voltage level of the sampling signal.
The data recovery unit may select any one of the plurality of prerecovery signals in response to the highest data transition signal and output the recovered signal.
The data recovery unit may include: a data transition detector configured to receive the plurality of clock signals and the plurality of prerecovery signals and detect and output the plurality of transition detection signals; A data transition comparator configured to output the lowest data transition signal and the highest data transition signal based on the plurality of transition detection signals; And a data selector configured to select any one of the plurality of prerecovery signals output from the unit oversampling receiver in response to the highest data transition signal and to output the recovered data.
The DFE controller may include: a DFE controller which receives the lowest data transition signal or the highest data transition signal and outputs an increase control signal and a decrease control signal for increasing or decreasing the control code by 1; And a counter unit configured to receive the increase control signal and the decrease control signal and output the DFE control signal.
The DFE adjustment unit may compare the first highest data transition signal in the first data transition detection period with the second highest data transition signal in the second data transition detection period to compare the highest data transition included in the first highest data transition signal. If the position and the number of the highest data transitions are changed, the increment control signal is output, and the first lowest data transition signal in the first data transition detection period and the second lowest data transition signal in the second data transition detection period are output. In comparison, when the number of the lowest data transitions included in the first lowest data transition signal decreases, the first data transition detection period is performed in the same direction as the change direction of the second control code with respect to the second data transition detection period. For changing the first control code Outputting the increase control signal or the decrease control signal and detecting the first data transition in a direction opposite to a change direction of the second control code with respect to the second data transition detection period when the number of the lowest data transitions is increased; The increase control signal or the decrease control signal for changing the first control code for a period may be output.
The DFE controller may adjust the first control code by using the lowest data transition signal when the highest data transition signal maintains the same highest sampling interval for a predetermined time.
A sampling signal is generated by receiving a clock signal and a receiver input signal, and an equalizing signal generated in response to the sampling signal and the DFE control signal is latched and output as a pre-recovery signal, wherein the pre-recovery signal is fed back. ; A data recovery unit configured to receive the clock signal and the pre-recovery signal and output recovered data, a lowest data transition signal, and a highest data transition signal; And a DFE controller configured to generate the DFE control signal in a first mode using the lowest data transition signal and to generate the DFE control signal in a second mode using the highest data transition signal. have.
In the first mode, the equalization coefficient may be increased until the first condition is satisfied, and in the second mode, the equalization coefficient may be increased or decreased according to the second condition after the first condition is satisfied. have.
The first condition may be a position of a sampling interval for the highest data transition signal for a predetermined time, and the second condition may be an increase or decrease in the number of data transitions for the lowest data transition signal.
Specific details of other embodiments are included in the detailed description and the drawings.
According to various embodiments of the inventive concept, a data recovery circuit and an adaptive equalization coefficient adjusting method using the same may effectively remove inter-symbol-interference (ISI) using over-sampling and an equalizer. In other words, by quickly reacting to noise or a change in the state of a channel, ISI can be effectively removed.
1 is a block diagram illustrating a data recovery circuit in an embodiment of the inventive concept.
FIG. 2 is a block diagram illustrating a configuration of an over-sampling receiver included in the data recovery circuit shown in FIG. 1.
FIG. 3 is a detailed circuit diagram of an embodiment of a unit over-sampling receiver of the over-sampling receiver shown in FIG. 2.
4 is a detailed circuit diagram illustrating an embodiment of a configuration of an equalization coefficient adjusting unit shown in FIG. 3.
FIG. 5 is a block diagram illustrating a configuration of a data recovery unit included in the data recovery circuit shown in FIG. 1.
6 is a timing diagram illustrating an adaptive equalization coefficient adjusting method using a data recovery circuit according to the inventive concept.
FIG. 7 is a block diagram illustrating a configuration of a DFE controller included in the data recovery circuit shown in FIG. 1.
8 is a flowchart illustrating a method for adjusting an adaptive equalization coefficient using a data recovery circuit according to the inventive concept.
The construction of the invention by the technical idea of the present invention and the objects to be achieved through them will be apparent from the embodiments and drawings described below. Embodiments described in the specification of the present invention are provided to enable those skilled in the art to easily convey and implement the technical idea. Therefore, the technical idea of the present invention may be modified in various forms without being limited to the embodiments described below. Shapes and sizes of the regions indicated in the drawings attached to the specification of the present invention are merely illustrated to facilitate understanding of the present invention and may be exaggerated for convenience. Thus, the regions illustrated in the figures have schematic attributes and do not limit the scope of the invention. The symbols in the specification of the present invention refer to the same components. Accordingly, the same or similar reference numerals may be described with reference to other drawings, even if not mentioned or described in the corresponding drawings. Also, although reference numerals are not indicated, they may be described with reference to other drawings.
1 is a block diagram illustrating a
Referring to FIG. 1, the
The over-sampling
The over-sampling
At this time, the DFE control signal CON_A may adjust the equalization coefficient to output the optimal recovered data REC_D.
The
The
FIG. 2 is a block diagram showing the configuration of the
Referring to FIG. 2, the
The
The
The
FIG. 3 is a detailed circuit diagram of one embodiment of the
Referring to FIG. 3, the
In detail, the
The
The equalization
Referring to FIG. 4, the DFE control signal CON_A may be a 4-bit control code having first to fourth control codes CD1 to CD4.
The equalization
The size ratio between the first to fourth coefficient determination transistors M5 to M8 may be set to 8: 4: 2: 1 when the size of the fourth coefficient determination transistor M8 is one.
The current passing ratio of the first to fourth coefficient determination transistors M5 to M8 may be proportional to the size ratio of the first to fourth coefficient determination transistors M5 to M8. That is, the larger the size of the first to fourth coefficient determination transistors M5 to M8, the greater the current passing rate.
For example, when '0, 1, 0, 0' is input to the first to fourth control codes CD1 to CD4, the first control code CD1 is 0 and the second control code CD2 is 1. The third control code CD3 may be zero, and the fourth control code CD4 may be zero. Since only the second control transistor M2 is turned on according to the first to fourth control codes CD1 to CD4 of '0100', the second control transistor M2 and the second coefficient determining transistor M6 may be formed only through the paths of the second control transistor M2. A current that drops the voltage level of one sampling signal SA_S <1> and / SA <1> may flow.
In addition, when '0, 1, 0, 1' is input to the first to fourth control codes CD1 to CD4, the first control code CD1 is 0 and the second control code CD2 is 1, first. 3 The control code CD3 may be 0, and the fourth control code CD4 may be 1. Since only the second control transistor M2 and the fourth control transistor M4 are turned on according to the first to fourth control codes CD1 to CD4 of '0101', the second control transistor M2 and the second coefficient determination transistor are turned on. The voltage level of the first sampling signals SA_S <1> and / SA <1> is lowered only through the path through M6 and the paths of the fourth control transistor M4 and the fourth coefficient determination transistor M8. Current can flow.
The voltage drop adjusted by the case where 0101 is input to the first to fourth control codes CD1 to CD4 is inputted with '0, 1, 0, 0' to the first to fourth control codes CD1 to CD4. Since the voltage drop is larger than the voltage drop adjusted by the case, the speed of the voltage drop of the first sampling signals SA_S <1> and / SA <1> may be increased.
In summary, as the values of the first to fourth control codes CD1 to CD4 increase, the speed at which the first sampling signals SA_S <1> and / SA <1> drop down may increase. That is, the equalization coefficients for the first sampling signals SA_S <1> and / SA <1> may be increased.
The
FIG. 5 is a block diagram showing the configuration of the
Referring to FIG. 5, the
The
Referring to FIG. 6, in the case of 3-over-sampling, the first to third transition detection signals FLG <1: 3> may include first to third clock signals CLK <1: 3>. It may include information about the data transition generated during the data transition detection period (T -2 -T n ) in the third sampling interval (P 1 ~ P 3 ). That is, the first transition detection signal FLG <1> includes the position and the number of data transitions generated during each data transition detection period T -2 -T n at the first sampling interval P 1 , The second transition detection signal FLG <2> includes the position and the number of data transitions generated during each data transition detection period T -2 -T n at the second sampling interval P 2 , and the third The transition detection signal FLG <3> may include the position and the number of data transitions generated during each data transition detection period T −2 -T n in the third sampling interval P 3 . In this case, the data transition detection period (T -n -T n ) is set to have a period of three clocks, respectively, but is not limited thereto, and may have a period of two clocks or a period of three clocks or more.
Between the first sampling interval (P 1) is the first clock signal (CLK <1>) of the first sampling time point (S 1) and the second clock signal (CLK <2>) a second sampling time point (S 2) of a between a second sampling interval (P 2) is the second clock signal (CLK <2>) a second sampling time point (S 2) and the third clock signal (CLK <3>) a third sampling point (S 3) of the and, the third sampling interval (P 3) is the third clock signal (CLK <3>) 3 the first sampling time point (S 1) of the sampling time (S 3) and the first clock signal (CLK <1>) of May be between. In this case, each of the first to third clock signals CLK <1: 3> may be delayed by an A interval and input.
The data
The lowest data transition signal OUT_CL has an average data transition among information on the number of data transitions occurring in the first to nth sampling intervals P 1 to P n during the data transition detection period T −n −T n . It may include information about the location of the first to n-th sampling interval (P 1 ~ P n ) and the number of data transitions that occur least. The highest data transition signal OUT_CH has an average data transition among information on the number of data transitions occurring in the first to nth sampling intervals P 1 to P n during the data transition detection period T -n -T n . It may include information about the position of the first to n-th sampling interval (P 1 ~ P n ) and the number of data transitions that occur most frequently.
The
FIG. 7 is a block diagram illustrating a configuration of the
Referring to FIG. 7, the
The
The increment control signal CI_S is included in the highest data transition signal OUT_CH between the current data transition detection period T 0 and the previous data transition detection period T -1 in the coarse control code setting mode, respectively. the first to n-th sampling interval (P 1 ~ P n) when the number of the position and the data transition of the first to n-th sampling interval (P 1 ~ P n) by comparing the number of positions and the data transition, fluctuation of the , And compare the number of data transitions included in the lowest data transition signal OUT_CL in the previous data transition detection period T -1 with the current data transition detection period T 0 in the optimal control code setting mode, respectively. When the number of data transitions is changed, the values of the first to fourth control codes CD1 to CD4 may be increased by one.
The decrement control signal CD_S corresponds to the data transition signal included in the lowest data transition signal OUT_CL in the current data transition detection period T 0 and the previous data transition detection period T −1 in the optimum control code setting mode. When the number of data transitions is changed by comparing the numbers, the values of the first to fourth control codes CD1 to CD4 may be decreased by one.
The
8 is a flowchart illustrating an adaptive equalization coefficient adjusting method using the
Referring to FIG. 8, the
Next, when performing the rough control code setting mode for setting the rough control code, the
Referring to FIG. 6, the
Meanwhile, the first to third signals included in the highest data transition signal OUT_CH detected in the previous data transition detection period T -1 and the highest data transition signal OUT_CH detected in the current data transition detection period T 0 . When there is no change in the position of the sampling intervals P 1 to P 3 and the number of data transitions, the first to third sampling intervals (DFE) included in the highest data transition signal OUT_CH for a predetermined period ( It may be determined whether the positions of P 1 to P 3 are maintained (S10).
If the positions of the first to third sampling intervals P 1 to P 3 included in the highest data transition signal OUT_CH are not maintained for a predetermined period, the
On the other hand, when the positions of the first to third sampling intervals P 1 to P 3 included in the highest data transition signal OUT_CH are maintained for a predetermined period, the
Next, when the
Referring to FIG. 6, the
Meanwhile, the lowest data transition signal OUT_CH has the number of one data transition in the third sampling interval P 3 of the previous data transition detection period T −1 , and the first data transition signal OUT_CH has the number of one data transition of the current data transition detection period T 0 . In the case of having the number of two data transitions in three sampling intervals P 3 (S18), the
The
For example, if the first to fourth control codes CD1 to CD4 are increased in the previous data transition detection period T -1 , the
On the other hand, when the number of data transitions included in the lowest data transition signal OUT_CH increases, the
For example, referring to FIG. 6, the lowest data transition signal OUT_CH is the number of two data transitions and the current data transition detection in the third sampling interval P 3 of the previous data transition detection period T −1 . When the number of three data transitions is included in the third sampling interval P 3 of the period T 0 , the
While the embodiments of the present invention have been schematically described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. I can understand that you can. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.
1: data recovery circuit
10: over-sampling receiver 12: over-sampler part
14: DFE section 16: latch section
1410: equalization coefficient control unit
20: data recovery unit
22: data transition detection unit 24: data comparison unit
26: data selector
30: DFE control unit
32: DFE control section 34: selection section
Claims (10)
A data recovery unit generating a plurality of transition detection signals by the plurality of clock signals based on the plurality of prerecovery signals, and outputting a lowest data transition signal and a highest data transition signal based on the plurality of transition detection signals; And
And a DFE controller configured to output the DFE control signal by using any one or more of the lowest data transition signal and the highest data transition signal.
The lowest data transition signal includes information on the position of the data transition and the number of the data transitions having the lowest average occurrence of the data transition occurring between sampling intervals using the transition detection signal. The data transition signal includes information on the position of the data transition and the number of data transitions having the largest average occurrence of the data transition occurring between the sampling intervals using the transition detection signal.
And the transition detection signal includes a position of the data transition and the number of data transitions occurring at a sampling interval between sampling points by two adjacent clock signals during a data transition detection period.
A plurality of unit over-sampling receivers respectively corresponding to the plurality of clock signals;
The unit over-sampling receiver,
An over-sampler unit configured to output the plurality of sampling signals by sampling the receiver input signal in response to the plurality of clock signals;
A DFE unit for equalizing the sampling signal according to an equalization coefficient adjusted by the DFE control signal in response to a feedback pre-recovery signal and outputting an equalizing signal; And
And a latch unit configured to output the plurality of pre-recovery signals in response to the equalizing signal.
The DFE unit,
And an equalization coefficient adjusting unit for adjusting the equalization coefficient according to the DFE control signal.
The data recovery unit,
A data transition detector which receives the plurality of clock signals and the plurality of prerecovery signals and detects and outputs the plurality of transition detection signals;
A data transition comparator configured to output the lowest data transition signal and the highest data transition signal based on the plurality of transition detection signals; And
And a data selector configured to select one of the plurality of prerecovery signals output from the unit over-sampling receiver in response to the highest data transition signal and to output the recovered data as the recovered data.
The DFE control unit,
A DFE controller which receives the lowest data transition signal or the highest data transition signal and outputs an increase control signal and a decrease control signal for increasing or decreasing the control code by 1; And
And a counter unit configured to receive the increase control signal and the decrease control signal and output the DFE control signal.
The DFE control unit,
The position and the maximum data of the highest data transition included in the first highest data transition signal by comparing the first highest data transition signal in the first data transition detection period and the second highest data transition signal in the second data transition detection period. When the number of transitions is changed, the increase control signal is outputted.
When the number of lowest data transitions included in the first lowest data transition signal decreases by comparing the first lowest data transition signal in the first data transition detection period and the second lowest data transition signal in the second data transition detection period. Outputs the increase control signal or the decrease control signal for changing the first control code for the first data transition detection period in the same direction as the change direction of the second control code for the second data transition detection period; And when the number of the lowest data transitions is increased, changing the first control code for the first data transition detection period in a direction opposite to the change direction of the second control code for the second data transition detection period. The increase control signal or the decrease control signal Output data recovery circuit.
The DFE control unit,
If the highest data transition signal maintains the same sampling interval for a predetermined time,
And a data recovery circuit for adjusting the first control code using the lowest data transition signal.
A data recovery unit configured to receive the clock signal and the pre-recovery signal and output recovered data, a lowest data transition signal, and a highest data transition signal; And
And a DFE controller for generating the DFE control signal in a first mode using the lowest data transition signal and generating the DFE control signal in a second mode using the highest data transition signal.
In the first mode, the equalization coefficient is increased until the first condition is satisfied,
In the second mode, after the first condition is satisfied, the equalization coefficient is increased or decreased according to the second condition,
The first condition is that the position of the sampling interval for the highest data transition signal is maintained for a predetermined time,
The second condition is that the number of data transitions for the lowest data transition signal is increased or decreased.
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KR1020120029572A KR20130043559A (en) | 2011-10-20 | 2012-03-22 | Equalizer, receiver circuit having the same and equalizer method |
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KR102599059B1 (en) | 2018-10-11 | 2023-11-08 | 삼성디스플레이 주식회사 | Transition detector and clock data recovery unit including the same |
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US20040032905A1 (en) | 2002-08-19 | 2004-02-19 | Andreas Dittrich | Receiver for high rate digital communication system |
JP2009225018A (en) | 2008-03-14 | 2009-10-01 | Nec Corp | Decision feedback equalization apparatus and method |
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KR20070017354A (en) * | 2004-04-09 | 2007-02-09 | 마이크로나스 세미컨덕터, 인코포레이티드 | Advanced digital receiver |
KR100965767B1 (en) * | 2008-09-08 | 2010-06-24 | 주식회사 하이닉스반도체 | Decision feedback equalizer having a clock recovery circuit and method thereof |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040032905A1 (en) | 2002-08-19 | 2004-02-19 | Andreas Dittrich | Receiver for high rate digital communication system |
JP2009225018A (en) | 2008-03-14 | 2009-10-01 | Nec Corp | Decision feedback equalization apparatus and method |
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