CN105390510A - 低温多晶硅tft基板及其制作方法 - Google Patents
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 85
- 239000000758 substrate Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229920005591 polysilicon Polymers 0.000 claims description 42
- 239000012212 insulator Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 24
- 150000002500 ions Chemical class 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- -1 phosphonium ion Chemical class 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
本发明提供一种低温多晶硅TFT基板及其制作方法。本发明的低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。本发明的低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
Description
技术领域
本发明涉及显示技术领域，尤其涉及一种低温多晶硅TFT基板及其制作方法。
背景技术
液晶显示装置(LiquidCrystalDisplay，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。
现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括壳体、设于壳体内的液晶面板及设于壳体内的背光模组(Backlightmodule)。传统的液晶面板的结构是由一彩色滤光片基板(ColorFilterSubstrate)、一薄膜晶体管阵列基板(ThinFilmTransistorArraySubstrate，TFTArraySubstrate)以及一配置于两基板间的液晶层(LiquidCrystalLayer)所构成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
低温多晶硅(LowTemperaturePoly-silicon，LTPS)技术是新一代TFT基板的制造技术，与传统非晶硅(a-Si)技术的最大差异在于，低温多晶硅显示器反应速度较快，且有高亮度、高解析度与低耗电量等优点。低温多晶硅技术中，目前各大厂家较常用的是顶栅型的低温多晶硅TFT基板，但是顶栅型的低温多晶硅TFT基板中为了防止光照对漏电流的影响，一般都会在有效显示区域(ActiveArea，AA)的TFT器件底部增加遮光金属层，这样就增加了低温多晶硅TFT基板的制程成本。由此可见开发底栅型低温多晶硅TFT基板工艺对于节省成本，增加产能具有重要意义。
请参阅图1，为一种现有的底栅型低温多晶硅TFT基板的剖面结构示意图，包括基板100、设于所述基板100上的栅极200、设于所述基板100与栅极200上的栅极绝缘层300、设于所述栅极绝缘层300上的多晶硅层400、设于所述栅极绝缘层300与多晶硅层400上的源极500与漏极600；所述多晶硅层400包括位于两侧且分别与所述源极500与漏极600相接触的源/漏极接触区410、位于所述多晶硅层400中间的沟道区420、及位于所述源/漏极接触区410与沟道区420之间的轻掺杂漏区(LDD)430。在该低温多晶硅TFT基板的制作方法中，所述源/漏极接触区410、沟道区420、及轻掺杂漏区430这三个区域都需要单独掺杂，这样在制程中至少需要两道光罩，工艺较为繁琐，生产效率较低，生产成本较高。
因此，有必要提供一种低温多晶硅TFT基板及其制作方法，以解决上述问题。
发明内容
本发明的目的在于提供一种低温多晶硅TFT基板，沟道区上方设有金属层，沟道区的电阻较低，TFT的开态电流较高。
本发明的目的还在于提供一种低温多晶硅TFT基板的制作方法，通过在沟道区上方制作金属层，并将金属层、及源极与漏极作为光罩在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩，节省生产成本，提高产能。
为实现上述目的，本发明提供一种低温多晶硅TFT基板，包括基板、设于所述基板上的栅极、设于所述基板与栅极上的栅极绝缘层、设于所述栅极绝缘层上的多晶硅层、设于所述栅极绝缘层与多晶硅层上的源极与漏极、及设于所述多晶硅层上且位于所述源极与漏极之间的金属层；
所述多晶硅层包括位于两侧且分别与所述源极与漏极相接触的源/漏极接触区、位于所述金属层下方的沟道区、及位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
所述基板为玻璃基板。
所述栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，在所述基板上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极；
步骤2、在所述基板与栅极上沉积栅极绝缘层；
步骤3、在所述栅极绝缘层上形成多晶硅层；
步骤4、对所述多晶硅层的两侧区域进行离子植入，形成源/漏极接触区；对所述多晶硅层的中间区域进行离子植入，形成沟道区；
步骤5、在所述栅极绝缘层与多晶硅层上沉积第二金属层，并对所述第二金属层进行图案化处理，形成源极、漏极、及位于所述源极与漏极之间的金属层；
步骤6、以所述金属层、及源、漏极为光罩，对所述多晶硅层进行离子植入，得到位于所述源/漏极接触区与沟道区之间的轻掺杂漏区。
所述步骤1中的基板为玻璃基板。
所述步骤2中的栅极绝缘层的材料为氮化硅、氧化硅、或二者的组合。
所述栅极、源极、漏极、及金属层的材料为钼、铝、铜中的一种或多种的堆栈组合。
所述源/漏极接触区为N型重掺杂区，所述沟道区为P型重掺杂区，所述轻掺杂漏区为N型轻掺杂区；或者所述源/漏极接触区为P型重掺杂区，所述沟道区为N型重掺杂区，所述轻掺杂漏区为N型轻掺杂区。
本发明的有益效果：本发明的低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。本发明的低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的低温多晶硅TFT基板的剖面结构示意图；
图2为本发明的低温多晶硅TFT基板的剖面结构示意图；
图3为本发明的低温多晶硅TFT基板的制作方法的示意流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先一种低温多晶硅TFT基板，包括基板1、设于所述基板1上的栅极2、设于所述基板1与栅极2上的栅极绝缘层3、设于所述栅极绝缘层3上的多晶硅层4、设于所述栅极绝缘层3与多晶硅层4上的源极5与漏极6、及设于所述多晶硅层4上且位于所述源极5与漏极6之间的金属层7。
所述多晶硅层4包括位于两侧且分别与所述源极5与漏极6相接触的源/漏极接触区41、位于所述金属层7下方的沟道区42、及位于所述源/漏极接触区41与沟道区42之间的轻掺杂漏区43。
具体地，所述基板1为玻璃基板。
具体地，所述栅极绝缘层3的材料可以是氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
具体地，所述栅极2、源极5、漏极6、及金属层7的材料为钼(Mo)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
可选的，所述源/漏极接触区41为N型重掺杂区，所述沟道区42为P型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区；或者所述源/漏极接触区41为P型重掺杂区，所述沟道区42为N型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区。
优选的，所述N型重掺杂区与N型轻掺杂区中掺杂的离子为磷离子或砷离子；所述P型重掺杂区中掺杂的离子为硼离子或镓离子。
具体的，所述N型重掺杂区或P型重掺杂区中掺杂的离子浓度范围为1019～1021ions/cm3，所述N型轻掺杂区中掺杂的离子浓度范围为1016～1017ions/cm3。
上述低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。
请参阅图3，同时参阅图2，本发明还提供一种低温多晶硅TFT基板的制作方法，包括如下步骤：
步骤1、提供基板1，在所述基板1上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极2。
具体地，所述步骤1中的基板1为玻璃基板。
步骤2、在所述基板1与栅极2上沉积栅极绝缘层3。
具体地，所述步骤2中的栅极绝缘层3的材料为氮化硅、氧化硅、或二者的组合。
步骤3、在所述栅极绝缘层3上形成多晶硅层4。
步骤4、对所述多晶硅层4的两侧区域进行离子植入，形成源/漏极接触区41；对所述多晶硅层4的中间区域进行离子植入，形成沟道区42。
步骤5、在所述栅极绝缘层3与多晶硅层4上沉积第二金属层，并对所述第二金属层进行图案化处理，形成源极5、漏极6、及位于所述源极5与漏极6之间的金属层7。
具体地，所述栅极2、源极5、漏极6、及金属层7的材料为钼、铝、铜中的一种或多种的堆栈组合。
步骤6、以所述金属层7、及源、漏极5、6为光罩，对所述多晶硅层4进行离子植入，得到位于所述源/漏极接触区41与沟道区42之间的轻掺杂漏区43。
可选的，所述源/漏极接触区41为N型重掺杂区，所述沟道区42为P型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区；或者所述源/漏极接触区41为P型重掺杂区，所述沟道区42为N型重掺杂区，所述轻掺杂漏区43为N型轻掺杂区。
优选的，所述N型重掺杂区与N型轻掺杂区中掺杂的离子为磷离子或砷离子；所述P型重掺杂区中掺杂的离子为硼离子或镓离子。
具体的，所述N型重掺杂区或P型重掺杂区中掺杂的离子浓度范围为1019～1021ions/cm3，所述N型轻掺杂区中掺杂的离子浓度范围为1016～1017ions/cm3。
上述低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
综上所述，本发明的低温多晶硅TFT基板，沟道区上方设有金属层，可将所述金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少形成轻掺杂漏区所单独需要的光罩；同时由于增加了一层与多晶硅层沟道区相连的金属层，可以有效降低沟道区的电阻，提高TFT的开态电流。本发明的低温多晶硅TFT基板的制作方法，通过在形成源极与漏极的同时，在沟道区上方形成金属层，并将金属层、及源极与漏极作为光罩，在多晶硅层上形成轻掺杂漏区，减少了形成轻掺杂漏区所单独需要的光罩，从而节省了生产成本，提高了产能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。
Claims (10)
1.一种低温多晶硅TFT基板，其特征在于，包括基板(1)、设于所述基板(1)上的栅极(2)、设于所述基板(1)与栅极(2)上的栅极绝缘层(3)、设于所述栅极绝缘层(3)上的多晶硅层(4)、设于所述栅极绝缘层(3)与多晶硅层(4)上的源极(5)与漏极(6)、及设于所述多晶硅层(4)上且位于所述源极(5)与漏极(6)之间的金属层(7)；
所述多晶硅层(4)包括位于两侧且分别与所述源极(5)与漏极(6)相接触的源/漏极接触区(41)、位于所述金属层(7)下方的沟道区(42)、及位于所述源/漏极接触区(41)与沟道区(42)之间的轻掺杂漏区(43)。
2.如权利要求1所述的低温多晶硅TFT基板，其特征在于，所述基板(1)为玻璃基板。
3.如权利要求1所述的低温多晶硅TFT基板，其特征在于，所述栅极绝缘层(3)的材料为氮化硅、氧化硅、或二者的组合。
4.如权利要求1所述的低温多晶硅TFT基板，其特征在于，所述栅极(2)、源极(5)、漏极(6)、及金属层(7)的材料为钼、铝、铜中的一种或多种的堆栈组合。
5.如权利要求1所述的低温多晶硅TFT基板，其特征在于，所述源/漏极接触区(41)为N型重掺杂区，所述沟道区(42)为P型重掺杂区，所述轻掺杂漏区(43)为N型轻掺杂区；或者所述源/漏极接触区(41)为P型重掺杂区，所述沟道区(42)为N型重掺杂区，所述轻掺杂漏区(43)为N型轻掺杂区。
6.一种低温多晶硅TFT基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供基板(1)，在所述基板(1)上沉积第一金属层，并对所述第一金属层进行图案化处理，形成栅极(2)；
步骤2、在所述基板(1)与栅极(2)上沉积栅极绝缘层(3)；
步骤3、在所述栅极绝缘层(3)上形成多晶硅层(4)；
步骤4、对所述多晶硅层(4)的两侧区域进行离子植入，形成源/漏极接触区(41)；对所述多晶硅层(4)的中间区域进行离子植入，形成沟道区(42)；
步骤5、在所述栅极绝缘层(3)与多晶硅层(4)上沉积第二金属层，并对所述第二金属层进行图案化处理，形成源极(5)、漏极(6)、及位于所述源极(5)与漏极(6)之间的金属层(7)；
步骤6、以所述金属层(7)、及源、漏极(5、6)为光罩，对所述多晶硅层(4)进行离子植入，得到位于所述源/漏极接触区(41)与沟道区(42)之间的轻掺杂漏区(43)。
7.如权利要求6所述的低温多晶硅TFT基板的制作方法，其特征在于，所述步骤1中的基板(1)为玻璃基板。
8.如权利要求6所述的低温多晶硅TFT基板的制作方法，其特征在于，所述步骤2中的栅极绝缘层(3)的材料为氮化硅、氧化硅、或二者的组合。
9.如权利要求6所述的低温多晶硅TFT基板的制作方法，其特征在于，所述栅极(2)、源极(5)、漏极(6)、及金属层(7)的材料为钼、铝、铜中的一种或多种的堆栈组合。
10.如权利要求6所述的低温多晶硅TFT基板的制作方法，其特征在于，所述源/漏极接触区(41)为N型重掺杂区，所述沟道区(42)为P型重掺杂区，所述轻掺杂漏区(43)为N型轻掺杂区；或者所述源/漏极接触区(41)为P型重掺杂区，所述沟道区(42)为N型重掺杂区，所述轻掺杂漏区(43)为N型轻掺杂区。
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