CN105355570A - 半导体芯片及形成芯片焊盘的方法 - Google Patents

半导体芯片及形成芯片焊盘的方法 Download PDF

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CN105355570A
CN105355570A CN201510617597.9A CN201510617597A CN105355570A CN 105355570 A CN105355570 A CN 105355570A CN 201510617597 A CN201510617597 A CN 201510617597A CN 105355570 A CN105355570 A CN 105355570A
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chip
copper
barrier layer
pad
layers
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CN105355570B (zh
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M·科伊茨
S·克拉姆普
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及半导体芯片及形成芯片焊盘的方法。公开了一种具有不同芯片焊盘的半导体芯片以及形成具有不同芯片焊盘的半导体芯片的方法。在一些实施例中，该方法包括在芯片正面上方沉积阻挡层，在沉积阻挡层之后沉积铜层，以及去除位于第一芯片焊盘区域之外的铜层的部分，其中在第一芯片焊盘区域内的铜层的剩余部分形成该芯片焊盘的表面层。该方法还包括去除位于第一芯片焊盘区域之外的阻挡层的部分。

Description

半导体芯片及形成芯片焊盘的方法
技术领域
实施例涉及芯片焊盘并且特别涉及一种半导体芯片及形成芯片焊盘的方法。
背景技术
虽然市场上存在可焊芯片背面，但是可焊芯片正面的制备是大得多的挑战。可焊正面的技术挑战是结合制备工艺找到能应对多种方面的材料系统。这些包括良好的电接触性质、良好的机械接触性质、良好的可焊接性、与电子器件需求的兼容性，例如没有表面泄漏电流、与各种芯片表面的兼容性，例如与钝化和金属化材料可兼容，无腐蚀，显示良好的与模塑材料的粘附性以及可接合至诸如铜(Cu)、铝(Al)和金(Au)线接合的线接合。此外，制备工艺应当是廉价的、能够大处理窗口(processingwindows)(例如能够高产能)，以及适合于铅焊料和无铅焊料。
发明内容
一些实施例涉及形成芯片焊盘的方法。该方法包括在芯片正面上方沉积阻挡层，以及在沉积阻挡层之后沉积铜层。该方法还包括去除至少位于第一芯片焊盘区域之外的铜层部分，其中第一芯片焊盘区域内铜层的剩余部分形成该芯片焊盘的表面层，以及去除至少位于第一芯片焊盘区域之外的阻挡层部分。
一些实施例涉及半导体芯片。该半导体芯片包括第一芯片焊盘和第二芯片焊盘。该第一芯片焊盘包括主要包含铜的表面层，并且该第二芯片焊盘包括主要包含铝的表面层。
附图说明
下面将仅作为示例并参照附图描述设备和/或方法的一些实施例，其中：
图1示出根据各种实施例的形成芯片焊盘的方法的流程图；
图2A至2D示出了根据各种实施例的形成芯片焊盘的方法的示意性图解；以及
图3示出了根据各种实施例的半导体芯片的示意性图解。
具体实施方式
现在将参照附图更全面描述各种示例实施例，在这些附图中图示了一些示例实施例。在附图中，为了清楚起见，可以放大各线、层和/或区域的厚度。
因此，虽然示例实施例能够具有各种修改和替换的形式，但其实施例在附图中是作为示例示出且将在本文中进行详细描述。然而，应该理解，不意图将示例实施例限制为特定公开的形式，而是相反地，示例实施例覆盖了落在本公开的范围内的所有修改、等效和替换。遍及附图的描述，相似的附图标记指代相似或类似元件。
应当理解，当元件被称为“连接”或“耦合”至另一元件时，其可以是直接连接或耦合至其他元件，或者可存在中间元件。相比之下，当元件被称为“直接连接”或“直接耦合”至另一元件时，将不存在中间元件。描述元件之间关系所使用的其他词应当按类似的方式来解释(例如，“在......之间”对“直接在......之间”，“邻近”和“直接邻近”等等)。
本文中使用的术语只是为了描述特定实施例的目的而不意在限制示例实施例。如本文中所使用的，单数形式“一”、“一个”和“该”意在也包括复数形式，除非上下文明确另有指示。还应当理解，术语“包括”、“包含了”、“包含”和/或“包含了”当在本文中使用时指定了所述特征、整数、步骤、操作、元件和/或部件的存在，但是并不排除一个或多个其他特征、整数、步骤、操作、元件、部件和/或他们的组的存在或附加。
除非另有限定，本文中使用的所有术语(包含技术和科学术语)具有与示例实施例所属于的领域普通技术人员通常理解的相同的含义。还应当理解，例如在通常使用的字典中限定的那些术语的术语应当被解释为具有与相关领域上下文中的它们的含义相一致的含义并且不应当解释为理想的或过度正式的意思，除非在文中明确这样限定。
图1示出了根据一个实施例的形成芯片焊盘的方法100的流程图。
方法100包括在芯片正面上方沉积110阻挡层以及在沉积阻挡层之后沉积120铜层。
方法100还包括去除130至少位于第一芯片焊盘区域之外的铜层的部分。在第一芯片焊盘区域内铜层的剩余部分形成该芯片焊盘的表面层。
方法100还包括去除140至少位于第一芯片焊盘区域之外的阻挡层的部分。
由于在芯片正面上方沉积阻挡层和铜层以及去除至少位于第一芯片焊盘区域之外的铜层部分和阻挡层部分，例如可以形成具有铜表面层的芯片焊盘和没有铜表面层的芯片焊盘。
方法100可被实现为形成芯片的芯片焊盘。该芯片可以包括衬底(例如半导体衬底或玻璃衬底)和一个或多个电绝缘层和/或导电层，例如它们可以被堆叠在芯片的正面上。半导体芯片可包括半导体衬底材料，且可包括一个或多个芯片中的集成电路器件。例如，该芯片可以是功率半导体芯片或CMOS半导体芯片。集成电路器件可包括例如一个或多个晶体管，例如功率晶体管，例如MOSFET或IGBT，和/或一个或多个二极管。
该半导体芯片可以是可包含半导体衬底或晶片的部分的半导体管芯。例如，该半导体衬底可以是硅基半导体衬底或碳化硅基半导体衬底或砷化镓基半导体衬底或氮化镓基半导体衬底。
该芯片可包括芯片正面和芯片背面。与该芯片的衬底的基本垂直边缘(例如起因于使芯片衬底与其他部分分离)相比，芯片的主表面或芯片正面可以是横向延伸的基本上水平表面。
芯片的主表面或正面表面是朝向衬底的表面的顶部上的金属层、绝缘层和/或钝化层或这些层中的一个的表面的衬底的表面。例如，芯片正面可以是其处形成芯片的有源元件的面。例如，在功率半导体芯片中，芯片正面可以是其处形成第一源/漏区和栅区的芯片的面，以及芯片背面可以是其处形成第二源/漏区的芯片的面。例如，更复杂的结构可以被设置在芯片正面处而不是芯片背面处。
芯片焊盘区域可以包括在芯片正面或表面处和/或上的导电接触区域。该芯片焊盘区域可以电连接至该芯片的集成电路器件的至少一个电有源元件。例如，芯片焊盘区域可电连接至有源源/漏区，且芯片焊盘区域还可电连接至有源栅区。在其他示例中，芯片焊盘区域和另外的芯片焊盘区域可电连接(例如短路)至相同有源元件。芯片焊盘区域可直接连接至电有源元件，或可选择地通过一个或多个互连或中间层。芯片焊盘区域还可用于提供芯片的集成电路器件的至少一个电有源元件和外部结构和/或外部电路之间的电连接。
该阻挡层可以是用作蚀刻停止层的层和/或扩散阻挡层。例如，以方法100沉积的阻挡层可以是可以被沉积在整个芯片正面上方的金属层。
该阻挡层209可以是钛钨(TiW)层。例如，钨含量的范围可以从60％至90％，例如70％至85％。例如，该阻挡层209可以具有Ti0.2W0.8的组成。该钛钨层可以具有在20nm至约200nm之间的平均厚度，例如约50nm至约150nm。
以方法100沉积的铜(Cu)层也可被沉积在整个芯片正面上方。例如，该铜层可被沉积在阻挡层上方或直接沉积在阻挡层上。
该铜层211主要可以为铜。例如，该铜层可具有大于50％的铜含量，例如大于90％，例如大于99％。该铜层可以具有在0.5μm至50μm之间的平均厚度，例如约1μm至50μm。该铜层厚度可以取决于晶片/芯片的弓限(bowrestriction)、使用的焊接系统和扩散电阻而被选择。
去除至少位于第一芯片焊盘区域之外的铜层的部分可以不覆盖至少位于第一芯片焊盘区域之外的阻挡层的部分。然后，至少在第一芯片焊盘区域之外的位置处随后也可以去除阻挡层。
由于在芯片正面上方沉积阻挡层和铜层以及去除至少位于第一芯片焊盘区域之外的铜层的部分和阻挡层的部分，在表面处可以形成具有不同材料的不同芯片焊盘，例如其可创建具有可焊和可接合芯片焊盘两者的通用器件。
至少位于第一芯片焊盘区域之外的铜层的部分的去除可通过用第一蚀刻剂蚀刻铜层来执行。至少位于第一芯片焊盘区域之外的阻挡层的部分的去除可通过用可不同于第一蚀刻剂的第二蚀刻剂蚀刻阻挡层来执行。
蚀刻至少位于第一芯片焊盘区域之外的铜层的部分不覆盖至少在第一芯片焊盘区域之外的阻挡层的部分。阻挡层可以用作抵抗第一蚀刻剂的蚀刻停止层，且例如可保护任何下层特征或芯片正面上的层免受第一蚀刻剂。例如阻挡层可保护第二芯片焊盘区域或其他导电结构(例如测试或监测结构)免受用于蚀刻铜层的第一蚀刻剂。
图2A至2D示出了根据实施例的形成芯片焊盘的方法的示意性图解。
如图2A所示，半导体芯片201的芯片焊盘204、205可以包括形成在芯片正面202上方预先确定位置中的导电材料206、207。例如，第一芯片焊盘区域204包括导电材料206，其可以与芯片上的器件的第一有源元件电接触。例如，这可以是晶体管的第一源/漏区。例如，该第二芯片焊盘区域205可以包括导电材料207，其可以与芯片上的器件的第二有源元件电接触。例如，这可以是晶体管的栅区。芯片背面203也可包括背面接触，其可以与芯片上的器件的第二有源元件电接触。例如，这可以是用于晶体管的第二源/漏区的背面金属化层。
电绝缘材料208可被沉积或形成在芯片焊盘区域204、205上方。该电绝缘材料208部分围绕芯片焊盘区域204、205的部分。电绝缘材料中预先限定的位置中形成的孔暴露芯片焊盘区域204、205中的每一个的至少一部分(在芯片正面表面处的导电材料206、207)。例如，该电绝缘材料208可在某些预先限定的位置处被去除，例如，从每个芯片焊盘区域204、205上方的区域去除。
该电绝缘材料208可包括例如聚酰亚胺或由例如聚酰亚胺组成。导电材料206、207可包括例如铝或由例如铝组成。例如，导电材料206、207可包括或具有主要为铝的组成，例如可具有大于50％的铝含量，或大于90％，或大于99％。
可选择地、可替换地或附加地，在芯片正面202上方沉积阻挡层之前，可以将由箭头214代表的非氧化等离子体施加至芯片正面202(见图2A)。该非氧化等离子体可被施加至芯片作为原位金属表面清洗。例如，该非氧化等离子体可以为Ar+溅射清洗，其可以在SFM(可焊正面金属)沉积之前执行。例如，在清洗期间从芯片焊盘的表面(例如从导电材料206、207)去除氧化铝。
由于氧化铝的清洗和/或去除，可实现与后续层，例如后续覆盖的阻挡层和铜层SFM(如TiWCu)更好的电和机械接触。钝化层上的金属再沉积可能引起泄露电流，可是其可通过选择合适的工艺参数来避免。
图2B示出了在芯片正面202上方TiW阻挡层209的沉积215(如结合图1描述的)。可以沉积该阻挡层使得其例如共形地覆盖例如芯片焊盘区域204、205，电绝缘材料208和电绝缘材料208的孔的一个或多个侧壁。
沉积阻挡层209之后可以沉积铜层211，例如，如方法100的120中所描述的。铜层可例如共形地覆盖或可形成在阻挡层209上方。例如，铜层211可直接形成在TiW阻挡层209上。
例如，TiW和/或Cu的沉积可通过诸如蒸发或溅射沉积的沉积工艺来执行。
铜层211可用作焊接伴侣(partner)，其对于引线和无引线焊接连接可以是理想的。该阻挡层(TiW)209可用作铝基芯片金属化，例如芯片焊盘区域204、205的导电材料206、207和焊接伴侣(Cu)之间的机械粘附性促进剂，
由于例如TiW和Cu材料的选择以及对应的沉积所选材料的沉积方法，可避免剥离结构化，其避免了不想要的剥离残余的产生，以及芯片焊盘的不充分清洗。此外，用来达到TiW和相邻金属层(例如下方的Al和上方的Cu)之间的良好粘附性的金属间相可相对是薄的。因此，可从一开始就避免厚且通常易碎的金属间相。
图2C示出了位于至少第一芯片焊盘区域204之外铜层211的部分被去除(例如，如结合图1描述)以及位于至少第一芯片焊盘区域204之外TiW阻挡层209的部分被去除(例如，如结合图1描述)。例如，图2C示出了正被执行的SFM结构化。
通过第一蚀刻剂的对铜层211的Cu的蚀刻由于通过TiW阻挡层的保护而在不损坏铝和/或硅区的情况下执行。例如，可保护芯片焊盘区域204、205的导电材料206、207。该第一蚀刻剂例如可包括磷酸或硫酸。
随后，通过第二蚀刻剂对阻挡层209的TiW蚀刻不可能引起对Al、硅、酰亚胺或氧化物的损坏。该第二蚀刻剂例如可以是过氧化氢(H2O2)。TiW可以被选择作为如其他材料的阻挡层209，例如纯Ti不能被软H2O2蚀刻结构化。
去除位于第一芯片区域204之外的铜层211和阻挡层209的部分导致从第二芯片焊盘区域205去除的铜层211和阻挡层209。可是铜层211和阻挡层209的剩余部分保留在第一芯片焊盘区域204内。因此，被去除的铜层211和阻挡层209暴露了第二芯片焊盘区域205(例如暴露第二芯片焊盘区域205的导电材料207)。铜层211和阻挡层209的剩余部分仍然覆盖第一芯片焊盘区域204的第一导电材料206。铜层211的剩余部分形成第一芯片焊盘区域204的表面层，例如第一芯片焊盘的表面层。
当通过去除位于第一芯片区域之外的铜层211和阻挡层209而暴露铝第二芯片焊盘区域205时，第二芯片焊盘区域的表面层为主要包括铝的导电材料207。
对于低焊剂焊接系统，可以在阻挡层209上方沉积铜层211之后可选择地用氧化保护层，例如银或金的氧化保护层覆盖铜层211。该氧化保护层的沉积可直接在铜层211的沉积之后执行或在铜层211的沉积之后的后续工艺中执行。例如，在去除位于第一芯片区域204之外的铜层211和阻挡层209的部分之后，仍然覆盖第一芯片焊盘区域204的第一导电材料206的铜层211的剩余部分可以可选择性地通过在该铜层211的剩余部分上方沉积氧化保护层而用氧化保护层覆盖。
由于选择TiW作为铝基芯片金属化和焊接伴侣Cu之间的阻挡层和机械粘附性促进层，可从Cu蚀刻保护该Al焊盘。由于其对应蚀刻剂的选择，可以侵蚀Al表面的Cu的化学结构化例如通过实现TiW阻挡层而可以被避免。此外，用H2O2进行的TiW结构化可以是可能的，由此不侵蚀衬底上的例如AlCu和/或Al的钝化材料和金属化材料(例如，在工艺控制监控中或在芯片自身上)。尽管目标在Ti20％W80％处，但化合物组成的变体在蚀刻化学工艺窗口内可以是可能的。
如图2D，该方法还包括由箭头216所表示的施加氧等离子体至芯片正面。例如该氧等离子体可至少施加至第二芯片焊盘区域的表面层。该氧等离子体可用于在暴露的第二芯片焊盘区域205的表面层上创建氧化铝钝化层。例如在氧气(O2)闪蒸工艺期间也在暴露的第一芯片焊盘区域204的表面层上可以产生氧化铜。
由于用于执行芯片正面202的表面钝化而在TiWCu结构化之后施加氧气(O2)等离子体工艺，在敞开放置的铝焊盘上可以创建轮廓分明的质量氧化铝层。这可以保证用于引线接合的稳定表面并且也可以在后续工艺期间保护免受侵蚀，例如在芯片个体化(例如划片)期间来自去离子水(DI水)的侵蚀，或在芯片焊接期间来自软焊料的侵蚀，或在软焊料清洗之后或在结合焊剂的回流工艺期间来自DI水的侵蚀。此外，它从金属残留物清洗掉钝化物(聚酰亚胺)，因此避免了泄漏电流并提供了轮廓分明的酰亚胺表面以用于至模塑料的良好粘附性，尽管可能发生酰亚胺层的干燥。
在一些实施例中，可以跳过图2A中描述的原位金属表面清洗和/或图2D中描述的表面钝化工艺。
该方法可还包括将接合引线接合至第二芯片焊盘区域205的表面层。例如，该接合引线可接合至第二芯片焊盘区域205的铝表面层207。例如，该接合引线包括来自下述材料组的至少一种材料，该材料组包括铝、铜、金或银。可通过例如球接合、楔形接合或钉头接合来将该接合引线接合至第二芯片焊盘区域205。
随后，可以在第一芯片焊盘区域204的表面层上方(例如铜层211上方)沉积焊接材料。因此，焊接材料可以与第一芯片焊盘区域204的表面层相接触。例如该焊接材料可包括锡(Sn)。该方法还包括例如在焊料回流工艺中熔化该焊接材料和在第一芯片焊盘区域204内的铜层的至少一部分，以将第一芯片焊盘区域204焊接至外部结构。
正面边缘终端区域可以用作焊盘保护器，其可保护下面的金属层免受焊料或软焊料，其中没有进一步的复合物。可通过使用在钝化层上重叠TiWCu的掩模设计来创建该正面边缘终端区域。例如该掩模设计可在铜层的去除和TiW阻挡层的去除工艺期间(例如结合图1和图2B所描述的)实现。例如该掩模设计可布置为使得该TiW阻挡层和铜层的剩余部分能覆盖第一芯片焊盘且也覆盖第一芯片焊盘周围的电绝缘聚酰亚胺部分。这意味着例如TiW阻挡层和铜层可以大于第一芯片焊盘。例如，TiW阻挡层和铜层可以覆盖(例如，完全覆盖)导电材料206，和/或电绝缘材料208的一个或多个侧壁，和/或平行于芯片正面的电绝缘材料208的表面区域。
在氧气闪蒸工艺期间产生的任何氧化铜可以溶解在软焊料中。由于铜和氧化铜的后续产物的选择，该氧化铜可很容易去除，且可避免诸如镍基系统中面临的那些问题的问题。例如，氧化镍太困难以致不被溶解在普通软焊料中或者不可能被溶解在普通软焊料中，且因此用价格昂贵的金(Au)或银(Ag)的氧化物保护层来覆盖。
焊料中锡的含量越大，焊料轮廓越长且越热，且焊料连接的期望寿命越长，因此，例如更厚的Cu可被沉积，以便以简单方式来满足需求。根据需求可以采用该TiW和Cu层的厚度。
由于将接合引线接合至第二芯片焊盘区域和/或将焊接材料接合至第一芯片焊盘区域的实现，可达到包括用于焊接的芯片焊盘和用于引线接合的芯片焊盘的器件。此外，创建了用于制造商的选择，其中终端用户可在引线接合焊盘或可焊接焊盘之间选择。在不需要焊料的区，诸如用于引线接合的第二芯片焊盘区域205的Al表面，结构化掩模的设计方案可被实现为制造无TiWCu的焊盘。Cu和TiW的结构化使用廉价的湿法化学且易于掌握。
尽管关于附图只示出并描述了第一芯片焊盘区域和第二芯片焊盘区域的形成，但可以理解关于图1和图2A至2D描述的方法也可以适用于具有多于一个的第一芯片焊盘区域和可选一个或多个第二芯片焊盘区域的芯片，或适用于多于一个的芯片。例如，该方法可以适用于在相同芯片上创建多个具有铜表面层的第一类型芯片焊盘区域(例如，第一芯片焊盘区域)和多个具有铝表面层的第二类型芯片焊盘区域(例如，第二芯片焊盘区域)。该方法也可通过晶片或衬底的批处理来执行，其可以包括多个半导体芯片，例如十几个、或数百个或数千个半导体芯片。
尽管锡基焊料(引线和无引线)可以创建Ni-Sn金属间相，其为在Ni和焊料之间的良好的电学和机械接触作准备，但是Ni需要氧化保护。例如，在使用剥离技术结构化的Al(Si)Cu-Ti-NiV-Ag金属层系统中，Ag作为Ni的氧化保护的使用仅有限地完成该任务。例如，对于厚度为1000nm的Ag，在温度高于100℃时可能发生显著的氧扩散，其可能导致Ni氧化以及焊接问题。可能需要精心的工艺控制来避免焊接问题。例如，该TiWCu堆叠能够避免该工艺限制。自然氧化铜可充当钝化，其可通过标准焊剂系统去除。文中描述的一个或多个实施例可避免这些问题。
另一个金属层系统，例如NiP-Au或NiP-Ag沉积，通常可通过电化工艺来执行，其中通过钝化开口或预电镀指定正面焊盘。由于没有剥离光刻胶，在NiP-Au(或Ag)沉积之前对Al表面层更好的清洗，以便达到更好的机械粘附性和电接触。其也可以与无引线焊接兼容，因为厚镍层可以不完全被无引线焊接所消耗并且也可以对于制造相对便宜。可是，正面边缘终端(例如，对下层焊盘边缘区域面积免于焊接/软焊接的保护)可能在技术上太难而无法实现。文中描述的一个或多个实施例可避免这些问题。
对于经由湿法化学蚀刻的AlCu-Cu金属层系统，Cu蚀刻化学物例如在锯框架中或在无铜芯片焊盘上可能与Al表面不兼容。此外，在铜焊盘在正向电势处的情况下，硫或磷模塑料中可能发生铜迁移问题。文中描述的实施例避免了这些问题。
结合上面或下面描述的实施例，更多细节和方面被提到(例如半导体芯片、第一芯片焊盘、第二芯片焊盘、阻挡层、铜层、焊接材料和接合引线)。图2A-2D所示的实施例可以包括一个或多个可选附加特征，其对应于结合所提概念或一个或多个上述(例如图1)或下述(例如图3)的实施例提到的一个或多个方面。
图3示出了根据实施例的半导体芯片300的示意性图解。
半导体芯片300包括第一芯片焊盘204和第二芯片焊盘205。
第一芯片焊盘204包括主要包含铜的表面层211，并且第二芯片焊盘205包括主要包含铝的表面层207。
由于在芯片正面上的芯片焊盘的实现(例如Cu或Al的金属焊盘)，可产生具有通用芯片连接可能性的芯片封装。
可选择地，第一芯片焊盘204还包括钛钨阻挡层，例如根据图1和图2A-2D所述的在第一芯片焊盘204的表面层211下的钛钨阻挡层209。
例如，第一芯片焊盘204和第二芯片焊盘205可形成在芯片正面上。
例如，半导体芯片300还包括沉积在第一芯片焊盘204的表面层上的焊接材料312。该半导体芯片300可还包括接合至第二芯片焊盘205的表面层的接合引线313。该半导体芯片300、焊接材料312和接合引线313可包含已经在图1和图2A-2D的实施例中所描述的半导体芯片、焊接材料和接合引线的一个或多个或全部特征。
由于在芯片正面上的芯片焊盘的实现(例如，Cu或Al金属焊盘)，各种芯片封装和他们的内部互连，例如用于焊接连接的铜焊盘、或例如用于Al楔形、Cu或Au针头引线接合连接的Al焊盘，可被优化设计或根据用户的愿望(芯片直接交付)设计。通过将是无铜的要求也可以在芯片上制造有Cu迁移倾向的焊盘。
结合上面描述的实施例，更多细节和方面被提到(例如半导体芯片、第一芯片焊盘、第二芯片焊盘、阻挡层、铜层、焊接材料和接合引线)。图3所描述的实施例可包括一个或多个可选附加特征，其对应于结合所提概念或一个或多个上述(例如图1或图2A-2D)的实施例提到的一个或多个方面。
各种实施例涉及TiWCu可焊接正面金属(SFM)和/或优化的铜基可焊接芯片正面。
相较于普通焊接正面金属化，各种实施例提供了明显更容易、更通用、更廉价和质量上高等级的解决方案。
各种实施例涉及结合适当的用于芯片正面的制造工艺的牢固的金属层系统AlCu-TiW-Cu，可以被廉价地焊接，其应用在各种领域中是通用的，且适合于引线和无引线焊接。各种实施例提供了与有机基钝化(用来封装模塑化合物的作为粘附性促进剂的酰亚胺)结合的良好或优化的电机械粘附性，例如其不会破坏或损害Al表面。
各种实施例遵循焊接伴随物越少可以越容易掌握或控制金属系统的原则。在这种情况下，焊接伴随物只能是Cu和Sn。工艺越简单，制造成本越低且系统可以是越容易在高产量中以稳定地生产。
各种实施例基于所提出的概念，且解决了比其他解决方案更多的技术需求并在铜金属化上维持了技术改进。
当在计算机或处理器上执行该计算机程序时，示例实施例还提供了具有用于执行上述方法之一的程序代码的计算机程序。本领域技术人员应当容易意识到各种上述方法可通过编程计算机执行的动作。文中，一些示例实施例也意在覆盖程序存储器件，例如数字数据存储介质，其是机器或计算机可读的和编码机器可执行的或计算机可执行的指令程序，其中指令执行一些或全部上述方法的动作。该程序存储装置可以是例如数字存储器、例如磁盘和磁带的磁存储介质、硬盘驱动、或可选可读数字数据存储介质。另外的示例实施例也意在覆盖编程以执行上述方法的动作的计算机，或编程以执行上述方法的动作的(现场)可编程逻辑阵列((F)PLA或(现场)可编程栅阵列((F)PGA))。
描述和附图仅说明了本公开的原理。因此将意识到，尽管文中没有明确描述或示出，但本领域技术人员将能够想出体现本公开原理并包含在本公开精神和范围之内的各种布置。此外，文中叙述的所有示例都明确地原理性意在只是为了教学的目的以帮助读者理解本公开的原理和由(多个)发明人贡献的用来促进本领域的概念，以及被解释为不受这些具体叙述的示例和条件的限制。此外，文中叙述原理、方面和公开的实施例、以及其特定示例的所有陈述意在包含其等同物。
表示为“用于......的装置”的功能块(执行特定功能)应当被理解为包括电路的功能块，该电路被配置成分别执行特定功能。因此，“用于什么事物的装置”也可以被理解为“配置为或适合于什么事物的装置”。因此，配置为执行特定功能的装置不暗示这些装置有必要正在执行该功能(在给定时刻)。
可通过使用专用硬件来提供图中所示的各种元件的功能，其包括标记为“装置”、“用于提供传感器信号的装置”、“用于生成发射信号的装置”等的任何功能块，所述专用硬件诸如是“信号提供器”、“信号处理单元”、“处理器”、“控制器”等，以及能够结合适当软件执行该软件的硬件。此外，文中描述为“装置”的任何实体可以对应于或被实现为“一个或多个模块”、“一个或多个器件”、“一个或多个单元”等。当通过处理器提供时，该功能可通过单个专用处理器、通过单个共享处理器、或通过其中一些可被共享的多个个别处理器来提供。此外，术语“处理器”或“控制器”的明确使用不应被解释成排他地提及能够执行软件的硬件，且可没有限制地隐含包括数字信号处理器(DSP)硬件、网络处理器、专用集成电路(ASIC)、现场可编程门阵列(FPGA)、用于存储软件的只读存储器(ROM)、随机存取存储器(RAM)和非易失存储装置。也可包括其他常规的和/或定制的硬件。
本领域技术人员应当意识到，文中的任何框图代表体现本公开原理的例证性电路的概念视图。类似地，将意识到，任何流程图、流程图解、状态转变图、伪代码等代表实质上可在计算机可读媒介中表示以及因此可通过计算机或处理器执行的各种过程，无论该计算机或处理器是否被明确示出。
此外，下面权利要求由此并入详细描述中，其中每一个权利要求可以独立自主为分开的实施例。尽管每一个权利要求可以独立自主为分开的实施例，但是应当注意——尽管从属权利要求在各权利要求中可以指代与一个或多个其他权利要求的特定组合——其他实施例也可包括具有从属或独立权利要求彼此的主题的从属权利要求的组合。这种组合在文中被提出除非陈述了特定组合是不期望的。此外，意在还包括相对于其他任何独立权利要求的权利要求的特征，即使该权利要求不是直接从属于该独立权利要求。
还应当注意，说明书中或权利要求中公开的方法可通过具有用于执行这些方法的各自动作的每一个的装置的器件来实现。
此外，应当理解，说明书中或权利要求中公开的多个动作或功能的公开内容可以不被解释成在特定的次序内。因此，多个动作或功能的公开内容将不限制这些到特定的次序，除非这些动作或功能由于技术原因而是不能互换的。此外，在一些实施例中，单个行为可包括或可分解为多个子动作。这些子动作可被包含在该单个动作的公开内容中且是该单个动作的公开内容的一部分，除非被明确排除。

Claims (19)

1.一种形成芯片焊盘的方法，该方法包括：
在芯片正面上方沉积阻挡层；
沉积阻挡层之后沉积铜层；
去除位于第一芯片焊盘区域之外的铜层的部分，其中第一芯片焊盘区域内的铜层的剩余部分形成该芯片焊盘的表面层；以及
去除位于第一芯片焊盘区域之外的阻挡层的部分。
2.根据权利要求1所述的方法，其中该阻挡层是钛钨层，其中钨含量为60％-90％的范围。
3.根据权利要求2所述的方法，其中该钛钨层包括20nm至200nm之间的平均厚度。
4.根据权利要求1所述的方法，其中该铜层包括大于50％的平均铜含量。
5.根据权利要求1所述的方法，其中该铜层具有范围为0.5μm至50μm的厚度。
6.根据权利要求1所述的方法，其中去除位于第一芯片焊盘区域之外的铜层的部分通过用第一蚀刻剂对铜层蚀刻来实现，其中去除位于第一芯片焊盘区域之外的阻挡层的部分通过用第二蚀刻剂对阻挡层蚀刻来实现。
7.根据权利要求6所述的方法，其中用第一蚀刻剂来蚀刻位于第一芯片焊盘区域之外的铜层的部分不覆盖在第一芯片焊盘区域之外的阻挡层，其中阻挡层用作针对第一蚀刻剂的蚀刻停止层。
8.根据权利要求6所述的方法，其中该第二蚀刻剂包括过氧化氢。
9.根据权利要求1所述的方法，还包括在芯片正面上方沉积阻挡层之前，将非氧化等离子体施加至芯片正面。
10.根据权利要求1所述的方法，其中去除位于第一芯片焊盘区域之外的铜层的部分和阻挡层的部分暴露包括主要包含铝的表面层的第二芯片焊盘区域。
11.根据权利要求10所述的方法，还包括将氧等离子体施加至第二芯片焊盘区域的表面层。
12.根据权利要求11所述的方法，还包括将接合引线接合至第二芯片焊盘区域的表面层。
13.根据权利要求1所述的方法，还包括熔化焊接材料和第一芯片焊盘区域内的铜层的部分以将第一芯片焊盘区域焊接至外部结构。
14.根据权利要求1所述的方法，其中阻挡层和铜层沉积在整个芯片正面上方。
15.一种半导体芯片，包括：
第一芯片焊盘；以及
第二芯片焊盘，
其中该第一芯片焊盘包括主要包含铜的表面层，并且该第二芯片焊盘包括主要包含铝的表面层。
16.根据权利要求15所述的半导体芯片，其中第一芯片焊盘还包括在第一芯片焊盘表面层下方的钛钨阻挡层。
17.根据权利要求15所述的半导体芯片，其中第一芯片焊盘和第二芯片焊盘形成在芯片正面上。
18.根据权利要求15所述的半导体芯片，还包括与第一芯片焊盘的表面层相接触的焊接材料。
19.根据权利要求15所述的半导体芯片，还包括接合至第二芯片焊盘的表面层的接合引线。
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