CN105321891B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN105321891B
CN105321891B CN201510274149.3A CN201510274149A CN105321891B CN 105321891 B CN105321891 B CN 105321891B CN 201510274149 A CN201510274149 A CN 201510274149A CN 105321891 B CN105321891 B CN 105321891B
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buffer layer
mold
substrate
semiconductor devices
layer
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CN105321891A (zh
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吴念芳
史朝文
江永平
蔡豪益
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体器件和制造该半导体器件的方法。该半导体器件包括芯片衬底、模具和缓冲层。在芯片衬底上方设置模具。缓冲层从外部嵌入芯片衬底和模具之间。缓冲层具有的弹性模量或热膨胀系数小于模具的弹性模量或热膨胀系数。方法包括：设置至少覆盖衬底的划线的缓冲层；在衬底上方形成模具，并且模具覆盖缓冲层；以及沿着划线并穿过模具、缓冲层和衬底进行切割。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及封装件及其制造方法，并且更具体地，涉及晶圆级芯片规模封装件(WLCSP)及其制造方法。
背景技术
集成电路是通常为硅的半导体材料块上的一组电子电路。通过包括成像、沉积和蚀刻的操作的前道工序制造半导体集成电路，并且通过掺杂和清洁来补充该前道工序。一旦完成前道工序，就制备晶圆以用于测试和封装。
已经开发了许多不同的封装技术，包括晶圆级封装技术。晶圆级封装技术是以晶圆形式完成的，并且在切割晶圆之后完成独立单元。当执行晶圆切割时，会出现碎裂、分层或微裂缝，这些会对晶圆的关键区域产生不利的影响。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种半导体器件，包括：芯片衬底；模具，位于所述芯片衬底的上方；以及缓冲层，从外部嵌入所述芯片衬底与所述模具之间，其中，所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数。
在该半导体器件中，所述芯片衬底包括有源区域和围绕所述有源区域的保护结构区域，所述缓冲层部分地覆盖所述保护结构区域。
在该半导体器件中，所述芯片衬底包括所述保护结构区域中的伪结构和介于所述有源区域与所述伪结构之间的密封环结构，所述缓冲层覆盖所述伪结构。
该半导体器件还包括：介电层，延伸至所述芯片衬底的有源区域和所述保护结构区域上方，其中，所述缓冲层通过间隙与所述介电层分离。
在该半导体器件中，所述间隙在5um至20um的范围内。
在该半导体器件中，所述缓冲层的厚度在5um至20um的范围内。
在该半导体器件中，所述缓冲层包括聚苯并恶唑。
根据本发明的另一方面，提供了一种半导体器件，包括：芯片衬底，包括接触焊盘、分离侧壁和所述接触焊盘上方的钝化层，所述钝化层包括连接至所述分离侧壁的表面；模具，位于所述芯片衬底的上方，所述模具包括分离侧壁；以及缓冲层，位于所述钝化层的表面上，其中，所述缓冲层将所述模具的侧壁与所述芯片衬底的侧壁分离，并且所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数。
在该半导体器件中，所述芯片衬底包括有源区域和围绕所述有源区域的保护结构区域，所述缓冲层部分地覆盖所述保护结构区域。
在该半导体器件中，所述芯片衬底包括所述保护结构区域中的伪结构和介于所述有源区域与所述伪结构之间的密封环结构，所述缓冲层覆盖所述伪结构。
该半导体器件还包括：介电层，延伸至所述芯片衬底的有源区域和所述保护结构区域上方，其中，所述缓冲层通过间隙与所述介电层分离。
在该半导体器件中，所述间隙在5um至20um的范围内。
在该半导体器件中，所述缓冲层的厚度在5um至20um的范围内。
在该半导体器件中，所述缓冲层包括聚苯并恶唑。
根据本发明的又一方面，提供了一种制造半导体器件的方法，包括：接收衬底，其中，所述衬底包括至少一个芯片区域和邻近所述芯片区域的至少一条划线，并且每一个芯片区域都包括有源区域；设置至少覆盖所述划线的缓冲层；在所述每一个芯片区域上方设置包括开口的介电层；将凸块材料设置到所述介电层的开口上，并且将所述凸块材料电连接至所述有源区域；在所述衬底上方形成模具，并且所述模具覆盖所述缓冲层，其中，所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数；以及沿着所述划线切割所述衬底。
在该方法中，每一个芯片区域都包括保护结构区域，并且所述缓冲层部分覆盖所述保护结构区域。
在该方法中，设置缓冲层与设置介电层同时进行。
在该方法中，所述介电层通过在5um至20um的范围内的间隙远离所述缓冲层。
该方法还包括：在所述介电层上形成钝化后衬里，以将所述凸块材料与所述有源区域连接，并且在所述钝化后衬里上方设置另一层介电层。
在该方法中，设置另一层介电层与所述设置缓冲层同时进行。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是示出根据一些实施例的模制衬底的一部分的截面图。
图2是示出了根据一些实施例的半导体器件的截面图。
图3是根据一些实施例的另一个半导体器件的截面图。
图4是根据一些实施例的关于制造半导体器件的方法的流程图。
图5是示出根据一些实施例的另一个模制衬底的一部分的截面图。
图6是根据一些实施例的关于制造半导体器件的另一种方法的另一个流程图。
图7是根据一些实施例的关于制造半导体器件的又一种方法的又一个流程图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括附加部件形成在第一部件和第二部件之间，使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语以描述如图中所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语旨在包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述可以同样地作相应地解释。
图1是示出根据一些实施例的模制衬底的一部分的截面图。图2是示出根据一些实施例的半导体器件的截面图。
衬底1包括设置有集成电路的正面和由块状半导体材料或块状硅形成的背面。正面包括多个有源区域11，每一个有源区域都具有对应的集成电路。通过包括沉积、去除、图案化和改变电气特性的多种工艺来构建正面。沉积生长、涂覆或其他的方法(包括物理汽相沉积、化学汽相沉积、电化学沉积、分子束外延和原子层沉积)将材料设置在衬底1上。例如，包括蚀刻工艺和化学机械平坦化的去除工艺从衬底去掉材料。沉积材料的图案化的形状或改变包括掩蔽沉积材料的区域和去除沉积材料中的不期望的部分。改变电气特性工艺通过扩散炉或离子注入来注入掺杂剂材料。
在一些实施例中，衬底1包括硅。在一些实施例中，衬底1包括硅晶圆、绝缘体上硅(SOI)衬底或硅锗衬底。在一些实施例中，衬底1包括多层或梯度衬底(gradientsubstrate)。在一些实施例中，集成电路包括电子电路，诸如二极管、电阻器、电容器、熔丝、电感器、有源器件、无源器件、微机电系统组件或光学元件。在一些实施例中，集成电路执行与存储结构、处理结构、传感器、放大器、功率分布和输入/输出电路的功能类似的功能。
衬底1包括被切割道或划线12分离的水平延伸的芯片区域10。在一些实施例中，衬底1分别包括有源区域11中的接触焊盘112和接触焊盘112上方的钝化层111。形成钝化层111以作为衬底1的顶部，并且通过钝化层111中形成的对应的开口113将接触焊盘112暴露到衬底1的外部，以连接至凸块材料19。钝化层111可以覆盖接触焊盘112的边缘。在一些实施例中，接触焊盘112包括铜(Cu)和/或铝(Al)但不限于上述材料。钝化层111由介电材料制成。在一些实施例中，钝化层111由氧化硅、氮化硅、氮氧化硅、未掺杂的硅酸盐玻璃(USG)或它们的组合形成，但不限于上述材料。
提供划线12，以用锯来切割衬底1而没有损坏集成电路。划线12的宽度小，通常在约50um至约240um的范围内。每一个芯片区域10都可以包括保护结构区域13。保护结构区域13可以围绕对应的有源区域11。保护结构区域13可以位于芯片区域10的外围。划线12在两个相邻的芯片区域10的区域13之间延伸。在区域13中，形成至少一个结构14或15，以保护对应的有源区域11中的电路防止显影液水分劣化(developing moisture degradation)、离子污染、半导体芯片或器件中的裂缝或延伸进有源区域11的裂缝。至少一个结构14或15也可以形成为散热路径。至少一个结构14或15可以位于钝化层111的下面。至少一个结构14或15可以包括水平延伸的组件。至少一个结构14或15还可以包括与水平延伸的组件互连的垂直延伸的组件。
在一些实施例中，至少一个结构14或15包括对应的有源区域11与对应的划线12之间的密封环结构。密封环结构可以连续地或不连续地形成为围绕有源区域11。密封环结构可以在整个密封环结构中由相同的材料形成，或在密封环结构中的不同部分用不同的材料形成。
在一些实施例中，至少一个结构14或15包括多个密封环结构，其中多个密封环结构没有形成为连续地围绕有源区域11，或至少一个密封环结构连续地围绕有源区域11。多个密封环结构可以彼此相互分离或多个密封环结构中至少两个连接或接合。多个密封环结构可以在结构上类似或不同。多个密封环结构可以由类似的材料形成，或一个密封环结构的一部分的材料不同于其他环结构的对应部分的材料。
在一些实施例中，至少一个结构14或15包括至少一个密封环结构15和至少一个伪结构14。至少一个伪结构14连续地或不连续地形成为围绕有源区域11，并且至少一个密封环结构15连续地或不连续地形成在至少一个伪结构14与有源区域11之间。密封环结构15可以保护对应的有源区域11以防止外部环境的影响。伪结构14可以是牺牲密封环结构，以保护内部的密封环结构15防止在切割操作期间出现裂缝所造成的损害。伪结构14和密封环结构15在结构或材料上可以类似或不同。
整个密封环结构15可以由相同的材料或不同的材料形成。密封环结构15包括金属组件，该金属组件由金属线151和导电通孔152形成。金属线151和导电通孔152形成在介电层中。金属线151和导电通孔152可以是互连的。可以在不同层中形成金属线151。可以通过至少一个导电通孔152连接两个相邻层的金属线151。密封环结构15可以由任何合适的材料形成，或者由铜、铝、钛、钨、多晶硅、硅、硅化物中的至少一种材料和它们的组合或合金形成。至少一部分导电通孔152是垂直对齐的。在一些实施例中，不同层之间的至少一组通孔152连接，以形成垂直定向的圆柱，从而进一步地加强芯片区域10的强度。
伪结构14可以由相同的材料或不同的材料形成。伪结构14可以包括金属组件。在一些实施例中，金属组件包括导电通孔142。在一些实施例中，金属组件包括导电通孔142和与至少一部分导电通孔142互连的金属线141。可以在不同层中形成金属线141。可以通过至少一个导电通孔142连接相邻层的两条金属线141。至少一部分导电通孔142是垂直对齐的。不同层之间的至少一组导电通孔142用于形成圆柱。在一些实施例中，圆柱可以不连接至金属线141。伪结构14可以由任何合适的材料形成，或者由铜、铝、钛、钨、多晶硅、硅、硅化物中的至少一种材料和它们的组合或合金形成。
在一些实施例中，至少一个结构14或15包括密封环结构15和伪结构14。密封环结构15可以是类似的或不同的。伪结构14可以是类似的或不同的。密封环结构15可以是分离的或连接的。伪结构14可以是分离的或连接的。相邻的密封环结构15和伪结构14可以是分离的或连接的。
如图2所示，在一些实施例中，衬底1包括层间介电层16和块状硅17。在块状硅17上方形成层间介电层16，并且在层间介电层16上方形成伪结构14和密封环结构15。在一些实施例中，在层间介电层16中形成至少一个导电通孔143，并且该导电通孔将伪结构14与块状硅17连接。在一些实施例中，伪结构14的圆柱连接至层间介电层16中的导电通孔143。在一些实施例中，层间介电层16上的金属线141连接至导电通孔143。
参考图1，在一些实施例中，可以在衬底1中和对应的划线12内形成PCM(工艺控制监控)测试结构18。可以去除PCM测试结构18上方的钝化层111，以允许用于测试的外部访问。
参考图1，在钝化层111上和每一个芯片区域10上方形成介电层20，该介电层20被图案化为具有开口，以暴露对应的接触焊盘112。UBM(Under Bump Metallurgies，凸块下金属化层)提供附着层、扩散阻挡层或焊料润湿层，该UBM设置为与介电层20的开口相对应。每一个UBM都与对应的接触焊盘112接触，并且延伸至围绕对应的开口的介电层20的区域的上方。将凸块材料19设置在UBM上方，并且可以通过回流工艺将凸块材料19变成球形，或者凸块材料19包括焊球，其中，通过模板掩模的开口将该凸块材料相应地设置在UBM上，然后通过回流工艺将该凸块材料与UBM接合。在一些实施例中，介电层20是聚合物，该聚合物可以包括苯并环丁烯(BCB)、聚苯并恶唑(PBO)、聚酰亚胺(PI)或环氧树脂。在一些实施例中，UBM包括以下材料中的至少一层：钯、钼、钛、氮化钛、钽、氮化钽、铬、钨、钒、铜、铝、银、金或镍，但不限于上述材料。在一些实施例中，凸块材料19包括无铅预焊层、SnAg或包括锡、铅、银、铜、镍、铋或它们的组合的合金的焊接材料。
如图1所示，在划线12上方设置缓冲层21。缓冲层21可以覆盖划线12。缓冲层21可以在芯片区域10的外围的上方延伸。当芯片区域10包括至少一个保护结构时，缓冲层21可以在保护结构区域13的上方延伸。缓冲层21可以覆盖保护结构区域13的至少一部分。在一些实施例中，每一个芯片区域10的区域13都包括一个密封环结构15和一个伪结构14。该伪结构14位于该密封环结构15与对应的划线12之间，并且该伪结构14位于缓冲层21的下面。在一些实施例中，每一个芯片区域10的区域13都包括多个密封环结构15和多个伪结构14。该多个伪结构14位于该多个密封环结构15与对应的划线12之间，并且该多个伪结构14还位于缓冲层21的下面。在一些实施例中，每一个芯片区域10的区域13都包括多个密封环结构15和多个伪结构14。该多个伪结构14位于该多个密封环结构15与对应的划线12之间，并且一个密封环15的至少一部分和多个伪结构14位于缓冲层21的下面。
在一些实施例中，在有源区域11上方形成介电层20，并且介电层20包括延伸至通过间隙200与对应的缓冲层21分离的位置处的至少一部分。在一些实施例中，间隙200在5um至20um的范围内。在其他的实施例中，介电层20连接至缓冲层21。
在一些实施例中，在有源区域11上方同时形成缓冲层21和介电层20，然后通过间隙200将缓冲层21与介电层20分离，该间隙200在5um至20um的范围内。
在一些实施例中，介电层20形成在有源区域11上方以及保护结构区域13的一部分上方，并且通过间隙200将该介电层20与缓冲层21分离，该间隙200在5um至20um的范围内。
将缓冲层21与至少在有源区域11上方的介电层20分离的间隙200可以作为裂缝停止部(crack stop)，使得裂缝不会被传播到介电层20中。
在一些实施例中，介电层20和缓冲层21具有相同的材料。在一些实施例中，介电层20和缓冲层21具有不同的材料。
参考图1，在衬底1上方形成模具22，以为有源区域11提供保护。模具22可以由粉末形式或流体形式的模塑料形成。在一些实施例中，模塑料包括环氧树脂，但不限于上述材料。
缓冲层21设置在模具22和衬底1之间，并且缓冲层21用于减少从模具22施加到衬底1上的压力的缓冲，使得在切割衬底1时，防止通过碎裂而引起的裂缝的出现。缓冲层21可以是聚合物。缓冲层21可以是环氧树脂。在一些实施例中，缓冲层21比模具22软。在一些实施例中，缓冲层21具有的弹性模量小于模具22的弹性模量。在一些实施例中，缓冲层21包括聚苯并恶唑。
缓冲层21还可以用作缓冲，以减轻由模具22和衬底1的钝化层111或衬底1的钝化层111的子层的热膨胀系数之间的显著偏差而引起的压力。在一些实施例中，缓冲层21的热膨胀系数小于模具22的热膨胀系数。在一些实施例中，缓冲层21的热膨胀系数介于模具22的热膨胀系数和衬底1的钝化层111或衬底1的钝化层111的子层的热膨胀系数之间。在一些实施例中，钝化层111的子层包括氮化硅。在一些实施例中，钝化层111的子层包括USG。
缓冲层21包括允许缓冲层21用作缓冲的厚度，以减轻从模具22施加到衬底1上的压力。在一些实施例中，缓冲层21的厚度在5um至20um的范围内。在一些实施例中，缓冲层21和介电层20一起形成，使得缓冲层21的厚度与介电层20的厚度类似。在一些实施例中，缓冲层21的厚度不同于介电层20的厚度。
参考图1和图2，在切割操作期间，沿着划线12应用切割工具，以产生多个半导体器件3和半导体器件3的分离侧壁31。每一个切下来的半导体器件3都包括与衬底1分离的芯片衬底1c、与模具22分离的模具22c和与缓冲层21分离的缓冲层21c。由于切割工具切割模具22、缓冲层21和衬底1，随后，分离侧壁31示出由芯片衬底1c、模具22c和缓冲层21c形成的分层结构，其中缓冲层21c从外部嵌入芯片衬底1c和模具22c之间。
在一些实施例中，芯片衬底1c包括芯片衬底1c的顶部上的钝化层111c。在钝化层111c上方或直接在钝化层111c上形成缓冲层21c。在一些实施例中，钝化层111c包括以下材料中的至少一层：氧化硅、氮化硅、氮氧化硅和未掺杂的硅酸盐玻璃。在一些实施例中，芯片衬底1c包括表面114，在表面114上形成钝化层111c，并且在表面114上方形成缓冲层21c。在一些实施例中，缓冲层21c部分地与表面114接触。
在一些实施例中，芯片衬底1c包括至少一个接触焊盘112上方的钝化层111c和在切割工艺期间产生的分离侧壁31。钝化层111c包括连接至分离侧壁31的表面1111。缓冲层21c形成在钝化层111c的表面1111上以及芯片衬底1c与模具22c之间，缓冲层21c延伸至分离侧壁31，并且缓冲层21c暴露到半导体器件3的外部。
在一些实施例中，芯片衬底1c包括分离侧壁31。模具22c包括分离侧壁221。在切割工艺期间产生芯片衬底1c的侧壁31和模具22c的侧壁221。缓冲层21c形成在芯片衬底1c和模具22c之间，并且缓冲层21c将模具22c的侧壁221与芯片衬底1c的侧壁31分离。
在一些实施例中，通过使用两步切割工艺来分离半导体器件3，使得半导体器件3的侧壁31具有两个基本垂直的切割面。在一些实施例中，通过单步切割工艺来分离半导体器件3。
图3是根据实施例的另一个半导体器件3a的截面图。
半导体器件3a包括芯片衬底1c、芯片衬底1c上方的模具22c和介于芯片衬底1c与模具22c之间的缓冲层21c。缓冲层21c暴露到半导体器件3a的外部。在一些实施例中，缓冲层21c具有的弹性模量比模具22c的弹性模量小。在一些实施例中，缓冲层21c具有的热膨胀系数比模具22c的热膨胀系数小。在一些实施例中，缓冲层21c的热膨胀系数介于模具22c的热膨胀系数和芯片衬底1c的钝化层111c或芯片衬底1c的钝化层111c的子层的热膨胀系数之间。
半导体器件3a包括再分布结构32，该再分布结构用于将接触焊盘112连接至不同位置的凸块材料。在一些实施例中，如图3所示，再分布结构32包括介电层321和至少一个钝化后衬里322。在芯片衬底1c的上方形成介电层321，并且介电层321部分地覆盖芯片衬底1c的至少一个接触焊盘112。钝化后衬里322形成在介电层321上方，并且将对应的接触焊盘112与凸块材料连接。在一些实施例中，介电层321和缓冲层21c由相同的材料形成。在一些实施例中，介电层321和缓冲层21c由不同的材料形成。在一些实施例中，介电层321的厚度在5um至15um的范围内，并且缓冲层21c的厚度在5um至20um的范围内。在一些实施例中，介电层321的一部分延伸至通过间隙200远离缓冲层21c的位置处，该间隙200在5um至20um的范围内。在一些实施例中，介电层321具有芯片衬底1c的区域13的边缘，并且该边缘通过间隙200与缓冲层21c的相邻部分分离，该间隙200在5um至20um的范围内。
在一些实施例中，半导体器件3a包括再分布结构32，再分布结构32包括芯片衬底1c上的介电层321、位于介电层321上并且连接至对应的接触焊盘112的至少一个钝化后衬里322和钝化后衬里322上方的另一层介电层323。在一些实施例中，介电层323由与缓冲层21c的材料相同的材料形成。在一些实施例中，介电层323由与缓冲层21c的材料不同的材料形成。在一些实施例中，介电层323的厚度在5um至20um的范围内，并且缓冲层21c的厚度在5um至15um的范围内。
在一些实施例中，芯片衬底1c包括保护结构区域，并且介电层321和/或缓冲层21c延伸至保护结构区域上。在一些实施例中，半导体器件3a包括一个密封环结构15和一个伪结构14，其中介电层321延伸至该密封环结构15的上方，并且缓冲层21c延伸至该伪结构14的上方。在一些实施例中，半导体器件3a包括多个密封环结构15和多个伪结构14，其中介电层321部分延伸至一个密封环结构15的上方，并且缓冲层21c延伸至该伪结构14的上方。在一些实施例中，半导体器件3a包括多个密封环结构15和多个伪结构14，其中介电层321部分延伸至一个密封环结构15的上方，并且缓冲层21c延伸至伪结构14的上方，并且缓冲层21c至少部分延伸至一个密封环结构15的上方。
图4是根据一些实施例的涉及制造半导体器件的方法的流程图。
参考图1和图4，在步骤401中，接收衬底1。衬底1包括至少一个芯片区域10和邻近至少一个芯片区域10的至少一条划线12。在一些实施例中，衬底1包括多个芯片区域10，该多个芯片区域被布置为网格图案的多条划线12分离。在一些实施例中，网格图案是正交的网格图案。在一些实施例中，每一个芯片区域10都包括有源区域11，并且每一个芯片区域10还可以包括保护结构区域13。衬底1包括钝化层111，并且每一个芯片区域10都包括至少一个接触焊盘112。钝化层111形成为衬底1的顶部，并且形成在每一个芯片区域10的接触焊盘112上方，以及钝化层111包括用于每一个芯片区域10的至少一个开口113，以暴露对应的接触焊盘。
参考图1和图4，在步骤403中，在衬底1上方设置缓冲层21并且图案化缓冲层21，以至少覆盖划线12。缓冲层21可以覆盖划线12中的钝化层111，并且例如，为了暴露诸如PCM测试结构的器件，去除钝化层111在划线12之间的部分区域。通过包括(但不限于)旋涂工艺的任何合适的方法来设置缓冲层21，并且通过包括(但不限于)光刻工艺的任何合适的方法来图案化缓冲层21。
在一些实施例中，每一条划线12上方的缓冲层21至少延伸到相邻的芯片区域10。在一些实施例中，每一个芯片区域10包括围绕有源区域11的保护结构区域13，并且缓冲层21至少部分地覆盖每一个芯片区域10的区域13。在一些实施例中，每一个芯片区域10的区域13包括至少一个密封环结构14或15，并且至少一个密封环结构14或15至少部分地位于缓冲层21的下面。在一些实施例中，每一个芯片区域10的区域13包括多个密封环结构14和15，并且多个密封环结构14和15的一部分位于缓冲层21的下面。在一些实施例中，每一个芯片区域10的区域13包括至少一个伪结构14和至少一个密封环结构15，并且至少伪结构14位于缓冲层21的下面。在一些实施例中，每一个芯片区域10的区域13包括多个伪结构14和多个密封环结构15，并且该多个伪结构14位于缓冲层21的下面，以及一个密封环结构15至少部分地位于缓冲层21的下面。
参考图1和图4，在步骤405中，介电层20设置在每一个芯片区域10的上方，并且例如，通过使用光刻工艺来图案化该介电层20。每一个芯片区域10的介电层20包括至少一个开口201，以暴露至少一个接触焊盘112。例如，可以通过旋涂工艺来设置介电层20。介电层20可以是PBO、BCB、PI、环氧树脂或光敏树脂，但不限于上述材料。在一些实施例中，同时进行或执行缓冲层21的沉积和介电层20的沉积，或在相同的操作中设置缓冲层21和介电层20。
参考图1和图4，在步骤407中，将UBM设置为对应于衬底1上方的开口201，并且将UBM电连接至接触焊盘112。可以通过顺序地沉积(如，溅射或蒸发)多金属层和通过蚀刻方法(诸如化学蚀刻)部分去除UBM堆叠件来形成UBM。也可以通过金属或光刻胶掩模选择性地将金属沉积在预期的位置上来形成UBM。
参考图1和图4，在步骤409中，凸块材料19设置在介电层20上方，并且将凸块材料19电连接至对应的有源区域11。在一些实施例中，可以通过蒸发、印刷、电镀、突出物或球凸起(ball bumping)、植球或焊料转移来设置凸块材料。在一些实施例中，然后通过回流工艺将凸块材料变成焊球。
参考图1和图4，在步骤411中，模具22设置在衬底1上方，覆盖缓冲层21，并且填充在凸块材料19之间。诸如，模具22包括液态的模塑料。
参考图1和图4，在步骤413中，沿着划线12切割衬底。切割工具顺序地切割穿过模具22、缓冲层21和衬底1。由于缓冲层21具有的弹性模量或热膨胀系数小于模具22的弹性模量或热膨胀系数，所以减小了通过切割产生的从模具22施加到衬底1上的压力。因此，可以减少切割边缘上的裂缝的出现。在一些实施例中，通过锯切切割衬底1。在一些实施例中，通过一步或两步切割工艺来切割衬底1。
图5是示出了根据一些实施例的另一个模制衬底的一部分的截面图。图6是根据一些实施例的关于制造半导体器件的方法的另一个流程图。
参考图5和图6，在步骤601中，接收衬底1。
在步骤603和605中，将介电材料设置在衬底1上方并且图案化介电材料，以形成每一个芯片区域10上的并且包括至少一个开口的介电层321以暴露接触焊盘112，并且以形成至少覆盖划线12的缓冲层21。在一些实施例中，划线12上方的缓冲层21可以延伸至相邻的芯片区域10的外围，并且缓冲层21还可以覆盖一个或多个伪结构14和一个或多个密封环结构15中的至少一个，并且该缓冲层21通过在5um至20um的范围内的间隙与相邻的芯片区域10的介电层321分离。在一些实施例中，在衬底1的表面上方形成缓冲层21，其中，在衬底1的表面上直接形成钝化层111。在一些实施例中，介电材料包括PBO、BCB、PI、环氧树脂或光敏树脂，但不限于上述材料。
在步骤607中，钝化后衬里322形成在介电层321上并且电连接至对应的接触焊盘112。在一些实施例中，钝化后衬里322包括(但不限于)铜、铝或铜合金。在一些实施例中，钝化后衬里322还可以包括含铜层顶部上的含镍层。在一些实施例中，钝化后衬里322包括附着层和附着层上的晶种层。附着层包括钛(Ti)、氮化钛(TiN)、钽(Ta)和氮化钽(TaN)中的至少一种，但不限于上述材料。可以通过物理汽相沉积(PVD)工艺来形成附着层。晶种层包括铜、铝、银、金和镍中的至少一种，但不限于上述材料。通过PVD工艺来形成晶种层。
在步骤609中，形成另一层介电层323并且覆盖在钝化后衬里322上方。在一些实施例中，介电层323包括PBO、BCB、PI、环氧树脂或光敏树脂，但不限于上述材料。
在步骤611中，凸块材料设置在衬底1上方或设置为对应于介电层323的开口以暴露对应的钝化后衬里322。在一些实施例中，在凸块材料和钝化后衬里322之间相应地形成UBM。UBM可以包括钯、钼、钛、氮化钛、钽、氮化钽、铬、钨、钒、铜、铝、银、金和镍中的至少一种，但不限于上述材料。
在步骤613中，模具22形成在衬底1上方，覆盖缓冲层21，并且填充在凸块材料之间。在一些实施例中，例如，模具22包括液态的模塑料。
在步骤615中，沿着划线12切割衬底1。切割工具顺序地切割穿过模具22、缓冲层21和衬底1，以获得多个半导体器件。在一些实施例中，通过锯切来切割衬底1。在一些实施例中，通过一步或两步切割工艺来切割衬底1。
图7是根据一些实施例的关于制造半导体器件的方法的又一个流程图。
参考图5和图7，在步骤701中，接收衬底1。
在步骤703中，在每一个芯片区域10的至少一个接触焊盘112上方形成介电层321，并且介电层321包括暴露接触焊盘112的至少一个开口113。
在步骤705中，在每一个芯片区域10的介电层321上方形成钝化后衬里322，并且钝化后衬里322通过介电层321的开口电连接至有源区域11中的对应的接触焊盘112。
在步骤707和709中，介电材料设置在衬底1上方，并且图案化介电材料，作为覆盖钝化后衬里322的介电层323和作为至少覆盖衬底1的划线的缓冲层21。缓冲层21可以延伸到芯片区域10的外围并且覆盖至少一个伪结构14和/或至少一个密封环结构15。
在步骤711中，凸块材料设置在衬底1上方或设置为对应于介电层323的开口，以暴露对应的钝化后衬里322，并且凸块材料通过介电层323相应地连接至钝化后衬里322。
在步骤713中，模具22形成在衬底1上方，覆盖缓冲层21，并且填充在凸块材料之间。
在步骤715中，沿着划线12切割衬底1。切割工具顺序地切割穿过模具22、缓冲层21和衬底1，以获得多个半导体器件。
在一些实施例中，缓冲层设置在模具和衬底之间，至少覆盖衬底的划线。缓冲层可以在切割衬底期间减少从模具到衬底的压力，从而阻止或最小化切割边缘上裂缝的出现。在一些实施例中，缓冲层不像模具那样硬。在一些实施例中，缓冲层具有的弹性模量小于模具的弹性模量。
在一些实施例中，缓冲层设置在模具和衬底之间，以至少覆盖衬底的划线。缓冲层可以缓解在模具与衬底的至少一个顶层之间的CTE(热膨胀系数)的不匹配，从而减少当切割衬底时由CTE不匹配所引起的压力。在一些实施例中，缓冲层具有的热膨胀系数小于模具的热膨胀系数。在一些实施例中，缓冲层具有的热膨胀系数介于模具的热膨胀系数和衬底的至少一个顶层的热膨胀系数之间，衬底的至少一个顶层包括氮化硅层或USG层。
在一些实施例中，缓冲层设置在模具和衬底之间，并且具有在5um至20um的范围内的厚度，以至少覆盖衬底的划线，从而减少在切割衬底期间从模具到衬底的压力。
在一些实施例中，半导体器件包括芯片衬底、模具和缓冲层。在芯片衬底上方设置模具。缓冲层从外部嵌入芯片衬底和模具之间。缓冲层具有的弹性模量小于模具的弹性模量或缓冲层的热膨胀系数小于模具的热膨胀系数。
在一些实施例中，半导体器件包括芯片衬底、模具和缓冲层。芯片衬底包括接触焊盘、分离侧壁和钝化层。在接触焊盘上方设置钝化层。钝化层包括连接至芯片衬底的分离侧壁的表面。模具设置在芯片衬底的上方并且包括分离侧壁。缓冲层设置在钝化层的表面上，并且缓冲层将模具的侧壁与芯片衬底的侧壁分离。缓冲层具有的弹性模量小于模具的弹性模量或缓冲层具有的热膨胀系数小于模具的热膨胀系数。
在一些实施例中，公开了制造半导体器件的方法。在该方法中，接收衬底。衬底包括至少一个芯片区域和邻近芯片区域的至少一条划线。每一个芯片区域包括有源区域。接下来，缓冲层设置为至少覆盖划线。然后，介电层设置在芯片区域上方。随后，凸块材料设置在介电层上并且电连接至有源区域。接下来，在衬底上方形成覆盖缓冲层的模具。缓冲层具有的弹性模量或热膨胀系数小于模具的弹性模量或热膨胀系数。然后，沿着划线切割衬底。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (18)

1.一种半导体器件，包括：
芯片衬底；
模具，位于所述芯片衬底的上方；以及
缓冲层，从外部嵌入所述芯片衬底与所述模具之间，其中，所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数，其中，所述芯片衬底包括有源区域和围绕所述有源区域的保护结构区域，所述缓冲层部分地覆盖所述保护结构区域。
2.根据权利要求1所述的半导体器件，其中，所述芯片衬底包括所述保护结构区域中的伪结构和介于所述有源区域与所述伪结构之间的密封环结构，所述缓冲层覆盖所述伪结构。
3.根据权利要求1所述的半导体器件，还包括：介电层，延伸至所述芯片衬底的有源区域和所述保护结构区域上方，其中，所述缓冲层通过间隙与所述介电层分离。
4.根据权利要求3所述的半导体器件，其中，所述间隙在5um至20um的范围内。
5.根据权利要求1所述的半导体器件，其中，所述缓冲层的厚度在5um至20um的范围内。
6.根据权利要求1所述的半导体器件，其中，所述缓冲层包括聚苯并恶唑。
7.一种半导体器件，包括：
芯片衬底，包括接触焊盘、分离侧壁和所述接触焊盘上方的钝化层，所述钝化层包括连接至所述分离侧壁的表面；
模具，位于所述芯片衬底的上方，所述模具包括分离侧壁；以及
缓冲层，位于所述钝化层的表面上，其中，所述缓冲层将所述模具的侧壁与所述芯片衬底的侧壁分离，并且所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数，其中，所述芯片衬底包括有源区域和围绕所述有源区域的保护结构区域，所述缓冲层部分地覆盖所述保护结构区域。
8.根据权利要求7所述的半导体器件，其中，所述芯片衬底包括所述保护结构区域中的伪结构和介于所述有源区域与所述伪结构之间的密封环结构，所述缓冲层覆盖所述伪结构。
9.根据权利要求7所述的半导体器件，还包括：介电层，延伸至所述芯片衬底的有源区域和所述保护结构区域上方，其中，所述缓冲层通过间隙与所述介电层分离。
10.根据权利要求9所述的半导体器件，其中，所述间隙在5um至20um的范围内。
11.根据权利要求7所述的半导体器件，其中，所述缓冲层的厚度在5um至20um的范围内。
12.根据权利要求7所述的半导体器件，其中，所述缓冲层包括聚苯并恶唑。
13.一种制造半导体器件的方法，包括：
接收衬底，其中，所述衬底包括至少一个芯片区域和邻近所述芯片区域的至少一条划线，并且每一个芯片区域都包括有源区域；
设置至少覆盖所述划线的缓冲层；
在所述每一个芯片区域上方设置包括开口的介电层；
将凸块材料设置到所述介电层的开口上，并且将所述凸块材料电连接至所述有源区域；
在所述衬底上方形成模具，并且所述模具覆盖所述缓冲层，其中，所述缓冲层的弹性模量小于所述模具的弹性模量，或所述缓冲层的热膨胀系数小于所述模具的热膨胀系数；以及
沿着所述划线切割所述衬底。
14.根据权利要求13所述的制造半导体器件的方法，其中，每一个芯片区域都包括保护结构区域，并且所述缓冲层部分覆盖所述保护结构区域。
15.根据权利要求13所述的制造半导体器件的方法，其中，设置缓冲层与设置介电层同时进行。
16.根据权利要求13所述的制造半导体器件的方法，其中，所述介电层通过在5um至20um的范围内的间隙远离所述缓冲层。
17.根据权利要求13所述的制造半导体器件的方法，还包括：在所述介电层上形成钝化后衬里，以将所述凸块材料与所述有源区域连接，并且在所述钝化后衬里上方设置另一层介电层。
18.根据权利要求17所述的制造半导体器件的方法，其中，设置另一层介电层与所述设置缓冲层同时进行。
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