CN105047713A - 隧道场效应晶体管及其制造方法 - Google Patents

隧道场效应晶体管及其制造方法 Download PDF

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CN105047713A
CN105047713A CN201510136532.2A CN201510136532A CN105047713A CN 105047713 A CN105047713 A CN 105047713A CN 201510136532 A CN201510136532 A CN 201510136532A CN 105047713 A CN105047713 A CN 105047713A
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type
layer
channel region
effect transistor
drain region
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CN105047713B (zh
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蔡腾群
王立廷
林正堂
陈德芳
彭治棠
王建勋
林宏达
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种隧道场效应晶体管及其制造方法。隧道场效应晶体管包括漏极区、与漏极区具有相反的导电类型的源极区、设置在漏极区和源极区之间的沟道区、设置在沟道区周围的金属栅极层、以及设置在金属栅极层和沟道区之间的高k介电层。

Description

隧道场效应晶体管及其制造方法
相关申请的交叉引用
本申请要求2014年4月30日提交的美国临时申请第61/986,663号的优先权，其全部内容结合于此作为参考。
技术领域
本发明涉及隧道场效应晶体管及其制造方法。
背景技术
金属氧化物半导体(MOS)技术已被广泛使用。MOS器件可以在包括线性区域、饱和区域和亚阀值区域的三个区域中工作，取决于栅极电压Vg和源极-漏极电压Vds。亚阀值区域是其中电压Vg小于阀值电压Vt的区域。被称为亚阀值摆幅(SS)的参数表示切断晶体管电流的容易度(easiness),并且是确定MOS器件的速度的因素。亚阀值摆幅可以表达为m×kT/q的函数，其中m是与电容相关的参数，k是玻尔兹曼常数，T是绝对温度，以及q是电子上的电荷的数量。以前的研究已经揭示典型的MOS器件的亚阀值摆幅在室温下具有约60mV/十进位的限制，其又设定对操作电压VDD和阀值电压Vt的进一步缩放的限制。这种限制是由于载流子的扩散传输机制。由于这个原因，典型地，现有的MOS器件在室温下不能比60mV/十进位更地转换。
发明内容
为了解决现有技术中的问题，本发明提供了一种隧道场效应晶体管，包括：漏极区；源极区，其中，所述漏极区和所述源极区是相反的导电类型；沟道区，设置在所述漏极区和所述源极区之间；金属栅极层，设置在所述沟道区周围；以及高k介电层，设置在所述金属栅极层和所述沟道区之间。
在上述隧道场效应晶体管中，其中，所述漏极区、所述源极区和所述沟道区基本上垂直地堆叠。
在上述隧道场效应晶体管中，其中，所述漏极区、所述源极区和所述沟道区基本上垂直地堆叠；其中，所述源极区的掺杂浓度大于所述漏极区的掺杂浓度。
在上述隧道场效应晶体管中，其中，所述源极区、所述漏极区和所述沟道区中的至少一个具有梯度掺杂浓度。
在上述隧道场效应晶体管中，还包括：侧壁间隔件，设置在所述源极区周围；绝缘层，设置在至少所述侧壁间隔件周围，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成，并且，所述绝缘层中具有至少一个开口以暴露所述金属栅极层；以及栅极接触件，通过所述开口连接至所述金属栅极层，其中，所述侧壁间隔件设置在所述栅极接触件和所述源极区之间。
在上述隧道场效应晶体管中，还包括：侧壁间隔件，设置在所述源极区周围；绝缘层，设置在至少所述侧壁间隔件周围，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成，并且，所述绝缘层中具有至少一个开口以暴露所述金属栅极层；以及栅极接触件，通过所述开口连接至所述金属栅极层，其中，所述侧壁间隔件设置在所述栅极接触件和所述源极区之间；其中，在所述侧壁间隔件之上的所述栅极接触件的截面面积大于在所述侧壁间隔件之下的所述栅极接触件的截面面积。
根据本发明的另一个方面，提供了一种隧道场效应晶体管组件，包括：衬底，具有第一类型阱、第二类型阱和将所述第一类型阱和所述第二类型阱分隔开的浅沟槽隔离部件；第一类型隧道场效应晶体管，设置在所述第二类型阱上，所述第一类型隧道场效应晶体管包括：第一类型漏极区；第二类型源极区；第一类型沟道区，设置在所述第一类型漏极区和所述第二类型源极区之间；第一金属栅极层，设置在所述第一类型沟道区周围；和第一高k介电层，设置在所述第一金属栅极层和所述第一类型沟道区之间；以及第二类型隧道场效应晶体管，设置在所述第一类型阱上，所述第二类型隧道场效应晶体管包括：第二类型漏极区；第一类型源极区；第二类型沟道区，设置在所述第二类型漏极区和所述第一类型源极区之间；第二金属栅极层，设置在所述第二类型沟道区周围；和第二高k介电层，设置在所述第二金属栅极层和所述第二类型沟道区之间。
在上述隧道场效应晶体管组件中，其中，所述第一类型漏极区、所述第二类型源极区和所述第一类型沟道区基本上垂直地堆叠。
在上述隧道场效应晶体管组件中，其中，所述第二类型漏极区、所述第一类型源极区和所述第二类型沟道区基本上垂直地堆叠。
在上述隧道场效应晶体管组件中，其中，所述第一类型源极区的掺杂浓度大于所述第二类型漏极区的掺杂浓度。
在上述隧道场效应晶体管组件中，其中，所述第二类型源极区的掺杂浓度大于所述第一类型漏极区的掺杂浓度。
在上述隧道场效应晶体管组件中，其中，所述第一类型源极区、所述第一类型漏极区、所述第一类型沟道区、所述第二类型源极区、所述第二类型漏极区以及所述第二类型沟道区中的至少一个具有梯度掺杂浓度。
在上述隧道场效应晶体管组件中，还包括：硅化物区，形成在所述第一类型源极区和所述第二类型源极区上；以及多个侧壁间隔件，分别设置在所述第一类型源极区和所述第二类型源极区周围，并且设置在所述硅化物区和所述金属栅极层之间。
根据本发明的又一个方面，提供了一种用于制造隧道场效应晶体管的方法，包括：在衬底上形成半导体线结构，其中，所述半导体线结构包括在所述衬底上形成的底部源极或漏极区、在所述底部源极或漏极区上形成的沟道区，并且在所述沟道区上形成的顶部源极或漏极区；在所述沟道区周围形成高k介电层；以及在所述高k介电层周围形成金属栅极层。
在上述用于制造隧道场效应晶体管的方法中，还包括：在所述底部源极或漏极区上形成底部硅化物区。
在上述用于制造隧道场效应晶体管的方法中，还包括：在所述顶部源极或漏极区上形成顶部硅化物区。
在上述用于制造隧道场效应晶体管的方法中，还包括：在所述顶部源极或漏极区周围形成侧壁间隔件；在所述衬底上方并且至少在所述侧壁间隔件周围形成绝缘层，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成；在蚀刻工艺中在所述绝缘层中形成至少一个开口以暴露所述金属栅极层，所述蚀刻工艺蚀刻所述绝缘层的速率大于蚀刻所述侧壁间隔件的速率，从而使得在所述蚀刻工艺期间保护所述顶部源极或漏极区；以及用导电材料填充所述开口。
在上述用于制造隧道场效应晶体管的方法中，，还包括：在所述顶部源极或漏极区周围形成侧壁间隔件；在所述衬底上方并且至少在所述侧壁间隔件周围形成绝缘层，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成；在蚀刻工艺中在所述绝缘层中形成至少一个开口以暴露所述底部源极或漏极区，所述蚀刻工艺蚀刻所述绝缘层的速率大于蚀刻所述侧壁间隔件的速率，从而使得在所述蚀刻工艺期间保护所述顶部源极或漏极区；以及用导电材料填充所述开口。
在上述用于制造隧道场效应晶体管的方法中，还包括：在所述顶部源极或漏极区周围形成侧壁间隔件；在所述衬底上方并且至少在所述侧壁间隔件周围形成绝缘层，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成；以及在所述绝缘层中形成至少一个开口以暴露所述金属栅极层，在所述侧壁间隔件之上的所述开口的截面面积大于在所述侧壁间隔件之下的所述开口的截面面积。
在上述用于制造隧道场效应晶体管的方法中，其中，形成所述半导体线结构包括：在所述衬底上形成至少一个线主体；以及对所述线主体实施一系列的注入工艺以形成底部源极或漏极区、沟道区和顶部源极或漏极区。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图50是根据一些实施例的用于制造隧道场效应晶体管组件的方法的不同步骤的截面图。
图51至图108是根据一些实施例的用于制造隧道场效应晶体管组件的方法的不同步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的许多不同的实施例或实例。下面描述了组件和布置的具体实例以简化本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
在以下描述中提供了具有一个或多个隧道场效应晶体管的隧道场效应晶体管组件及其制造方法。隧道场效应晶体管包括高k金属栅极结构并且因此对短沟道效应具有抗干扰性。
参照图1至图50，其是根据一些实施例的在方法的各个制造步骤期间的用于制造部分或全部的隧道场效应晶体管组件的方法的不同步骤的截面图。应当理解，对于方法的额外的实施例，在方法之前、期间或之后可以提供额外的步骤，并且可以替代或消除以下描述的一些步骤。进一步地理解，对于隧道场效应晶体管组件的额外的实施例，额外的部件可以添加到隧道场效应晶体管组件中，并且可以替代或消除以下描述的一些部件。
参照图1，在衬底100上形成硬掩模层102。衬底100是半导体衬底。例如，衬底100由硅；诸如碳化硅、砷化铟或磷化铟的化合物半导体；或诸如碳化硅锗、磷砷化镓或磷化镓铟的合金半导体制成。例如，硬掩模层102由氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)制成。
参照图2，形成沟槽104。为了形成沟槽104，在衬底100上形成掩模层106。掩模层106是光刻胶层。通过光刻工艺图案化掩模层106以在硬掩模层102上形成多个部件和由部件限定的多个开口。根据预定的集成电路图案形成掩模层106的图案。光刻胶工艺可以包括光刻胶涂覆、曝光、曝光后烘烤和显影。然后实施蚀刻工艺以形成沟槽104。蚀刻工艺是在开口处具有约1:10以及在沟槽底部具有约1:3至1:4的氮化物或氮氧化物与氧化物的选择性的干蚀刻工艺。在这个步骤之后去除掩模层106。
参照图3，浅沟槽隔离(STI)电介质108填充在沟槽104中。例如，STI电介质108由氧化物制成。STI电介质108的部分沉积在硬掩模层102上。
参照图4，例如，通过在硬掩模层102处具有抛光停止的化学机械抛光(CMP)来抛光STI电介质108。
参照图5，通过干蚀刻工艺蚀刻STI电介质108。
参照图6，在衬底100上形成阻挡和抗反射涂(BARC)层110。BARC层110的厚度在从约100埃至约500埃的范围内。例如，BARC层110由氮氧化硅或有机材料制成。可以通过沉积工艺形成BARC层110，并且可选地抛光BARC层110。在BARC层110上形成另一掩模层112。
参照图7，通过光刻工艺图案化掩模层112以在BARC层110上形成多个部件以及通过部件限定的多个开口。
参照图8，例如，通过干蚀刻工艺蚀刻通过图案化的掩模层112暴露的BARC层110、硬掩模层102和衬底100的部分。因此，在衬底100上形成多个半导体线结构。在一些实施例中，干蚀刻工艺停止在STI电介质108的顶部，并且因此在干蚀刻工艺之后暴露STI电介质108。
参照图9，从图8中所示的结构中去除掩模层112和BARC层110。可以通过湿蚀刻工艺或干蚀刻工艺去除掩模层112和BARC层110。对衬底100进行退火。在退火工艺中，将诸如氢气的高温气体提供至工艺室内，在工艺室内退火衬底100。在一些实施例中，氧化半导体线结构114，并且通过剥离来去除其氧化物以减薄半导体线结构114。图10中示出了退火工艺之后的衬底100的斜视图，其中半导体线结构114基本上垂直地设置在衬底100上。
参照图11，在衬底100上形成BARC层116，并且用BARC层116填充半导体线结构114之间的间隙。抛光或回蚀刻BARC层116以暴露设置在半导体线结构114上的硬掩模层102。然后，在BARC层116上形成诸如光刻胶层的掩模层118。通过光刻工艺图案化掩模层118以在BARC层116上形成部件和通过部件限定的开口，并且通过掩模层118暴露位于沟槽104的一侧的BARC层116的部分。
参照图12，例如，通过湿蚀刻工艺去除通过掩模层118暴露的BARC层116的部分。从BARC层116、掩模层118和硬掩模层102暴露的衬底100的部分掺杂有P型或N型掺杂剂以形成P阱或N阱。在一些实施例中，衬底100的部分掺杂有N型掺杂剂，诸如P、As、Si、Ge、C、O、S、Se、Te或Sb以在沟槽104的一侧形成N阱120。在这个步骤之后，去除掩模层118和BARC层116。
参照图13，在去除掩模层和BARC层之后，可选地退火N阱120。退火工艺包括快速热退火(RTA)、激光退火工艺或其他合适的退火工艺。另外，一些实施例可以包括具有很短持续时间的“尖峰”退火工艺。
参照图14，在衬底100上形成BARC层122，并且用BARC层122填充半导体线结构114之间的间隙。抛光或回蚀刻BARC层122以暴露设置在半导体线结构114上的硬掩模层102。诸如光刻胶层的掩模层124设置在BARC层122上。通过光刻工艺图案化掩模层124以在BARC层122上形成部件和通过部件限定的开口，并且通过掩模层124暴露在沟槽104的另一侧的BARC层122的部分。
参照图15，例如，通过湿蚀刻工艺蚀刻通过掩模层124暴露的BARC层122的部分。从BARC层122、掩模层124和硬掩模层102暴露的衬底100的部分掺杂有P型或N型掺杂剂以形成P阱或N阱。在一些实施例中，衬底100的部分掺杂有P型掺杂剂，诸如B、BF2、Si、Ge、C、ZN、Cd、Be、Mg或In以形成P阱126。在这个步骤之后，去除BARC层122和掩模层124。
参照图16，类似地，可选地退火P阱126。N阱120和P阱126形成在沟槽104的相对两侧上，并且半导体线结构114分别设置在N阱120和P阱126上。
参照图17，在衬底100上形成BARC层128和掩模层130，并且图案化BARC层128和掩模层130以暴露P阱126和在P阱126上的半导体线结构114。实施N型注入以在P阱126上形成N型漏极区132。通过N型注入将N型掺杂剂基本上垂直地掺杂至衬底100内。同样地，可选地退火N型漏极区132。在退火工艺期间N型掺杂剂的一些可以扩散至半导体线结构114的底部。因此，半导体线结构114的底部可以认为是N型漏极区132的部分。
参照图18，以N型掺杂剂轻掺杂位于N型漏极区132上的半导体线结构114。因此，N型沟道区134在N型漏极区132上形成。N型沟道区134的掺杂浓度小于N型漏极区132的掺杂浓度。因为硬掩模层102覆盖半导体线结构114的顶面，因此通过半导体线结构114的侧面将N型掺杂剂掺杂至半导体线结构114内。也就是，N型掺杂剂倾斜地掺杂至半导体线结构114内。在这个步骤之后，如图19所示，去除BARC层128和掩模层130。同样，可以可选地退火N型沟道区134。
参照图20，在衬底100上形成BARC层136和掩模层138，并且图案化BARC层136和掩模层138以暴露N阱120和在N阱120上的半导体线结构114。实施P型注入以在N阱120上形成P型漏极区140。通过P型注入将P型掺杂剂基本上垂直地掺杂至衬底100内。同样，可选地退火P型漏极区140。在退火工艺期间P型掺杂剂的一些可以扩散至半导体线结构114的底部。因此，半导体线结构114的底部可以认为是P型漏极区140的部分。
参照图21，以P型掺杂剂轻掺杂位于P型漏极区140上的半导体线结构114。因此，在P型漏极区140上形成P型沟道区142。P型沟道区142的掺杂浓度小于P型漏极区140的掺杂浓度。因为硬掩模层102覆盖半导体线结构114的顶面，因此通过半导体线结构114的侧面将P型掺杂剂掺杂至半导体线结构114内。也就是，P型掺杂剂倾斜地掺杂至半导体线结构114内。在这个步骤之后，如图22所示，去除BARC层136和掩模层138。同样，可以可选地退火P型沟道区142。
参照图23，在衬底100上形成绝缘层144，并且抛光绝缘层144直到其达到硬掩模层102。用绝缘层144填充半导体线结构114之间的间隙。可以通过沉积工艺形成绝缘层144。绝缘层144由诸如氧化硅或氮化硅的介电材料或绝缘材料制成。
参照图24，例如，通过剥离工艺去除硬掩模层102(见图23)。因此，多个开口146形成在绝缘层144中，并且通过绝缘层144暴露半导体线结构114的顶部。
参照图25，在绝缘层144上形成掩模层148。图案化掩模层148，并且去除设置在P阱126之上的掩模层148的部分。掩模层148可以是光刻胶层，并且可以通过光刻工艺图案化掩模层148。通过掩模层148暴露设置在P阱上的半导体线结构114。然后，对半导体线结构114实施P型注入以在N型沟道区134上形成P型源极区150。P型掺杂剂通过半导体线结构114的顶面进入半导体线结构114。N型漏极区132、N型沟道区134以及P型源极区150基本上垂直地堆叠。P型源极区150的掺杂浓度大于N型漏极区132的掺杂浓度，从而使得电流可以更容易地通过N型沟道区134。P型源极区150和/或N型漏极区132具有在从约1×1018原子/立方厘米至约1×1022原子/立方厘米的范围内的掺杂浓度。N型沟道区134具有在从约1×1012原子/立方厘米至约1×1018原子/立方厘米的范围内的掺杂浓度。在形成P型源极区150之后，去除掩模层148。
参照图26，在绝缘层144上形成掩模层162。图案化掩模层162，并且去除设置在N阱120之上的掩模层162的部分。掩模层162可以是光刻胶层，并且可以通过光刻工艺图案化掩模层162。通过掩模层162暴露设置在N阱120上的半导体线结构114。然后，对半导体线结构114上实施N型注入以在P型沟道区142上形成N型源极区164。N型掺杂剂通过半导体线结构114的顶面进入半导体线结构114。P型漏极区140、P型沟道区142以及N型源极区164基本上垂直地堆叠。N型源极区164的掺杂浓度大于P型漏极区140的掺杂浓度，从而使得电流可以更容易地通过P型沟道区142。N型源极区164和/或P型漏极区140具有在从约1×1018原子/立方厘米至约1×1022原子/立方厘米的范围内的掺杂浓度。P型沟道区142具有在从约1×1012原子/立方厘米至约1×1018原子/立方厘米的范围内的掺杂浓度。在形成N型源极区164之后，去除掩模层162。
参照图27，实施一个或多个退火工艺以扩散或活化源极和漏极区。因为通过注入工艺形成源极区、沟道区和漏极区，以便源极区、沟道区和漏极区中的至少一个具有梯度掺杂浓度。
在实施一个或多个退火工艺之后，如图28所示去除绝缘层144。例如，通过湿蚀刻工艺去除绝缘层144。
参照图29，在衬底100上形成间隔件层172。例如，通过沉积工艺形成间隔件层172。例如，间隔件层172由氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)制成。
参照图30，通过干蚀刻工艺图案化间隔件层172以暴露衬底100和半导体线结构114。
参照图31，在衬底100上形成金属层174。在一些实施例中，金属层174沉积在衬底100上。例如，金属层174由Ti、Co、Ni、NiCo、Pt、NiPt、Er或Yb制成。在一些实施例中，在金属层174上可选地形成覆盖层。例如，覆盖层由氮化钛制成。
参照图32，在硅化工艺中实施一个或多个退火工艺。衬底100的材料包括硅。因此，衬底100和半导体线结构114的与金属层接触的部分与金属层反应并在硅化工艺之后变为硅化物区176。硅化物区176在P型漏极区140、N型源极区164、N型漏极区132和P型源极区150上形成。在形成硅化物区176之后去除剩余的金属层。例如，可以通过湿剥离工艺去除剩余的金属层。同样，如图33所示，在形成硅化物区176之后去除剩余的间隔件层172。
参照图34，在衬底100上形成蚀刻停止层178，并且在蚀刻停止层178上形成绝缘层180。例如，蚀刻停止层178由氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)制成。绝缘层180由诸如氧化硅或氮化硅的介电材料绝缘材料制成。
参照图35，例如，通过CMP工艺抛光绝缘层180。抛光绝缘层180的工艺停止在蚀刻停止层178上。
参照图36，去除蚀刻停止层178和绝缘层180的部分。通过一个或多个干蚀刻工艺去除蚀刻停止层178和绝缘层180。去除在P型漏极区140和N型漏极区132之上的蚀刻停止层178和绝缘层180的部分。剩余的绝缘层180可以认为是底部绝缘层。
参照图37，在衬底100上形成高k(HK)介电层182和P型功函层184。在高k介电层182和衬底100之间可选地形成界面(IL)层。例如，界面层由氧化硅(SiO2)、HfSiO、SiON或它们的组合制成。在一些实施例中，界面层包括具有羟基基团的化学SiO2层。在界面层的表面上具有羟基基团，提高了随后生长的高k介电层182的质量。
通过原子层沉积(ALD)、化学汽相沉积(CVD)、金属有机CVD(MOCVD)、物理汽相沉积(PVD)、热氧化或它们的组合在界面层上方形成高k介电层182。例如，高k介电层182是二元或三元高k膜，诸如HfOx。可选地，高k介电层182由高k电介质制成，诸如LaO、AlO、ZrO、ZrO2、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfZrO2、HfLaO、HfSiO、LaSiO、La2O3、AlSiO、TiO2、HfTaO、HfTiO、HfO2、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物或它们的组合。
例如，P型功函层184由TiN、W、Ta、Ni、Pt、Ru、Mo、Al、WN或它们的组合制成。
参照图38，在衬底100上形成并且图案化BARC层186和掩模层188。在N阱120之上的半导体线结构114被BARC层186和掩模层188覆盖，而去除P阱126之上的BARC层186和掩模层188的部分。去除P阱126之上的P型功函层184的部分。在去除功函金属层184的部分之后，也去除BARC层186和掩模层188。
参照图39，在衬底100上形成N型功函层190。例如，N型功函层190由Ti、Ag、Al、TiAlMo、Ta、TaN、TiAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr或它们的组合制成。
参照图40，在衬底100上形成金属栅极层192。通过ALD、PVD、CVD或其他工艺在N型功函层190上沉积金属栅极层192。例如，金属栅极层192由Al、W、Co或Cu制成。
参照图41，例如，通过干蚀刻工艺去除在STI电介质108之上的金属栅极层192、N型功函层190、P型功函层184和高k介电层182的部分。干蚀刻工艺停止在底部绝缘层180上。
参照图42，在衬底100上形成绝缘层194。用绝缘层194填充半导体线结构114之间的间隙。
参照图43，例如，通过CMP工艺抛光绝缘层194。抛光绝缘层194并且抛光工艺停止在N型功函层190和P型功函层184上。
参照图44，通过干蚀刻或湿蚀刻工艺蚀刻绝缘层194。去除在STI电介质108之上的绝缘层194的部分。剩余的绝缘层194可以认为是中间绝缘层，其设置在底部绝缘层180上。中间绝缘层194和底部绝缘层180由相同的介电材料制成。中间绝缘层194的顶面与沟道区134和142的顶面基本上齐平。
参照图45，通过干蚀刻或湿蚀刻工艺去除金属栅极层192、N型功函层190、P型功函层184和高k介电层182的顶部以暴露其上的P型源极区150、N型源极区164和硅化物区176。金属栅极层192设置在N型沟道区134和P型沟道区142周围，并且高k介电层182设置在金属栅极层192和沟道区134、142之间。在这个步骤之后，形成具有垂直全环栅(VGAA)结构的N型隧道场效应晶体管160和P型隧道场效应晶体管170。
参照图46，在衬底100上形成并且抛光绝缘层196。绝缘层196的顶面高于N型隧道场效应晶体管160和P型隧道场效应晶体管170的顶面。剩余的绝缘层196可以认为是设置在中间绝缘层194上的顶部绝缘层。顶部绝缘层196、中间绝缘层194和底部绝缘层180在下文认为是绝缘层200。通过绝缘层200将N型隧道场效应晶体管160和P型隧道场效应晶体管170隔离。
参照图47，图案化绝缘层200，并且在绝缘层200中形成多个开口202。开口202分别导致位于漏极或源极区上的金属栅极层192和硅化物区176。在一些实施例中，通过干蚀刻工艺形成开口202。
参照图48，沉积导电材料204，以及用导电材料204填充开口202。例如，导电材料204由W、Co、Al或Cu制成。然后，例如，通过CMP工艺抛光导电材料204。
参照图49，在抛光导电材料204之后，在开口202中形成多个接触结构206。接触结构206中的一些连接至金属栅极层192，并且其他的接触结构206连接至硅化物区176。接触结构206通过硅化物区176连接至漏极或源极区132、140、150和164。
参照图50，分别在接触结构206上形成多个电极208以用于后续互连，诸如后段制程(BEOL)工艺。电极208包括栅电极、源电极和漏电极。例如，电极208由Cu、Co或其他金属制成。
如以上所描述，提供了包括具有高k金属栅极的一个或多个隧道场效应晶体管的隧道场效应晶体管组件。然而，可以通过其他可能的工艺制造隧道场效应晶体管，例如，在形成半导体线结构的行为之前或之后可以实施形成浅沟槽隔离的行为；在形成金属栅极结构的行为之前或之后可以实施源极注入的行为。
参照图51至图108，其示出了根据一些实施例的用于制造隧道场效应晶体管组件的方法的不同步骤的截面图。应当理解，对于方法的额外的实施例，在方法之前、期间或之后可以提供额外的步骤，并且可以替代或消除以下描述的一些步骤。进一步地理解，对于隧道场效应晶体管组件的额外的实施例，额外的部件可以添加到隧道场效应晶体管组件中，并且可以替代或消除以下描述的一些部件。
参照图51，在衬底300上形成硬掩模层302。例如，衬底300由硅；诸如碳化硅、砷化铟或磷化铟的化合物半导体；或诸如碳化硅锗、磷砷化镓或磷化镓铟的合金半导体制成。例如，硬掩模层302由氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)制成。
参照图52，在硬掩模层302上形成掩模层304。掩模层304是光刻胶层。通过光刻工艺图案化掩模层304并且在硬掩模层302上形成多个部件和由部件限定的多个开口。根据预定的集成电路图案形成掩模层304的图案。光刻工艺可以包括光刻胶涂覆、曝光、曝光后烘烤和显影。然后蚀刻硬掩模层302，并且去除通过掩模层304暴露的硬掩模层302的部分。在图案化硬掩模层302之后去除掩模层304。
参照图53，例如，通过蚀刻工艺去除通过硬掩模层302暴露的衬底300的部分。因此，在衬底300上形成多个半导体线结构306。
参照图54，退火衬底300。在退火工艺中，在退火工艺中，将诸如氢气的高温气体提供至工艺室内，在工艺室内退火衬底300。在一些实施例中，氧化半导体线结构306，并且通过剥离去除其氧化物以减薄半导体线结构306。
参照图55，在衬底300上形成阻挡和抗反射涂(BARC)层308。BARC层308的厚度在从约100埃至约500埃的范围内。BARC层308是氮氧化硅或有机材料。可以通过沉积工艺形成BARC层308，并且用BARC层308填充半导体线结构306之间的间隙。
参照图56，例如，通过在硬掩模层302处具有抛光停止的化学机械抛光(CMP)来抛光BARC层308。
参照图57，掩模层310在BARC层308上形成并且通过光刻工艺图案化。实施蚀刻工艺以在衬底300中形成沟槽312。蚀刻工艺是在开口处具有约1:10以及在沟槽底部具有约1:3至1:4的氮化物或氮氧化物与氧化物的选择性的干蚀刻工艺。在这个步骤之后进一步去除掩模层310。
参照图58，在沟槽312中填充浅沟槽隔离(STI)电介质314。例如，STI电介质314由氧化物制成。STI电介质314的部分沉积在硬掩模层302上以及BARC层308上。
参照图59，例如，通过在硬掩模层302处具有抛光停止的化学机械抛光(CMP)来抛光STI电介质314。
参照图60，用干蚀刻工艺进一步蚀刻STI电介质314。蚀刻STI电介质314至预定深度。在一些实施例中，去除半导体线结构306之间的间隙填充氧化物层314。图61示出衬底300的斜视图。多个半导体线结构306形成在衬底300上，并且沟槽312形成在半导体线结构306之间。半导体线结构306基本上垂直地设置在衬底300上。
参照图62，在衬底300上形成BARC层316，并且用BARC层316填充半导体线结构306之间的间隙。抛光或蚀刻BARC层316以暴露设置在半导体线结构306上的硬掩模层302。然后，在BARC层316上形成诸如光刻胶层的掩模层318。通过光刻工艺进一步图案化掩模层318并且在BARC层316上形成部件和通过部件限定的开口，并且通过掩模层318暴露位于沟槽312的一侧的BARC层316的部分。
参照图63，例如，通过湿蚀刻工艺去除通过掩模层318暴露的BARC层316的部分。从BARC层316、掩模层318和硬掩模层302暴露的衬底300的部分掺杂有P型或N型掺杂剂以形成P阱或N阱。在一些实施例中，衬底300的部分掺杂有N型掺杂剂，诸如P、As、Si、Ge、C、O、S、Se、Te或Sb以在沟槽312的一侧形成N阱320。在这个步骤之后，去除掩模层318和BARC层316。
参照图64，在去除掩模层和BARC层之后，可选地退火N阱320。退火工艺包括快速热退火(RTA)、激光退火工艺或其他退火工艺。
参照图65，在衬底300上形成BARC层322，并且用BARC层322填充半导体线结构306之间的间隙。抛光或蚀刻BARC层322以暴露设置在半导体线结构306上的硬掩模层302。诸如光刻胶层的掩模层324设置在BARC层322上。图案化掩模层324并且在BARC层322上形成部件和开口，并且通过掩模层324暴露BARC层322的部分。
参照图66，例如，通过湿蚀刻工艺去除通过掩模层324暴露的BARC层322的部分。以N型或P型掺杂剂掺杂从BARC层322和掩模层324暴露的衬底300的部分以形成N阱或P阱。在一些实施例中，衬底300的部分掺杂有P型掺杂剂，诸如B、BF2、Si、Ge、C、ZN、Cd、Be、Mg或In以在沟槽312的另一侧形成P阱326。在这个步骤之后，去除BARC层322和掩模层324。
参照图67，类似地，可选地退火P阱326。N阱320和P阱326在沟槽312的相对两侧上形成，并且半导体线结构306分别设置在N阱320和P阱326上。
参照图68，在衬底300上形成BARC层328和掩模层330，并且图案化BARC层328和掩模层330以暴露P阱326和设置在P阱326上的半导体线结构306，其中通过硬掩模层302覆盖半导体线结构306。实施N型注入以在P阱326上形成N型漏极区332。N型掺杂剂基本上垂直地掺杂至衬底300内。同样地，可选地退火N型漏极区332。在退火工艺期间一些N型掺杂剂可以扩散至半导体线结构306的底部内。因此，半导体线结构306的底部可以认为是N型漏极区332的部分。
参照图69，以N型掺杂剂轻掺杂在N型漏极区332上的半导体线结构306。因此，在N型漏极区332上形成N型沟道区334。N型沟道区334的掺杂浓度小于N型漏极区332的掺杂浓度。因为硬掩模层302覆盖半导体线结构306的顶面，所以通过半导体线结构306的侧面将N型掺杂剂掺杂至半导体线结构306内。也就是，N型掺杂剂倾斜地掺杂至半导体线结构306内。在这个步骤之后，如图70所示，去除设置的BARC层328和掩模层330。同样，可选地退火N型沟道区334。
参照图71，在衬底300上形成BARC层336和掩模层338，并且图案化BARC层336和掩模层338以暴露N阱320和设置在N阱320上的半导体线结构306，其中通过硬掩模层302覆盖半导体线结构306。实施P型注入以在N阱320上形成P型漏极区340。将P型掺杂剂基本上垂直地掺杂至衬底300内。同样，可选地退火P型漏极区340。在退火工艺期间P型掺杂剂的一些可以扩散至半导体线结构306的底部。因此，半导体线结构306的底部可以认为是P型漏极区340的部分。
参照图72，以P型掺杂剂轻掺杂在P型漏极区340上的半导体线结构306。因此，在P型漏极区340上形成P型沟道区342。P型沟道区342的掺杂浓度小于P型漏极区340的掺杂浓度。因为硬掩模层302覆盖半导体线结构306的顶面，所以通过半导体线结构306的侧面将P型掺杂剂掺杂至半导体线结构306内。也就是，将P型掺杂剂倾斜地掺杂至半导体线结构306内。在这个步骤之后，如图73所示，去除BARC层336和掩模层338。同样，可以可选地退火P型沟道区342。
参照图74，在衬底300上形成间隔件层344。可以通过沉积工艺形成间隔件层344。间隔件层344由诸如氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)的介电材料制成。
参照图75，例如，通过干蚀刻工艺图案化间隔件层344以暴露衬底300和半导体线结构306。在衬底300上形成金属层346。金属层346由Ti、Co、Ni、NiCo、Pt、NiPt、Er或Yb制成。在一些实施例中，在金属层346上可选地形成覆盖层。例如，覆盖层可以是氮化钛层。
参照图76，在硅化工艺中实施一个或多个退火工艺。衬底300的材料包括硅；因此，在这个工艺中衬底300的与金属层接触的部分与金属层反应并变为底部硅化物区348。底部硅化物区348在P型漏极区340和N型漏极区332上形成。在形成底部硅化物区348之后去除剩余的金属层。例如，通过湿剥离工艺去除剩余的金属层。同样，如图77所示，在形成底部硅化物区348之后去除剩余的间隔件层344。
参照图78，在衬底300上形成蚀刻停止层350，并且在蚀刻停止层350上形成绝缘层352。例如，蚀刻停止层350由氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)制成。
参照图79，例如，通过CMP工艺抛光绝缘层352。抛光绝缘层352的工艺停止在蚀刻停止层350上。
参照图80，去除蚀刻停止层350和绝缘层352的部分。通过一个或多个干蚀刻工艺去除蚀刻停止层350和绝缘层352。去除在P型漏极区340和N型漏极区332之上的蚀刻停止层350和绝缘层352的部分。在这个步骤中，也去除硬掩模层302(见图79)。剩余的绝缘层352可以认为是底部绝缘层。
参照图81，在衬底300上形成高k(HK)介电层354和P型功函层356。在高k介电层354和衬底300之间可选地形成界面(IL)层。界面层可以是氧化硅(SiO2)层。可选地，界面层可以可选地包括HfSiO或SiON。在一些实施例中，界面层包括具有羟基基团的化学SiO2层。在界面层的表面上具有羟基基团，可以提高随后生长的高k介电层354的质量。
通过ALD、CVD、金属有机CVD(MOCVD)、PVD、热氧化或它们的组合在界面层上方形成高k介电层354。高k介电层354可以包括二元或三元高k膜，诸如HfOx。可选地，高k介电层354可以可选地包括高k电介质，诸如LaO、AlO、ZrO、ZrO2、TiO、Ta2O5、Y2O3、SrTiO3(STO)、BaTiO3(BTO)、BaZrO、HfZrO、HfZrO2、HfLaO、HfSiO、LaSiO、La2O3、AlSiO、TiO2、HfTaO、HfTiO、HfO2、(Ba,Sr)TiO3(BST)、Al2O3、Si3N4、氮氧化物或其他材料。
P型功函层356可以是TiN、W、Ta、Ni、Pt、Ru、Mo、Al、WN或它们的组合。可以通过ALD、PVD、CVD或其他工艺形成P型功函层356。
参照图82，在衬底300上形成并且图案化BARC层358和掩模层360。在N阱320之上的半导体线结构306被BARC层358和掩模层360覆盖，而去除P阱326之上的BARC层358和掩模层360的部分。去除P阱326之上的P型功函层356的部分。在去除功函金属层356的部分之后，也去除BARC层358和掩模层360。
参照图83，在衬底300上形成N型功函层362。N型功函层362可以是Ti、Ag、Al、TiAlMo、Ta、TaN、TiAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr或它们的组合。可以通过ALD、PVD、CVD或其他工艺形成N型功函层362。
参照图84，在衬底300上形成金属栅极层364。通过ALD、PVD、CVD或其他工艺在N型功函层362上形沉积金属栅极364。金属栅极层364可以是Al、W、Co或Cu。
参照图85，例如，通过干蚀刻工艺去除金属栅极层364、P型功函层356、N型功函层362和高k介电层354的部分。干蚀刻工艺停止在底部绝缘层352上。
参照图86，在衬底300上形成绝缘层366。用绝缘层366填充半导体线结构306之间的间隙。
参照图87，例如，通过CMP工艺抛光绝缘层366。抛光绝缘层366，并且抛光工艺停止在P型功函层356和N型功函层362上。
参照图88，通过干蚀刻或湿蚀刻工艺蚀刻绝缘层366。去除绝缘层366的部分。剩余的绝缘层366可以认为是中间绝缘层，其设置在底部绝缘层352上。中间绝缘层366的顶面低于沟道区334和342的顶面。
参照图89，例如，通过干蚀刻或湿蚀刻工艺去除金属栅极层364、P型功函层356、N型功函层362和高k介电层354的顶部区域。暴露N型沟道区334和P型沟道区342的顶部。金属栅极层364设置在N型沟道区334和P型沟道区342周围，以及高k介电层354设置在金属栅极层364和沟道区334、342之间。
参照图90，在衬底300上形成绝缘层368并且如图91所示，抛光绝缘层368。绝缘层368的顶面与半导体线结构306的顶面基本上齐平。剩余的绝缘层368可以认为是设置在中间绝缘层366上的顶部绝缘层。顶部绝缘层368、中间绝缘层366和底部绝缘层352由相同的介电材料制成并且在下文认为是绝缘层374。
参照图92，在绝缘层374上形成掩模层376。图案化掩模层376，并且去除设置在P阱326之上的掩模层376的部分。通过掩模层376暴露设置在P阱326上的半导体线结构306。然后，对半导体线结构306实施P型注入以在N型沟道区334上形成P型源极区378。P型掺杂剂通过半导体线结构306的顶面进入半导体线结构306。N型漏极区332、N型沟道区334以及P型源极区378基本上垂直地堆叠。P型源极区378的掺杂浓度大于N型漏极区332的掺杂浓度，从而使得电流可以更容易地通过N型沟道区334。N型漏极区332和/或P型源极区378具有在从约1×1018原子/立方厘米至约1×1022原子/立方厘米的范围内的掺杂浓度。N型沟道区334具有在从约1×1012原子/立方厘米至约1×1018原子/立方厘米的范围内的掺杂浓度。在形成P型源极区378之后，去除掩模层376。
参考图93，在绝缘层374上形成掩模层382。图案化掩模层382，并且去除设置在N阱320之上的掩模层382的部分。通过掩模层382暴露设置在N阱320上的半导体线结构306。然后，对半导体线结构306实施N型注入以在P型沟道区342上形成N型源极区384。N型掺杂剂通过半导体线结构306的顶面进入半导体线结构306。P型漏极区340、P型沟道区342以及N型源极区384基本上垂直地堆叠。N型源极区384的掺杂浓度大于P型漏极区340的掺杂浓度，从而使得电流可以更容易地通过P型沟道区342。N型源极区384和/或P型漏极区340具有在从约1×1018原子/立方厘米至约1×1022原子/立方厘米的范围内的掺杂浓度。P型沟道区342具有在从约1×1012原子/立方厘米至约1×1018原子/立方厘米的范围内的掺杂浓度。在形成N型源极区384之后，去除掩模层382。
参照图94，实施一个或多个退火工艺以扩散或活化源极和漏极区。因为通过注入工艺形成源极区、沟道区和漏极区，以便源极区、沟道区和漏极区中的至少一个具有梯度掺杂浓度。在实施退火工艺之后，回蚀刻绝缘层374，并且绝缘层374的顶面与N型沟道区334和P型沟道区342基本上齐平。
参照图95，在衬底300上形成介电硬掩模层388。介电硬掩模层388可以是介电材料，诸如氮化硅(SiN)、碳化硅(SiC)、氮掺杂的碳化硅(SiC:N，也称为NDC)、氮氧化硅(SiON)、氧掺杂的碳化硅(SiC:O，也称为ODC)或氧化硅(SiO2)。介电硬掩模层388用于随后的自对准接触工艺。
参照图96，通过各向异性蚀刻来蚀刻介电硬掩模层，并且在半导体线结构306的侧壁上形成多个侧壁间隔件390。侧壁间隔件390设置在N型源极区384和P型源极区378周围。
参照图97，绝缘层392形成在衬底300上并且覆盖绝缘层374和侧壁间隔件390。因此，用绝缘层392填充N型源极区384和P型源极区378之间的间隙。侧壁间隔件390和绝缘层392由不同的材料制成。
参照图98，抛光绝缘层392。抛光工艺停止在侧壁间隔件390。在下文中，剩余的绝缘层392认为是绝缘层374的部分。侧壁间隔件390被绝缘层374围绕。在这个步骤之后，形成具有垂直全环栅(VGAA)结构的N型隧道场效应晶体管380和P型隧道场效应晶体管386。
参照图99，在衬底300上形成含硅层394。含硅层394可以是无定形硅或多晶硅层。
参照图100，在含硅层394上形成金属层396。例如，金属层396由Ti、Co、Ni、NiCo、Pt、NiPt、Er或Yb制成。在一些实施例中，在金属层396上可选地形成覆盖层。例如，覆盖层可以由氮化钛制成。
参照图101，在硅化工艺中实施一个或多个退火工艺。在这个工艺中含硅层与金属层接触并且与金属层反应以变为顶部硅化物层398。例如，可以通过湿剥离工艺去除剩余的金属层。
参照图102，在顶部硅化物层398上形成掩模层400，以及图案化掩模层400以形成多个部件和通过部件限定的开口。P型隧道场效应晶体管386和N型隧道场效应晶体管380被掩模层400覆盖，并且去除通过掩模层400暴露的顶部硅化物层398的部分。在这个步骤之后，去除掩模层400。
参照图103，图案化的顶部硅化物层398形成在N型源极区384和P型源极区378上作为多个顶部硅化物区。
参照图104，在衬底300上形成并且抛光绝缘层402。绝缘层402的顶面高于N型隧道场效应晶体管380和P型隧道场效应晶体管386的顶面。在下文中，剩余的绝缘层402和绝缘层374称为绝缘层404。N型隧道场效应晶体管380和P型隧道场效应晶体管386通过绝缘层404隔离。
参照图105，图案化绝缘层404，并且在绝缘层404中形成多个开口406。开口406分别暴露金属栅极层364、底部硅化物区348和顶部硅化物区398。可以通过干蚀刻工艺形成开口406，其中蚀刻绝缘层404的速率大于蚀刻侧壁间隔件390的速率，从而使得在蚀刻工艺期间保护N型源极区384和P型源极区378。由于侧壁间隔件390，开口406导致硅化物区348，和金属栅极层364具有至少两个不同的直径。因此，在侧壁间隔件390之上的开口406的直径大于在侧壁间隔件390之下的开口406的直径。
参照图106，沉积导电材料408，以及用导电材料408填充开口406。例如，导电材料408可以通过W、Co、Al或Cu的沉积来形成。然后，例如，通过CMP工艺抛光导电材料408。
参照图107，在开口406中形成多个接触结构410。接触结构410分别连接至金属栅极层364、底部硅化物区348和顶部硅化物区398。接触结构410通过底部硅化物区348连接至漏极区332和340。接触结构410通过顶部硅化物层398连接至源极区384和378。由于开口406在侧壁间隔件390之上和之下具有不同的直径，因此，相应的接触结构410在侧壁间隔件390之上和之下也具有不同的直径。例如，连接至金属栅极层364的接触结构410认为是栅极接触件，并且在侧壁间隔件390之上的栅极接触件的截面面积大于在侧壁间隔件390之下的栅极接触件的截面面积。该工艺也称为自对准接触(SAC)。侧壁间隔件390可以防止接触结构410之间的电短路。
参照图108，分别在接触结构410上形成多个电极412用于后续互连，诸如后段制程(BEOL)工艺。电极412包括栅电极、源电极和漏电极。电极412可以是Cu、Co或其他金属。
如以上描述，提供了包括一个或多个隧道场效应晶体管的隧道场效应晶体管组件。隧道场效应晶体管包括高k金属栅极结构并且因此对短沟道效应具抗干扰性。隧道场效应晶体管具有相反的导电类型。此外，通过使用自对准接触工艺，可以防止接触结构之间的电短路。
以上说明包括示例性操作，并且操作中的步骤并不必按示出的顺序实施。根据本发明的各个实施例的精神和范围，可以适当地添加、替代、改序和/或消除步骤。例如，可以在形成半导体线结构之前或之后形成浅沟槽隔离；可以在形成金属栅极结构之前或之后注入源极区；可选地实施形成侧壁间隔件的步骤。
根据本发明的各个方面，隧道场效应晶体管包括漏极区、与漏极区具有相反的导电类型的源极区、设置在漏极区和源极区之间的沟道区、设置在沟道区周围的金属栅极层、以及设置在金属栅极层和沟道区之间的高k介电层。
在一个或多个实施例中，漏极区、源极区和沟道区基本上垂直地堆叠。源极区的掺杂浓度大于漏极区的掺杂浓度。漏极区、源极区和沟道区中的至少一个具有梯度掺杂浓度。
在一个或多个实施例中，隧道场效应晶体管还包括设置在源极区周围的侧壁间隔件、至少设置在侧壁间隔件周围的绝缘层和栅极接触件。绝缘层和侧壁间隔件由不同的材料制成，并且绝缘层中至少具有至少一个开口以暴露金属栅极层。栅极接触件通过开口连接至金属栅极层，并且侧壁间隔件设置在栅极接触件和源极区之间。在侧壁间隔件之上的栅极接触件的截面面积大于在侧壁间隔件之下的栅极接触件的截面面积。
根据本发明的各个方面，隧道场效应晶体管组件包括具有第一类型阱、第二类型阱、和将第一类型阱与第二类型阱分隔开的浅沟槽隔离部件。隧道场效应晶体管组件包括设置在第二类型阱上的第一类型隧道场效应晶体管、和设置在第一类型阱上的第二类型隧道场效应晶体管。第一类型隧道场效应晶体管包括第一类型漏极区、第二类型源极区、设置在第一类型漏极区和第二类型源极区之间的第一类型沟道区、设置在第一类型沟道区周围的第一金属栅极层、以及设置在第一金属栅极层和第一类型沟道区之间的第一高k介电层。第二类型隧道场效应晶体管包括第二类型漏极区、第一类型源极区、设置在第二类型漏极区和第一类型源极区之间的第二类型沟道区、设置在第二类型沟道区周围的第二金属栅极层、以及设置在第二金属栅极层和第二类型沟道区之间的第二高k介电层。
在一个或多个实施例中，第一类型漏极区、第二类型源极区和第一类型沟道区基本上垂直地堆叠。第二类型漏极区、第一类型源极区和第二类型沟道区基本上垂直地堆叠。
在一个或多个实施例中，第一类型源极区的掺杂浓度大于第二类型漏极区的掺杂浓度。第二类型源极区的掺杂浓度大于第一类型漏极区的掺杂浓度。第一类型源极区、第一类型漏极区、第一类型沟道区、第二类型源极区、第二类型漏极区、和第二类型沟道区中的至少一个具有梯度掺杂浓度。
在一个或多个实施例中，隧道场效应晶体管组件包括形成在第一类型源极区和第二类型源极区上的硅化物区、以及分别设置在第一类型和第二类型源极区周围的多个侧壁间隔件。侧壁间隔件设置在硅化物区和金属栅极层之间。
根据本发明的各个方面，用于制造隧道场效应晶体管的方法包括提供衬底，在衬底上形成半导体线结构，形成高k介电层以及金属栅极层。半导体线结构包括在衬底上形成的底部源极或漏极区、在底部源极或漏极区上形成的沟道区、以及在沟道区上形成的顶部源极或漏极区。高k介电层在沟道区周围形成，并且金属栅极层在高k介电层周围形成。
在一个或多个实施例中，底部硅化物区在底部源极或漏极区上形成，并且顶部硅化物区在顶部源极或漏极区上形成。
在一个或多个实施例中，方法还包括在沟道区周围形成侧壁间隔件，在衬底上方并且至少在侧壁间隔件周围形成绝缘层，在蚀刻工艺中在绝缘层中形成至少一个开口以暴露金属栅极层，蚀刻工艺蚀刻绝缘层的速率大于蚀刻侧壁间隔件的速率，从而使得在蚀刻工艺期间保护沟道区，以及用导电材料填充开口。绝缘层和侧壁间隔件由不同的材料制成。
在一个或多个实施例中，方法还包括在沟道区周围形成侧壁间隔件，在衬底上方并且至少在侧壁间隔件周围形成绝缘层，在蚀刻工艺中在绝缘层中形成至少一个开口以暴露底部源极或漏极区，蚀刻工艺蚀刻绝缘层的速率大于蚀刻侧壁间隔件的速率，从而使得在蚀刻工艺期间保护沟道区，以及用导电材料填充开口。绝缘层和侧壁间隔件由不同的材料制成。
在一个或多个实施例中，方法还包括在顶部源极或漏极区周围形成侧壁间隔件，在衬底上方并且至少在侧壁间隔件周围形成绝缘层，在绝缘层中形成至少一个开口以暴露金属栅极层。在侧壁间隔件之上的开口的截面面积大于在侧壁间隔件之下的开口的截面面积。绝缘层和侧壁间隔件由不同的材料制成。
在一个或多个实施例中，用于形成半导体线结构的行为包括在衬底上形成至少一个线体，以及对线体实施一系列的注入工艺以形成底部源极或漏极区、沟道区和顶部源极或漏极区。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种隧道场效应晶体管，包括：
漏极区；
源极区，其中，所述漏极区和所述源极区是相反的导电类型；
沟道区，设置在所述漏极区和所述源极区之间；
金属栅极层，设置在所述沟道区周围；以及
高k介电层，设置在所述金属栅极层和所述沟道区之间。
2.根据权利要求1所述的隧道场效应晶体管，其中，所述漏极区、所述源极区和所述沟道区基本上垂直地堆叠。
3.根据权利要求2所述的隧道场效应晶体管，其中，所述源极区的掺杂浓度大于所述漏极区的掺杂浓度。
4.根据权利要求1所述的隧道场效应晶体管，其中，所述源极区、所述漏极区和所述沟道区中的至少一个具有梯度掺杂浓度。
5.根据权利要求1所述的隧道场效应晶体管，还包括：
侧壁间隔件，设置在所述源极区周围；
绝缘层，设置在至少所述侧壁间隔件周围，其中，所述绝缘层和所述侧壁间隔件由不同的材料制成，并且，所述绝缘层中具有至少一个开口以暴露所述金属栅极层；以及
栅极接触件，通过所述开口连接至所述金属栅极层，其中，所述侧壁间隔件设置在所述栅极接触件和所述源极区之间。
6.根据权利要求5所述的隧道场效应晶体管，其中，在所述侧壁间隔件之上的所述栅极接触件的截面面积大于在所述侧壁间隔件之下的所述栅极接触件的截面面积。
7.一种隧道场效应晶体管组件，包括：
衬底，具有第一类型阱、第二类型阱和将所述第一类型阱和所述第二类型阱分隔开的浅沟槽隔离部件；
第一类型隧道场效应晶体管，设置在所述第二类型阱上，所述第一类型隧道场效应晶体管包括：
第一类型漏极区；
第二类型源极区；
第一类型沟道区，设置在所述第一类型漏极区和所述第二类型源极区之间；
第一金属栅极层，设置在所述第一类型沟道区周围；和
第一高k介电层，设置在所述第一金属栅极层和所述第一类型沟道区之间；以及
第二类型隧道场效应晶体管，设置在所述第一类型阱上，所述第二类型隧道场效应晶体管包括：
第二类型漏极区；
第一类型源极区；
第二类型沟道区，设置在所述第二类型漏极区和所述第一类型源极区之间；
第二金属栅极层，设置在所述第二类型沟道区周围；和
第二高k介电层，设置在所述第二金属栅极层和所述第二类型沟道区之间。
8.根据权利要求7所述的隧道场效应晶体管组件，其中，所述第一类型漏极区、所述第二类型源极区和所述第一类型沟道区基本上垂直地堆叠。
9.根据权利要求7所述的隧道场效应晶体管组件，其中，所述第二类型漏极区、所述第一类型源极区和所述第二类型沟道区基本上垂直地堆叠。
10.一种用于制造隧道场效应晶体管的方法，包括：
在衬底上形成半导体线结构，其中，所述半导体线结构包括在所述衬底上形成的底部源极或漏极区、在所述底部源极或漏极区上形成的沟道区，并且在所述沟道区上形成的顶部源极或漏极区；
在所述沟道区周围形成高k介电层；以及
在所述高k介电层周围形成金属栅极层。
CN201510136532.2A 2014-04-30 2015-03-26 隧道场效应晶体管及其制造方法 Active CN105047713B (zh)

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