CN105023877A - 半导体晶片、封装结构与其制作方法 - Google Patents

半导体晶片、封装结构与其制作方法 Download PDF

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Publication number
CN105023877A
CN105023877A CN201410174317.7A CN201410174317A CN105023877A CN 105023877 A CN105023877 A CN 105023877A CN 201410174317 A CN201410174317 A CN 201410174317A CN 105023877 A CN105023877 A CN 105023877A
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Prior art keywords
tube core
wafer
spacing
encapsulating structure
underfill layer
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Granted
Application number
CN201410174317.7A
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CN105023877B (zh
Inventor
郭建利
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201410174317.7A priority Critical patent/CN105023877B/zh
Priority to US14/287,065 priority patent/US9947640B2/en
Publication of CN105023877A publication Critical patent/CN105023877A/zh
Priority to US15/911,180 priority patent/US10714452B2/en
Application granted granted Critical
Publication of CN105023877B publication Critical patent/CN105023877B/zh
Priority to US16/889,828 priority patent/US10861832B2/en
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Abstract

本发明提供了一种半导体晶片、封装结构与其制作方法。制作封装结构的方法：首先提供一阵列芯片，包含多个第一管芯。接着提供一晶片，包含有多个第二管芯。进行一封装步骤将阵列芯片对应地设置在晶片上，使该各第一管芯对应地电连接各第二管芯。本发明另外还提供了一种半导体晶片结构，以及一种封装结构。

Description

半导体晶片、封装结构与其制作方法
技术领域
本发明涉及一种半导体晶片、封装结构与其制作方法，特别来说，是涉及一种具有阵列区与管芯区的半导体晶片、封装结构与其制作方法。
背景技术
在现代的资讯社会中，由集成电路(integrated circuit,IC)所构成的微处理器系统早已被普遍运用于生活的各个层面，例如自动控制的家电用品、行动通讯设备、个人电脑等，都有集成电路的踪迹。而随着科技的日益精进，以及人类社会对于电子产品的各种想象，使得集成电路也往更多元、更精密、更小型的方向发展。
一般所谓集成电路，是通过现有半导体制作工艺中所生产的管芯(die)而形成。制造管芯的过程，由生产一晶片(wafer)开始：首先，在一片晶片上区分出多个区域，并在每个区域上，通过各种半导体制作工艺如沉积、光刻、蚀刻或平坦化步骤，以形成各种所需的电路路线，接着，再对晶片上的各个区域进行切割而成各个管芯，并利用各种的封装技术，将管芯封装成芯片(chip)，最后再将芯片电连至一电路板，如一印刷电路板(printed circuit board,PCB)，使芯片与印刷电路板的接脚(pin)电连接后，便可执行各种编程的处理，而形成一完整的封装体。
为了达成各种微型化的需求，目前业界对于崭新的封装制作工艺以及封装结构有着强烈的需求。
发明内容
本发明于是提出了一种半导体晶片、一种封装结构与其制作方法，可以提升制作工艺速度，又能兼顾产品良率。
根据本发明其中一种实施例，本发明提供了一种制作封装结构的方法，首先提供一阵列芯片(array chip)，包含多个第一管芯(die)。接着提供一晶片(wafer)，包含多个第二管芯。最后进行一封装步骤将阵列芯片对应地设置在晶片上，使各第一管芯对应地电连接各第二管芯。
根据本发明另外一种实施例，本发明提供了一种半导体晶片，其包含有多个阵列区、多个管芯区以及多个管芯。每个阵列区之间具有一第一间距。多个管芯区设置在一个阵列区中，其中每个管芯区之间具有一第二间距，第一间距大于第二间距。每一个管芯对应设置在每一个管芯区中。
根据本发明另外一种实施例，本发明提供一种封装结构，包含一第一管芯、一第二管芯以及一底部填充层。第一管芯与第二管芯都包含一第一面、与第一面对应设置的第二面、在第一面与第二面之间的至少两侧面。底部填充层覆盖在第一管芯的第一面与第二管芯的第一面，且进一步覆盖第一管芯的至少一个侧面，且该第一管芯的至少一个该侧面完全未被底部填充层覆盖。
本发明制作封装结构的方法，其特征在于先将多个管芯通过一阵列芯片与一晶片电连接后，再进行切割制作工艺以将各个管芯分开，而形成封装结构。与现有技术相比，可以提升制作工艺速度，又能兼顾产品良率。
附图说明
图1、图1A、图2、图3、图4、图4A、图5、图5A、图6、图6A与图6B，所绘示为本发明一种半导体结构的制作方法其中一种实施例的步骤示意图。
主要元件符号说明
300,400         晶片                  314          接触垫
302,402         管芯                  316          阵列芯片
304             主动面(有源面)        318          侧面
306,406         半导体结构        350,450          阵列区
308             硅贯穿电极        352,452          管芯区
310             晶体管            500              连接元件
312             金属内连线系统    502              底部填充层
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参考图1、图1A、图2、图3、图4、图4A、图5、图5A、图6、图6A、图6B，所绘示为本发明一种半导体结构的制作方法其中一种实施例的步骤示意图，其中图1、图2、图3、图4、图5与图6为立体图，图1A为图1的剖视图。图4A为对应于图4的剖视图，图5A为对应于图5的剖视图，图6A为对应于图6的剖视图，图6B为对应于图6的俯视图。
首先请参考图1与图1A，图1A为图1中沿AA’切线所绘制的剖视图。本发明的半导体结构的制作方法提供一第一晶片(wafer)300。第一晶片300上定义有多个阵列区(array region)350，在一实施例中，各阵列区350呈现如阵列的排列方式，例如具有M排以及N列，使得第一晶片300包含M×N数量的阵列区350，M与N为大为1的整数。在一优选实施例中，M与N相等。在本发明中，每个阵列区350之间具有一第一间距G1。
如图1所示，每个阵列区350中定义有多个管芯区352。在一实施例中，位于同一阵列区350中的管芯区350同样呈现如阵列的排列方式，例如具有m排以及n列，使得一个阵列区350中包含有m×n数量的管芯区350，其中m与n可以是大于1的整数。在一实施例中，m与n相等。在本发明中，位于同一阵列350区中的管芯区350之间具有一第二间距G2。在一实施例中，第二间距G2小于第一间距G1，两者的差值大于10微米(μm)，例如是20微米与40微米之间。在一实施例中，第一间距G1大于80微米，例如是100微米，第二间距G2介于40微米与60微米之间。而在另一实施例中，第一间距G1也可以等于第二间距G2。
后续，进行一个或多个半导体制作工艺，以在第一晶片300上形成至少一个半导体结构306。如图1A所示，半导体结构306形成在第一晶片300的一主动面304的一侧上。半导体结构306可以包含各种主动元件或是被动元件，在本发明的一实施例中，半导体结构306例如包含一硅贯穿电极308、一晶体管310、一金属内连线系统312、及/或一接触垫314，但并不以上述为限。第一晶片300中，包含了已完成的半导体结构306的每个管芯区352被定义为一第一管芯(die)302。
关于第一管芯302在第一晶片300中的布局方式，本发明提供至少四种实施态样。在第一实施例中，位于第一芯片300上的每个第一管芯302都相同(identical)，也就是说，在每个第一管芯302中半导体结构306的布局与设置完全相同。在第二实施例中，位于同一阵列区350的每个第一管芯302相同，但位于不同阵列区350的第一管芯302彼此不同，以图1为例，位于阵列区350A中的多个第一管芯302A都相同，位于阵列区350B的多个第一管芯302B都相同，但第一管芯302A与第一管芯302B不相同。在第三实施例中，位于阵列区350中的每个第一管芯302都不同，但不同阵列区350之间各第一管芯302的布局与相对位置相同，以图1为例，位于阵列区350C的第一管芯302各自为不同的管芯，标示为C、D、F、G、H、I、J、K，在阵列区350D的第一管芯302各自为不同的管芯，标示为C、D、F、G、H、I、J、K，阵列区350C的第一管芯302C与阵列区350D的第一管芯302C相同且对应位置相同，阵列区350C的第一管芯302D与阵列区350D的第一管芯302D相同且对应位置相同，如此类推。在第四实施例中，位于第一晶片300上的每个第一管芯302都不相同。此外，在一实施例中，半导体结构306也可以形成在管芯区350以外的地方，例如位于管芯区352与管芯区352之间(即第二间距G2处)、或者阵列区350与阵列区350之间(即第一间距G1处)，以作为例如测试电路或虚拟电路之用。
接着如图2所示，对第一晶片300进行一第一切割制作工艺(dicingprocess)，沿着阵列区350的边缘切割，以形成多个阵列芯片(array chip)316。每个阵列芯片316包含多个第一管芯302。
接着如图3所示，提供一第二晶片400。第二晶片400大体上具有与第一晶片300相同的布局，例如第二晶片400具有多个阵列区450，每个阵列区450中具有多个管芯区452，其中每个阵列区450之间具有一第三间距G3，每个管芯区452之间具有一第四间距G4，第三间距G3大于第四间距G4。在一实施例中，第四间距G4和第二间距G2相同，使得阵列芯片316上的管芯区352可以对应于第二晶片400上阵列区450的管芯区352。在一实施例中，第三间距G3与第一间距G1相同，但于另一实施例中，第三间距G3与第一间距G1也可以不同。第二晶片400上同样具有半导体结构406(图3未示)，其配置可以和第一晶片300不同，也可以相同。
在另外一实施例中，第二晶片400的管芯区452也可以毋须对应第一晶片300的管芯区352，而可以以「一对多」的方式呈现，例如第二晶片400的一个管芯区452可以对应第一晶片300的多个管芯区352。
而第二晶片400上第二管芯402布局而言，同样具有四种态样：第一实施例中，位于第二芯片400上的每个第二管芯402都相同；在第二实施例中，位于同一阵列区450的每个第二管芯402相同，但位于不同阵列区450的第二管芯402不同；在第三实施例中，位于阵列区450中的每个第二管芯402都不同，但不同阵列区450之间各第一管芯402的布局与相对位置相同。在第四实施例中，位于第一芯片400上的每个第二管芯402都不相同。而在一实施例中，第一晶片300与第二晶片400的实施态样会相同，例如当第一晶片300为第二实施例时，第二晶片400也是第二实施例。但在其他实施例中，视产品设计与规划，他们也可以不相同。
接着如图4与图4A所示，进行一封装步骤以将阵列芯片316对应地封装在第二晶片400的阵列区450上，使阵列芯片316的第一管芯302对应地电连接至第二晶片400阵列区450的至少一个第二管芯402。本实施例所称的封装步骤，是指任何电连接第一管芯302的半导体结构306与第二管芯402的半导体结构406的步骤。在一实施例中，如图4A所示，封装步骤包含形成一连接元件500，例如锡球，以电连接第一管芯302的接触垫314以及第二管芯402的接触垫414。而在其他实施例中，也可使用例如硅贯穿电极、铜柱、硅中间板(interposer)或是打线(wire bonding)等方式来实现，且不以上述为限。
后续，如图5与图5A所示，在阵列芯片316与第二晶片400之间形成一底部填充层(underfill layer)502。在一实施例中，如图5A所示，底部填充层502会形成在第一芯片302与第二芯片402与连接元件500之间所形成的空间中，且为了确保底部填充层502能完全填入前述空间中，底部填充层502会进一步形成第二晶片400上超出阵列区450边缘的区域，且覆盖在阵列芯片316的一侧壁318上。在一实施例中，底部填充层502例如是环氧树脂(epoxy)。本发明由于阵列区450之间具有较大的第三间距G3，可顺利施加底部填充层。另一方面，管芯区452之间的间距G4即可缩小，可省却晶片空间。
最后，如图6、图6A、图6B所示，进行一第二切割制作工艺，以将同一阵列区的第一管芯302与第二管芯402切割出来，而形成多个封装结构504。如图6与图6A所示，封装结构504包含第一管芯302与第二管芯402，底部填充层502设置在第一管芯302与第二管芯402之间。更详细来说，第一管芯302包含有一第一面302a(例如是主动面或正面)、一第二面302b(例如是背面)、以及位于第一面302a与第二面302b之间的多个侧面302c；第二管芯402包含有一第一面402a、一第二面402b、以及位于第一面402a与第二面402b之间的多个侧面402c。底部填充层502会覆盖在第一芯片302的第一面302a以及第二芯片402的第二面402a。
在一实施例中，在切割各阵列区450的周围时，第二切割制作工艺中的切割道稍微突出于阵列区450，使得第二切割制作工艺并不切割底部填充层502，或是仅切割部分的底部填充层502，而形成三种封装结构504A、504B、504C。如图6与图6B所示，以靠近阵列区450周围的封装结构504A而言，第一管芯302的一个侧壁302c会被底部填充层502覆盖(可一并参考图6A)，但其他三个侧壁则没有被底部填充层502覆盖。以位于转角(corner)处的封装结构504B而言，其第一管芯302的两个侧壁302c会被底部填充层502覆盖，但其他两个侧壁则没有被底部填充层502覆盖；而其余的封装结构504C，管芯300没有侧壁被底部填充层502覆盖。并且，如图6A所示，第二管芯402’的第一面402a与第二面402b大于第一管芯302的第一面302a与第二面302b。
此外，第二切割制作工艺主要沿着阵列芯片316的管芯区352或者第二晶片400的管芯区452切割，而在如前述实施例中「多对一」的情况时，则以面积较大的管芯区为主。例如当第二晶片400的管芯区452对应于多个阵列芯片346的管芯区352时，第二切割制作工艺是切割第二晶片400的管芯区452。后续，可进一步对封装结构504做后续的封装制作工艺。
本发明制作封装结构的方法，其特征在于先将多个管芯通过一阵列芯片以和一晶片电连接，再进行切割制作工艺以将各个管芯分开，而形成封装结构。与现有技术相比，例如「芯片对晶片(chip to wafer)」制作工艺，其是以一个管芯个别地连接另一晶片，此现有技术必须额外加大每个管芯之间的间距以利形成底部填充层(例如每个管芯之间的间距都大于80微米)，且过程十分耗时。与另一现有技术相比，如「晶片对晶片(wafer to wafer)」制作工艺，其是以一个晶片直接连接另一晶片，此现有技术必须克服两晶片之间的对应程度，十分容易产生偏移，且容易因尘埃等污染而使两个晶片同时报销，有损制作良率。本发明则能在上述现有技术中取得平衡，可以提升制作工艺速度，又能兼顾产品良率。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种制作封装结构的方法，包含：
提供一阵列芯片(array chip)，包含多个第一管芯(die)；
提供一晶片(wafer)，包含多个第二管芯；
进行一封装步骤将该阵列芯片对应地设置在该晶片上，使各该第一管芯对应地电连接各该第二管芯。
2.如权利要求1所述的制作封装结构的方法，其中该阵列芯片具有多个管芯区，且各该管芯区中对应设置有一个该第一管芯。
3.如权利要求2所述的制作封装结构的方法，各该管芯区之间具有一第二间距，该第二间距介于40微米与60微米之间。
4.如权利要求1所述的制作封装结构的方法，其中该晶片包含：
多个阵列区，每个该阵列区之间具有一第三间距：
多个管芯区设置在一个该阵列区中，其中每个该管芯区之间具有一第四间距，该第三间距大于该第四间距：以及
该多个第二管芯，各该第二管芯对应设置在各该管芯区中。
5.如权利要求1所述的制作封装结构的方法，该封装步骤包含在该晶片以及该阵列芯片之间形成一连接元件。
6.如权利要求1所述的制作封装结构的方法，该封装步骤包含在该晶片以及该阵列芯片之间形成一底部填充层(underfill layer)。
7.如权利要求6所述的制作封装结构的方法，其中该底部填充层还会形成在该阵列芯片的一侧壁上。
8.如权利要求6所述的制作封装结构的方法，其中该底部填充层包含环氧树脂。
9.如权利要求1所述的制作封装结构的方法，进行完该封装步骤后，还包含进行一切割制作工艺同时切割该阵列芯片以及该晶片，以形成一封装结构。
10.如权利要求9所述的制作封装结构的方法，其中该封装结构包含：
一个该第一管芯以及一个该第二管芯，该第一管芯与该第二管芯都包含：
第一面；
第二面，与该第一面对应设置；以及
至少两侧面设置在该第一面与该第二面之间；以及
底部填充层设置在该第一管芯与该第二管芯之间，且该第一管芯的至少一个该侧面被该底部填充层覆盖。
11.如权利要求10所述的制作封装结构的方法，其中该第一管芯的两个该侧面被该底部填充层覆盖。
12.一种半导体晶片，包含：
多个阵列区，各该阵列区之间具有一第一间距：
多个管芯区设置在一个该阵列区中，各该管芯区之间具有一第二间距，该第一间距大于该第二间距：以及
多个管芯，各该管芯对应设置在各该管芯区中。
13.如权利要求12所述的半导体晶片，其中位于同一个阵列区中的该多个管芯实质上相同。
14.如权利要求12所述的半导体晶片，其中位于同一个阵列区中的该多个管芯实质上相同，但位于不同阵列区的该多个管芯实质上不同。
15.如权利要求12所述的半导体晶片，其中该第一间距大于80微米。
16.如权利要求12所述的半导体晶片，其中该第二间距介于40微米与60微米之间。
17.一种封装结构，包含：
第一管芯以及第二管芯，该第一管芯与该第二管芯都包含：
第一面；
第二面，与该第一面对应设置；以及
至少两侧面设置在该第一面与该第二面之间；以及
底部填充层，覆盖在该第一管芯的该第一面与该第二管芯的该第一面，以及该第一管芯的至少一个该侧面，且该第一管芯的至少一个该侧面完全未被该底部填充层覆盖。
18.如权利要求17所述的封装结构，其中该底部填充层覆盖该第一管芯的该两个侧面。
19.如权利要求17所述的封装结构，其中该第一管芯的至少一个该侧面被该底部填充层覆盖，但其他侧面没有被该底部填充层覆盖。
20.如权利要求17所述的封装结构，其中该第二管芯的该第一面大于该第一管芯的该第一面。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114927415A (zh) * 2022-07-22 2022-08-19 山东中清智能科技股份有限公司 一种芯片阵列封装体及其形成方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023033970A (ja) * 2021-08-30 2023-03-13 ソニーセミコンダクタソリューションズ株式会社 半導体チップ、製造方法、および電子機器
KR20240061786A (ko) * 2022-11-01 2024-05-08 삼성전자주식회사 반도체 장치의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113253A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20080153265A1 (en) * 2006-12-21 2008-06-26 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer
US20080164605A1 (en) * 2007-01-08 2008-07-10 United Microelectronics Corp. Multi-chip package
CN101258583A (zh) * 2005-07-29 2008-09-03 飞思卡尔半导体公司 利用多管芯小片的三维集成电路的制造
US20090194787A1 (en) * 2008-01-14 2009-08-06 The Regents Of The University Of California Vertical outgassing channels

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5206181A (en) * 1991-06-03 1993-04-27 Motorola, Inc. Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing
US6610560B2 (en) * 2001-05-11 2003-08-26 Siliconware Precision Industries Co., Ltd. Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
JP4123027B2 (ja) * 2003-03-31 2008-07-23 セイコーエプソン株式会社 半導体装置の製造方法
US7807505B2 (en) * 2005-08-30 2010-10-05 Micron Technology, Inc. Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods
US8344505B2 (en) * 2007-08-29 2013-01-01 Ati Technologies Ulc Wafer level packaging of semiconductor chips
US7951647B2 (en) 2008-06-17 2011-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Performing die-to-wafer stacking by filling gaps between dies
US8242543B2 (en) 2009-08-26 2012-08-14 Qualcomm Incorporated Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers
US8345508B2 (en) * 2009-09-20 2013-01-01 General Electric Company Large area modular sensor array assembly and method for making the same
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8486758B2 (en) 2010-12-20 2013-07-16 Tessera, Inc. Simultaneous wafer bonding and interconnect joining
US8963334B2 (en) * 2011-08-30 2015-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Die-to-die gap control for semiconductor structure and method
TWI620340B (zh) * 2013-03-15 2018-04-01 傲思丹度科技公司 增強效能主動式像素陣列及用於達成其之磊晶成長方法
US9524942B2 (en) * 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9716031B2 (en) * 2014-04-08 2017-07-25 Nxp Usa, Inc. Semiconductor wafer and method of concurrently testing circuits formed thereon

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040113253A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
CN101258583A (zh) * 2005-07-29 2008-09-03 飞思卡尔半导体公司 利用多管芯小片的三维集成电路的制造
US20080153265A1 (en) * 2006-12-21 2008-06-26 Texas Instruments Incorporated Semiconductor Device Manufactured Using an Etch to Separate Wafer into Dies and Increase Device Space on a Wafer
US20080164605A1 (en) * 2007-01-08 2008-07-10 United Microelectronics Corp. Multi-chip package
US20090194787A1 (en) * 2008-01-14 2009-08-06 The Regents Of The University Of California Vertical outgassing channels

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114927415A (zh) * 2022-07-22 2022-08-19 山东中清智能科技股份有限公司 一种芯片阵列封装体及其形成方法

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