CN104979344A - 用于创建具有降低表面电场效果的具有在体衬底上的横向集电极的高电压互补bjt的方法 - Google Patents

用于创建具有降低表面电场效果的具有在体衬底上的横向集电极的高电压互补bjt的方法 Download PDF

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CN104979344A
CN104979344A CN201510158427.9A CN201510158427A CN104979344A CN 104979344 A CN104979344 A CN 104979344A CN 201510158427 A CN201510158427 A CN 201510158427A CN 104979344 A CN104979344 A CN 104979344A
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CN104979344B (zh
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J·A·巴布科克
A·萨多夫尼科夫
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Texas Instruments Inc
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Abstract

本发明公开了用于创建具有降低表面电场效果的具有在体衬底上具有的横向集电极的具有减小表面电场效果的高电压互补BJT的方法，并且描述了形成在标准体硅集成电路中的高电压双极晶体管(100，200)。在一个公开的实施例中，集电极区域(104，204)被形成在外延硅层中。基区(113，213)和发射极(108，208)被布置在集电极区域的上方。n型区域(106)通过在沉积集电极外延区域之前将施主杂质注入到PNP晶体管的p衬底和将受主杂质注入到NPN晶体管的p衬底来形成在集电极区域的下方。在后面的工艺流程中，这些n型(106)和p型(206)区域通过深n+(110)阱和深p+(210)阱分别连接到管芯的顶部。n型阱接着被耦合到VCC，而p型阱被耦合到GND，从而提供PNP和NPN集电极区域的横向消耗的部分，并且因此增加PNP和NPN集电极区域的BV。

Description

用于创建具有降低表面电场效果的具有在体衬底上的横向集电极的高电压互补BJT的方法
技术领域
本发明涉及双极晶体管制造领域，并且特别涉及使用体硅技术在公共衬底上具有变化特性的互补晶体管的制造。
背景技术
集成电路已经利用双极结晶体管多年，利用其高增益特性的优势以满足高性能和高电流驱动的需要。特别地，如本领域所知的，双极晶体管尤其非常适合高频率应用，诸如，现在被用于无线通信中。
绝缘体上的硅(SOI)技术因在高频率电子器件中发挥重要优势而被本领域所熟知。作为SOI技术中的基础，有源器件诸如晶体管被形成在于绝缘层上形成的单晶硅层中，诸如通常被称作隐埋氧化物(BOX)的二氧化硅层。隐埋氧化物层将有源器件与下面的衬底隔离，这有效地消除了到衬底的寄生非线性结电容并且降低了集电极-衬底电容。在某种程度上，体晶体管的高频性能受限于衬底电容，SOI技术提供了显著的改善。
针对NPN和PNP两者已经实现了记录fT峰值*BVCEO产品。这是可能的，其应归功于从衬底穿过低掺杂集电极区域上的隐埋氧化物的降低表面电场(resurf)效果。
然而，SOI衬底的高成本阻止了使用这种技术来进行大量的产品开发。此外，分离电压源必须在PNP中实现降低表面电场效果(用于接地衬底)。已经观察到的是，显著的自加热出现在电流超过fT峰值和大VCE处。
传统的SOI双极晶体管被设计成高性能器件。然而，从击穿电压和性能两者的角度来看，高性能晶体管在某种程度上受限于其结构。作为本领域中的基础，集电极发射极击穿电压(BVCEO)取决于集电极区域的厚度和集电极区域的掺杂浓度。集电极区域的轻掺杂和厚集电极区域会使该击穿电压增加。
在实际电路中，发射极和基极互补SiGe双极结型晶体管(BJT)围绕最高电势Vcc(相对于接地衬底)被偏置，而集电极在Vcc和0之间切换。高B-C偏置对应于集电极处的零电势。
所需要的是增加PNP BV而不降低集电极掺杂浓度或增加PNP的集电极区域厚度，同时在相同体处理的电路/衬底上包括高电压的NPN的方法。
发明内容
为了提供对本发明的一个或多个方面的基本理解，在下面呈现了简要概述。此概述并非本发明的详尽概述，并且既不旨在确定本发明的关键或重要元素，也不旨在描述其范围。更确切地说，概述的主要目的是作为引子以简化形式呈现本发明的某些概念，以便稍后呈现更详细的描述。
根据本申请的实施例，一种集成电路结构，其包括：互补的PNP和NPN结构；其中PNP和NPN结构包括p型体半导体衬底；PNP和NPN有源器件区域；隐埋N+和P+降低表面电场区域；其中，p型区域和有源器件PNP和NPN区两者使用单晶硅来实现；以及围绕每个晶体管的深槽隔离区域，其中该深槽隔离区域将互补的PNP和NPN结构彼此隔离。
根据本申请的另一实施例，一种形成互补的PNP和NPN结构的方法，该形成互补的PNP和NPN结构的方法包括：提供p型体半导体衬底；创建PNP和NPN有源器件区域；分别在PNP和NPN器件区中注入隐埋N+和P+降低表面电场区域；使用单晶硅实现体半导体衬底和PNP和NPN器件区两者；以及使用深槽隔离区域围绕每个晶体管，以将互补的PNP和NPN结构彼此隔离。
附图说明
图1A示出本发明的实施例的横截面图。
图1B示出图1A中PNP晶体管的细节的放大部分。
图1C示出图1A中NPN晶体管的细节的放大部分。
图2示出BVCER对针对以μm为单位的各种基极-集电极间距SBC的PNP的集电极掺杂浓度的依赖关系。
图3示出BVCER对针对以μm为单位的各种基极-集电极间距SBC的NPN的集电极掺杂浓度的依赖关系。
图4示出针对NPN和PNP两者的，BVCER对以μm为单位的各种基极-集电极间距SBC的依赖关系。
在附图中，相同的参考数字有时用来指定相同的结构元件。还应当理解的是，附图中的描绘是示意的，而不是按比例的。
具体实施方式
参照附图对本发明进行描述。该附图没有按比例绘制，并且它们仅被提供用于图示本发明。参照用于说明的示例应用，下面对本发明的几个方面进行描述。应当理解的是，多个具体细节、关系以及方法被阐述，从而提供对本发明的理解。然而，相关领域的技术人员将容易认识到，本发明可以无需一个或多个特定细节或者使用其它方法来实施。在其他实例中，公知的结构或操作没有详细示出，以避免使本发明不清楚。本发明不受到活动或事件的示出的顺序的限制，因为某些活动可以按不同的顺序和/或与其它活动或事件同时发生。此外，并不是所有示出的活动或事件对实现根据本发明的方法来说都是必需的。
本发明的实施例被示出在图1A-1C中，互补的PNP 100和NPN200结构使用体硅技术包括在共同的衬底上，该结构分别具有p型区101、有源器件区域104和204。有源器件区域104和204的初始掺杂水平可以是n型，1e14。在本示例中，p型区域101和有源器件区域104和204两者都使用单晶硅来实现。为了创建图3B的具有较高的PNP BV的结构，通过在集电极104外延生长之前，将约3e16至3e181/cm3的施主杂质注入到p型区域101，从而使隐埋的n型降低表面电场区域106被包括在PNP晶体管100的有源器件区域104的下方。在后面的工艺流程中，该n型区域106通过深n型阱110从顶部被连接，并且被偏置于Vcc。在这种情况下，这会消耗PNP集电极区域的横向部分，并且因此将增加PNP集电极区域得BV。为了创建图3C中具有较高NPN BV的结构，通过在集电极204外延生长之前将约3e16至3e18 1/cm3的受主杂质注入到p型区域101，隐埋的p型降低表面电场区域206被包括在NPN晶体管100的有源器件区域204的下方。在后面的工艺流程中，该p型区域206通过深P型阱210从顶部被连接，并且被偏置于GND。在这种情况下，这将既消耗NPN集电极区域的横向部分，并且又因此将增加NPN集电极区域得BV。
以下对提供具有较高BV的PNP晶体管100的结构(图1B)进行描述。
首先，如图1A-1B中所示的本发明所描述的，标准的p型体晶片被提供。
接着，第一掩膜和注入步骤被完成，以注入高3e16至3e181/cm3剂量的n型种类。高掺杂的n层106垂直地在PNP的下方。
接着，集电极104epi以＜3e141/cm3的非常低的掺杂和～3到4um的厚度增长。
完成第三掩膜和蚀刻步骤从而提供硬掩膜，硬掩膜用于限定和沉积有源器件区域104中的绝缘层STI 105。
深槽109被形成，以包围PNP晶体管100和深n型阱110。沟槽从管芯的顶部延伸至高掺杂的n层106以下，并且深n型阱从管芯的顶部延伸到并且穿过有源器件区域104，并且延伸到高掺杂n层106，其中该深n型阱110接触注入的高掺杂n层，并且延伸到管芯的顶部，从而提供了到注入的n层106的顶部触点。
使用有源器件区域104的顶部上的具有相反导电性类型的杂质来沉积、限定以及掺杂基极外延半导体层113，其中基极触点111耦合到该基极外延半导体层113。在由浅槽隔离STI 105暴露的基极区和p阱107之间的间隔在确定如图4所示的PNP晶体管的BVCER和fT峰值是十分关键的。
最后，发射极区域108覆盖基极外延半导体层113的一部分，其中发射极区域108被高掺杂以与有源器件区域104相同的导电性类型。
以下对提供具有较高BV的NPN晶体管200的结构(图1C)进行描述。
首先，如图1A和图1C中所示的本发明所描述的，标准的p型体晶片被提供。
接着，完成第一掩膜和注入步骤，从而注入高3e16至3e181/cm3剂量的p型种类。高掺杂的p层206垂直地在NPN的下方。
接着，集电极204epi以＜3e141/cm3的非常低的掺杂和～3到4um的厚度增长。
完成第三种掩膜和蚀刻步骤从而提供硬掩膜，硬掩膜用于限定和沉积有源器件区域204中的绝缘体层STI 105。
深槽109被形成，以包围NPN晶体管200和深p型阱210。沟槽从管芯的顶部延伸至高掺杂的p层206的下方，并且深p型阱从管芯的顶部延伸到并且穿过有源器件区域204，并且延伸到高掺杂P层206，其中该深p型阱210接触注入的高掺杂p层，并且延伸到管芯的顶部，从而提供了到注入的p层206的顶部触点。
使用有源器件区域204的顶部上的具有相反导电性类型的杂质来沉积、限定以及掺杂基极外延半导体层213，其中基极触点111耦合到该基极外延半导体层213。在由浅槽隔离STI 105暴露的基极区域和n阱207之间的间隔在确定如图4所示的NPN晶体管的BVCER和fT峰值中是十分关键的。
最后，发射极区域208覆盖基极外延半导体层113的一部分，其中发射极区域208被高掺杂以与有源器件区域204相同的导电性类型。
用于NPN和PNP的基极外延半导体可以是硅锗或硅。基极外延半导体也可以在两个操作中被沉积，一个操作是用于NPN的以及一个操作是用于PNP的。
图2示出BVCER对针对以μm为单位的各种基极-集电极间距SBC的PNP的集电极掺杂浓度的依赖关系。与曲线对齐的数字表示以μm为单位的基极-集电极间距。
图3示出BVCER对针对以μm为单位的各种基极-集电极间距SBC的NPN的集电极掺杂浓度的依赖关系。与曲线成对齐的数字表示以μm为单位的基极-集电极间距。
图4示出针对NPN和PNP两者的BVCER对以μm为单位的各种基极-集电极间距SBC的依赖关系。PNP的集电极掺杂是3e15并且NPN的集电极掺杂是2e15。
本发明相对于现存的SOI体系结构提供了三个优点：
(1)工艺流程开始于廉价的标准体晶片。
(2)适当的偏置可以被施加到PNP和NPN的隐埋层，以使用降低表面电场效果从而充分发挥其强度。根据TCAD结果，相比于SOI上的器件的类似的fT峰值*BVCEO的数字可以被实现。
(3)自加热要低得多。
虽然以上已经描述本发明的各种实施例，但是应当理解的是，它们仅通过示例的方式来呈现，而非限制的。在不背离本发明的精神或范围的情况下，根据在此的公开可以对公开的实施例进行多种改变。因此，本发明的广度和范围不应当受限于以上描述的任何实施例。相反，本发明的范围应当根据以下的权利要求及其等同来限定。

Claims (16)

1.一种集成电路结构，其包括：
互补的PNP和NPN结构；
其中所述PNP和NPN结构包括p型体半导体衬底；
PNP有源器件区域和NPN有源器件区域；
隐埋N+降低表面电场区域和隐埋P+降低表面电场区域；
其中所述p型区域和所述PNP有源器件区域和所述NPN有源器件区域两者使用单晶硅来实现；和
围绕每个晶体管的深槽隔离区域，其中所述深槽隔离区域将所述互补的PNP和NPN结构彼此隔离。
2.根据权利要求1所述的集成电路结构，其中所述PNP进一步包括：
第一掩膜和注入，以将高掺杂n层注入所述p型体半导体衬底中，其中所述高掺杂n层垂直地在所述PNP区的下方，并且向所述深槽隔离延伸并且与所述深槽隔离接触；
第二掩膜和注入步骤，所述第二掩膜和注入步骤在焊盘氧化之后氮化物沉积之前被执行，以在所述有源器件区域创建均匀的集电极掺杂水平；
第三掩膜和蚀刻步骤，所述第三掩膜和蚀刻步骤用于提供限定在所述有源器件区域中的浅槽绝缘层即STI层的区域的硬掩膜；
深槽，所述深槽被形成以包围所述PNP晶体管和所述高掺杂n层，其中所述沟槽在所述高掺杂n层的底部以下延伸，并且延伸到管芯的顶部；
p型阱，所述p型阱延伸穿过所述STI层，并且接触所述有源器件层的集电极，其中集电极触点耦合到该p型阱；
深n型阱，所述深n型阱从所述晶片的顶部延伸穿过所述STI层和所述有源器件层，所述深n型阱接触所述高掺杂n层，其中VCC触点耦合到该深n型阱；
基极外延半导体层，使用所述有源器件区域的顶部上的相反导电性类型的杂质来沉积、限定以及掺杂所述基极外延半导体层，其中基极触点耦合到该基极外延半导体层；和
发射极区域，所述发射极区域覆盖所述基极外延半导体层的一部分，其中所述发射极区域被高掺杂以与所述有源器件区域相同的导电性类型。
3.根据权利要求1所述的集成电路结构，其中所述PNP有源器件区域具有＜3e14 1/cm3的受主掺杂和3到4um的厚度。
4.根据权利要求1所述的集成电路结构，其中所述PNP区中的所述隐埋N+降低表面电场区域被注入以3e16至3e18 1/cm3的施主剂量。
5.根据权利要求1所述的集成电路结构，其中所述NPN进一步包括：
第一掩膜和注入，以将高掺杂p层注入所述p型体半导体衬底中，其中所述高掺杂p层垂直地在所述NPN区的下方，并且向所述深槽隔离延伸并且与所述深槽隔离接触；
第二掩膜和注入步骤，所述第二掩膜和注入步骤在焊盘氧化之后氮化物沉积之前被执行，以在所述有源器件区域中创建均匀的集电极掺杂水平；
第三掩膜和蚀刻步骤，所述第三掩膜和蚀刻步骤用于提供限定在所述有源器件区域中的浅槽绝缘层即STI层的区域的硬掩膜；
深槽，所述深槽被形成以包围所述NPN晶体管和所述高掺杂p层，其中所述沟槽在所述高掺杂p层的底部以下延伸，并且延伸到管芯的顶部；
n型阱，所述n型阱延伸穿过所述STI层，并且接触所述有源器件层的所述集电极，其中集电极触点耦合到该n型阱；
深p型阱，所述深p型阱从所述晶片的顶部延伸穿过所述STI层和所述有源器件层，所述深p型阱接触所述高掺杂p层，其中GND触点耦合到该深p型阱；
基极外延半导体层，使用所述有源器件区域的顶部上的相反导电性类型的杂质来沉积、限定以及掺杂所述基极外延半导体层，其中基极触点耦合到所述基极外延半导体层；和
发射极区域，所述发射极区域覆盖所述基极外延半导体层的一部分，其中所述发射极区域被高掺杂以与有源器件区域相同的导电类型而。
6.根据权利要求1所述的集成电路结构，其中所述NPN有源器件区域具有＜3e14 1/cm3的施主掺杂和3到4um的厚度。
7.根据权利要求1所述的集成电路结构，其中所述NPN区中的所述隐埋N+降低表面电场区域被注入以3e16至3e18 1/cm3的受主剂量。
8.根据权利要求1所述的集成电路结构，其中被包括在所述PNP晶体管下方的隐埋N+降低表面电场和在所述NPN下方的所述隐埋P+降低表面电场区域分别通过深n型和p型阱耦合到所述晶片的顶部并且分别偏置于Vcc和GND，其中所述偏置将消耗所述PNP和NPN集电极区域两者的横向部分，并且因此将增加所述PNP和NPN集电极区域的BV。
9.一种形成互补的PNP和NPN结构的方法，其包括：
提供p型体半导体衬底；
创建PNP有源器件区域和NPN有源器件区域；
在所述PNP和NPN器件区域分别注入隐埋N+降低表面电场区域和隐埋P+降低表面电场区域；
使用单晶硅实现所述体半导体衬底和PNP和NPN器件区域两者；和
使用深槽隔离区域围绕每个晶体管，以使所述互补的PNP和NPN结构彼此隔离。
10.一种形成权利要求9的互补的PNP和NPN结构，其中所述PNP进一步包括：
执行第一掩膜操作并且将高掺杂n层注入所述p型体半导体衬底中，其中所述高掺杂n层垂直地在所述PNP区的下方，并且向所述深槽隔离延伸并且与所述深槽隔离接触；
执行第二掩膜操作和注入步骤，所述第二掩膜操作和注入步骤在焊盘氧化之后氮化物沉积之前被执行，以在所述有源器件区域创建均匀的集电极掺杂水平；
执行第三掩膜操作和蚀刻步骤，以提供用于限定在所述有源器件区域中的浅槽绝缘层即STI层的区域的硬掩膜；
形成深槽隔离，以包围所述PNP晶体管和所述高掺杂n层，其中所述沟槽在所述高掺杂n层的底部以下延伸，并且延伸到管芯的顶部；
注入p型阱，所述p型阱延伸穿过所述STI层，并且接触所述有源器件层的集电极，其中集电极触点耦合到所述注入p型阱；
注入深n型阱，所述深n型阱从所述晶片的顶部延伸穿过所述STI层和所述有源器件层，接触所述高掺杂n层，其中VCC触点耦合到所述注入深n型阱；
使用所述有源器件区域的顶部上的相反导电性类型的杂质来沉积、限定和掺杂基极外延半导体层，其中基极触点耦合到所述基极外延半导体层；和
沉积发射极区域，所述发射极区域覆盖所述基极外延半导体层的一部分，其中所述发射极区域被高掺杂以与所述有源器件区域相同的导电类型。
11.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中所述PNP有源器件区域具有＜3e14 1/cm3的受主掺杂和3到4um的厚度。
12.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中所述PNP区中的所述隐埋N+降低表面电场区域被注入以3e16至3e18 1/cm3的施主剂量。
13.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中所述NPN进一步包括：
执行第一掩膜操作并且将高掺杂p层注入所述p型体半导体衬底中，其中所述高掺杂p层垂直地在所述NPN区的下方，并且向所述深槽隔离延伸并且与所述深槽隔离接触；
执行第二掩膜操作和注入步骤，所述第二掩膜操作和注入步骤在焊盘氧化之后氮化物沉积之前被执行，以在所述有源器件区域创建均匀的集电极掺杂水平；
执行第三掩膜操作和蚀刻步骤，以提供用于限定在所述有源器件区域中的浅槽绝缘层即STI层的区域的硬掩膜；
形成深槽隔离，以包围所述NPN晶体管和所述高掺杂p层，其中所述沟槽在所述高掺杂p层的底部以下延伸，并且延伸到管芯的顶部；
注入n型阱，所述n型阱延伸穿过所述STI层，并且接触所述有源器件层的所述集电极，其中集电极触点耦合到该注入n型阱；
注入深p型阱，所述深p型阱从所述晶片的顶部延伸穿过所述STI层和所述有源器件层，所述注入深p型阱接触所述高掺杂p层，其中GND触点耦合到所述注入深p型阱；
使用所述有源器件区域的顶部上的相反导电性类型的杂质来沉积、限定和掺杂基极外延半导体层，其中基触点耦合到所述基极外延半导体层；和
沉积发射极区域，所述发射极区域覆盖所述基极外延半导体层的一部分，其中所述发射极区域被高掺杂以与所述有源器件区域相同的导电性类型。
14.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中所述NPN有源器件区域具有＜3e14 1/cm3的施主掺杂和3到4um的厚度。
15.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中所述NPN区中的所述隐埋P+降低表面电场区域被注入以3e16至3e18 1/cm3的受主剂量。
16.根据权利要求9所述的形成互补的PNP和NPN结构的方法，其中被包括在所述PNP晶体管下方的隐埋N+降低表面电场区域和在所述NPN下方的隐埋P+降低表面电场区域分别通过深n型和p型阱耦合到所述晶片的所述顶部并且分别偏置于Vcc和GND，其中所述偏置将消耗所述PNP和NPN集电极区域两者的横向部分，并且因此将增加所述PNP和NPN集电极区域的BV。
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