CN113270490A - 一种pnp型双极晶体管制造方法 - Google Patents

一种pnp型双极晶体管制造方法 Download PDF

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CN113270490A
CN113270490A CN202110551865.7A CN202110551865A CN113270490A CN 113270490 A CN113270490 A CN 113270490A CN 202110551865 A CN202110551865 A CN 202110551865A CN 113270490 A CN113270490 A CN 113270490A
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P·舍瓦利耶
G·阿弗尼耶
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STMicroelectronics Crolles 2 SAS
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Abstract

一种与制造NPN、NMOS、和PMOS晶体管并行地制造PNP晶体管的方法，该PNP双极晶体管制造方法包括以下连续步骤：在P型掺杂半导体衬底上沉积第一半导体层，该第一半导体层被划分为第一、第二和第三区域；向该衬底中深注入绝缘阱；在所述第二和第三区域与所述绝缘阱之间注入分别为第一N型、第二P型和第三P型掺杂阱；在该第三区域上沉积第一绝缘层以及在该第一绝缘层上方可选择性蚀刻的第二绝缘层，并且创建掩膜；在该掩膜中选择性外延第二P型掺杂半导体层。

Description

一种PNP型双极晶体管制造方法
本申请是于2017年2月24日提交的申请号为201710104749.4、题为“一种PNP型双极晶体管制造方法”的发明专利申请的分案申请。
本申请要求于2016年7月22日提交的法国专利申请号16/57067的优先权权益，其内容在法律允许的最大程度上通过引用以其全文结合在此。
背景技术
本公开涉及一种制造PNP型双极晶体管的方法，并且更具体地涉及在所谓的BiCMOS技术中一种与同时制造NPN型双极晶体管、N沟道MOS晶体管、以及P沟道MOS晶体管兼容的制造PNP型双极晶体管的方法。
相关技术
制造各种类型的双极晶体管以及各种类型的MOS晶体管的各种方法是已知的。这类方法通常被提供以用于减少制造步骤的数量并且用于优化这些晶体管中的每个晶体管。
在此提供了一种最小化步骤数量并且优化PNP型和NPN型双极晶体管的性能的方法。PNP型双极晶体管的期望性能例如是高于100的增益以及大于25GHz的转换频率。NPN型双极晶体管的期望性能例如是大于300Ghz的截止频率。
发明内容
因此，实施例提供了一种与制造NPN型双极晶体管以及N沟道和P沟道MOS晶体管并行地制造PNP型双极晶体管的方法，方法在制造所述PNP型双极晶体管时包括以下连续步骤：a)在P型掺杂半导体衬底上沉积第一N型掺杂半导体层，该第一N型掺杂半导体层由绝缘层划分为第一、第二该和第三区域；b)向该衬底中深注入N型掺杂绝缘阱；c)在该第一区域与该绝缘阱之间注入第一N型掺杂阱；d)向该衬底中在该第二区域与该绝缘阱之间注入第二P型掺杂阱；e)向该衬底中在该第三区域与该绝缘阱之间注入第三P型掺杂阱，该第三阱形成该晶体管的集电极；f)在该第三区域上沉积第一绝缘层以及在该第一绝缘层上方可选择性蚀刻的第二绝缘层，并且在该第三区域的一部分上创建开口；g)在该开口中选择性外延第二P型掺杂半导体层，该第二层形成该晶体管的发射极，并且移除该第一和第二绝缘层；h)向该第一区域中注入N型掺杂剂原子；以及i)向该第二区域中注入P型掺杂剂原子，步骤a)、b)、c)、d)、i)、j)对N沟道和P沟道MOS晶体管制造步骤而言是相同的。
根据实施例，在步骤e)，通过深注入第四P型掺杂阱并且通过注入第五P型掺杂阱来执行对该第三阱的注入。
根据实施例，该第二层进一步掺杂有碳原子。
根据实施例，该方法进一步包括步骤i)之后的步骤j)：在该第一、第二和第三区域的上表面以及该第二层的上表面上形成硅化区域。
根据实施例，该方法进一步包括步骤i)之后的步骤k)：在该第二层的横向边缘上形成间隔物。
根据实施例，在步骤g)，通过湿蚀刻来移除该第一和第二绝缘层。
根据实施例，在步骤a)，通过外延来沉积该第一半导体层。
根据实施例，该第一绝缘层是氧化硅层，并且该第二绝缘层是氮化物层。
根据实施例，绝缘材料是氧化硅。
根据实施例，该衬底由硅制成。
另一实施例提供了一种PNP型双极晶体管，该晶体管包括发射极，该发射极具有矩形横截面，相对于该晶体管的基极被抬起，并且具有受间隔物保护的横向表面，该晶体管进一步包括在该基级的由这些间隔物界定的重掺杂N型部分上形成的基极触头。
将结合附图在具体实施例的以下非限制性描述中详细讨论前述和其他特征以及优势。
附图说明
图1至图21是横截面视图，展示了制造PNP型双极晶体管和NPN型双极晶体管的方法的实施例的连续步骤。
具体实施方式
为了清楚起见，相同部件在各个附图中以相同的参考标号标示，并且各个附图并不按比例绘制。为清楚起见，仅示出并详述对于理解所描述的实施例有用的那些步骤和元件。
在以下描述中，当参考限定绝对位置的术语(比如术语“左侧”、“右侧”等)或者参考限定相对位置的术语(诸如术语“顶部”、“下部”以及“上部”等)时，参考附图的朝向。除非另外指明，否则表达“大约”和“基本上”意指在10％内，优选地在5％内。
图1至图21是横截面视图，展示了制造PNP型双极晶体管和NPN型双极晶体管的方法的连续步骤。该方法进一步使得能够同时形成N沟道MOS晶体管和P沟道MOS晶体管，但是在此不详述MOS晶体管形成步骤。
已经在图1至图21中的每张图的右侧部分示出了制造PNP型双极晶体管的步骤，并且已经在图1至图21中的每张图的左侧部分示出了制造NPN型双极晶体管的步骤。
图1展示了制造PNP型和NPN型双极晶体管的方法的步骤。初始结构是当前由硅制成的P型掺杂半导体层1。在半导体支撑件上形成以下被称作衬底的层1。该半导体支撑件例如是轻N型掺杂。例如，层1是通过外延形成的。在衬底1中在期望形成NPN型晶体管的位置处形成N型掺杂半导体阱3。阱3是由衬底1的上表面形成的。在衬底1的上表面以及在阱3的上表面上通过外延来沉积N型掺杂半导体层5。作为示例，层5具有范围从200nm到600nm的厚度，例如，大约400nm。
在图2的步骤处，跨层1的整个厚度(例如，范围从2μm至6μm，典型地大约4μm)来形成深绝缘沟槽7(DTI)。沟槽7环绕PNP晶体管制造区域和NPN晶体管制造区域(虽然在图1至图21的右侧未示出该沟槽)。
在图3的步骤处，至少在区域11和区域13中由浅绝缘沟槽9(“浅沟槽绝缘”，STI)对层5位于阱3上的部分进行划分。区域11和13具有基本上相同的宽度。由沟槽9’将层5位于衬底1上的部分划分为三个区域15、17和19。区域15比具有基本上相同宽度的区域17和19更宽。
在图4的步骤处，通过向衬底1中深注入PNP型晶体管制造区域来形成N型掺杂阱21。阱21形成在衬底1的下表面侧并且在PNP型双极晶体管制造区域的整个宽度下方延伸。
在图5的步骤处，通过向阱3注入NPN型双极晶体管制造区域来形成重掺杂N型阱23。阱23形成在阱3的上表面下方并与阱的上表面相接触，并且朝向阱3的下部分延伸。阱23定位在层5的区域11下方。
在图6的步骤处，通过向衬底1中注入PNP型双极晶体管制造区域来形成N型掺杂阱25和P型掺杂半导体阱27。阱25和阱27相邻，并且从衬底1的上表面向阱21延伸。N型掺杂阱25在层5的区域19下方延伸。P型掺杂阱27在层5的区域17下方延伸。当然，为了节省制造步骤，可以在与N型阱23相同的时间形成N型阱25。
在图7的步骤处，在结构的上表面上相继沉积绝缘层29和多晶硅层31。层29和31进一步用于形成与双极晶体管并行制造的MOS晶体管的绝缘栅。作为示例，绝缘层29由氧化硅或氮氧化物制成。
在图8的步骤处，通过对NPN型和PNP型双极晶体管制造区域以上的结构进行掩膜来移除多晶硅层31。在图9至图19中示出的制造步骤特定于制造双极晶体管。在附图的左侧，在层5的区域13的中心部分中形成具体地N型掺杂半导体阱33。阱33旨在形成NPN型双极晶体管的子集电极区域(“选择性注入集电极”，SIC)。阱33均跨层5的区域13的厚度而延伸。
在图9的步骤处，在附图的右侧，通过向衬底1中深注入形成P型掺杂半导体阱35。阱35形成在阱21的上表面并且在沟槽7与阱27之间横向延伸。阱35定位在层5的区域15下方，但并不与其相接触。阱35形成PNP型双极晶体管的非本征集电极。
在图10的步骤处，通过向衬底1中注入PNP型双极晶体管制造区域来形成P型掺杂阱37。阱37形成在阱35的上表面与层5的区域15的下表面之间。阱37未与阱27横向接触。阱37形成PNP型双极晶体管的本征集电极。完整集电极具有范围从800nm到1200nm的厚度，例如，大约950nm。
在图11的步骤处，通过对NPN和PNP型双极晶体管制造区域的上表面进行掩膜来移除绝缘层29。绝缘层39和重掺杂的P型多晶硅层41沉积在结构的上表面上。对层41进行沉积以便形成NPN型双极晶体管的非本征基极。作为示例，层39是由氧化硅或氮氧化物制成的。
在图12的步骤处，在层41的上表面上相继沉积两个绝缘层43和45以及一个抗蚀层47。作为示例，绝缘层是由氧化硅和氮化硅制成的。在树脂层47中形成蚀刻掩膜。在层41、43和45中在阱33上方形成具有宽度小于阱33的宽度的开口49。
在图13的步骤处，在移除抗蚀层47之后，通过沉积并蚀刻氮化硅层来形成间隔物50以便保护开口49的壁。通过在开口49的底部进行湿蚀刻来移除氧化硅层39的一部分。通过在阱33上方在介质材料上进行选择性外延生长来形成例如由硅锗制成的半导体层51。层51形成在阱33和层5的区域13上并且跨宽度大于开口49的宽度而延伸。因此，层51通过其上表面与形成NPN晶体管的集电极的阱33相接触，并且通过其上表面的外围与形成NPN晶体管的非本征基极的重掺杂P型层41相接触。层51形成NPN晶体管的本征基极。
在图14的步骤处，在附图的左侧形成NPN型双极晶体管的发射极。为了实现这一点，先前形成了被定位在开口49的壁的底部且抵靠开口的壁的两个绝缘间隔物53。间隔物53在层51上界定了具有范围从50nm至100nm的基本维度的开口。作为示例，间隔物53由氧化硅制成。在结构的上表面上相继沉积重掺杂的N型半导体层55和抗蚀层57。然后通过蚀刻来移除层45、55、和57以便在结构的上表面仅留下该层的一部分。层45、55、和57的剩余部分具有与层5的区域13的宽度相类似的宽度。层55形成NPN型双极晶体管的发射极触头。层55与形成同一晶体管的本征基极的层51相接触。
在图15的步骤处，移除抗蚀层57，并且在结构的上表面上沉积另一抗蚀层61。在抗蚀层61中形成新的蚀刻掩膜。该蚀刻掩膜使得能够在结构的上表面仅留下层39和41的一部分。层39和41的剩余部分定位在层5的区域13上，但具有比区域13的宽度更大的宽度。然后移除抗蚀层61。
在图16的步骤处，在结构的上表面沉积绝缘层63以及在绝缘层63上方可选择性蚀刻绝缘层65。作为示例，绝缘层63是氧化硅层，并且绝缘层65是氮化硅层。
在图17的步骤处，在附图的右侧，通过在层63和65中进行掩膜来形成开口67。开口67形成在层5的区域15的一部分之上并且跨绝缘层63和65的整个厚度而延伸。通过在开口67中进行选择性外延来形成重掺杂的P型半导体层69。层69是PNP型双极晶体管的发射极。层69可以掺杂有碳原子以便减少碳原子在结构的剩余部分中扩散。沉积层69使得能够优化PNP型双极晶体管的发射极的掺杂分布。进一步地，在开口67中沉积层69，这使得能够控制发射极的形态。实际上，PNP型双极晶体管的最终发射极和基极触头将关闭，并且在图20的步骤处，间隔物可以形成在层69的各侧，该间隔物将PNP型双极晶体管的发射极和基极触头绝缘。进一步地，对层69进行沉积具有低热预算并且不热影响形成NPN型双极晶体管的基极的层51的掺杂。
在图18的步骤处，例如，通过湿蚀刻来移除绝缘层63、65。在结构的上表面沉积新的绝缘层71。在对MOS晶体管栅极进行掺杂的步骤过程中，层71保护NPN和PNP型双极晶体管。一旦完成这些步骤，则移除层71。
在图19的步骤处，从整个结构中移除层29和31，并且图19、图20、和图21中所展示的步骤对双极晶体管制造和MOS晶体管制造而言是相同的。
在图20的步骤处，在双极晶体管的发射极的外部侧表面形成双间隔物73。除双间隔物73之外，层41的宽度能够接收硅化区域，该硅化区域接收NPN型双极晶体管的基极触头。这些间隔物例如是由氮化物层和氧化硅层形成的。N型掺杂剂原子同时被注入到层5的区域11的中心部分75中、注入到层5的区域15的部分77中以及注入到层5的区域19中。部分77定位在区域15的一端。区域11的中心部分75提高NPN型双极晶体管的集电极触头。区域15的部分77提高PNP型双极晶体管的基极触头。区域19提高PNP型双极晶体管的绝缘触头。在层5的区域17中注入P型掺杂剂原子。区域17提高PNP型双极晶体管的集电极触头。
在图21的步骤处，硅化区域E1、B1、C1、E2、B2、C2和ISO形成在双极晶体管的接触区域上。硅化区域E1形成在层55的上表面上并且形成NPN型双极晶体管的发射极触头。硅化区域B1形成在层41的可见上表面上并且形成NPN型双极晶体管的基极触头。硅化区域C1形成在层75的上表面上并且形成NPN型双极晶体管的集电极触头。硅化区域E2形成在层69的上表面上并且形成PNP型双极晶体管的发射极触头。硅化区域B2形成在层5的部分77的上表面上并且形成PNP型双极晶体管的基极触头。硅化区域C2形成在层5的区域17的上表面上并且形成PNP型双极晶体管的集电极触头。硅化区域ISO形成在层5的区域19的上表面上并且形成与PNP型双极晶体管的阱21的接触。然后在硅化区域上沉积电触头。
作为示例，可以利用下表中给出的掺杂水平来形成先前描述的方法。
针对PNP型双极晶体管：
Figure BDA0003075443890000081
针对NPN型双极晶体管：
Figure BDA0003075443890000082
Figure BDA0003075443890000091
作为示例，在上述掺杂水平的情况下，由在此描述的制造方法制造的PNP晶体管具有范围从100到220的增益以及范围从30Ghz到45Ghz的转换频率。
这样的变更、修改和改进旨在是本公开的一部分，并且旨在在本发明的精神和范围内。从而，前文描述仅为举例而并非旨在是限制性的。仅如以下权利要求书及其等效物中所界定的那样限定本发明。

Claims (5)

1.一种集成电路NPN型双极晶体管，包括：
集电极，由N型掺杂阱形成，所述N型掺杂阱由浅沟槽隔离横向界定；
绝缘层，在所述浅沟槽隔离之上延伸并且包括第一开口；
基极，由在所述第一开口内并与所述N型掺杂阱的顶部接触的外延P型掺杂区域形成，所述外延P型掺杂区域具有上表面；
非本征基极，由P型掺杂的多晶硅层形成，所述P型掺杂的多晶硅层与所述绝缘层的顶部表面接触并与所述外延P型掺杂区域的所述上表面接触而延伸，所述P型掺杂的多晶硅层包括在所述外延P型掺杂区域的所述上表面之上的第二开口；
间隔物，保护所述第二开口的横向表面；
发射极，由外延N型区域形成，所述外延N型区域包括第一部分和第二部分，所述第一部分延伸通过所述间隔物中的开口以接触所述外延P型掺杂区域的所述上表面，所述第二部分由所述间隔物横向界定；
其中所述非本征基极包括与所述发射极和所述间隔物横向偏移的基极接触表面。
2.根据权利要求1所述的晶体管，还包括：
第一硅化层，在针对所述发射极的所述外延N型区域的顶部上；以及
第二硅化层，在所述基极接触表面的顶部上。
3.根据权利要求2所述的晶体管，还包括：
另外的N型掺杂阱，形成在所述集电极的所述N型掺杂阱中；
第三硅化层，在所述另外的N型掺杂阱的更重掺杂的N型区域的顶部上；
其中所述更重掺杂的N型区域是与所述集电极的所述N型掺杂阱隔离的浅沟槽。
4.一种集成电路NPN型双极晶体管，包括：
集电极，由N型掺杂阱形成，所述N型掺杂阱由浅沟槽隔离横向界定；
基极，由与所述N型掺杂阱的顶部接触的外延P型掺杂区域形成，所述外延P型掺杂区域具有上表面；
非本征基极，由P型掺杂的多晶硅层形成，所述P型掺杂的多晶硅层在所述浅沟槽隔离之上延伸并与所述外延P型掺杂区域的所述上表面接触，所述P型掺杂的多晶硅层包括在所述外延P型掺杂区域的所述上表面之上的开口；
间隔物，保护所述开口的横向表面；
发射极，由外延N型区域形成，所述外延N型区域包括第一部分和第二部分，所述第一部分延伸通过所述间隔物中的开口以接触所述外延P型掺杂区域的所述上表面，所述第二部分由所述间隔物横向界定；
其中所述非本征基极包括与所述发射极和所述间隔物横向偏移的基极接触表面；
另外的N型掺杂阱，形成在所述集电极的所述N型掺杂阱中；以及
更重掺杂的N型区域，在所述另外的N型掺杂阱之上并与所述另外的N型掺杂阱接触；
其中所述更重掺杂的N型区域是与所述集电极的所述N型掺杂阱隔离的浅沟槽。
5.根据权利要求4所述的晶体管，还包括：
第一硅化层，在针对所述发射极的所述外延N型区域的顶部上；
第二硅化层，在所述基极接触表面的顶部上；以及
第三硅化层，在所述更重掺杂的N型区域的顶部上。
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