CN104956782A - 集成电路模块 - Google Patents
集成电路模块 Download PDFInfo
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- CN104956782A CN104956782A CN201480003922.6A CN201480003922A CN104956782A CN 104956782 A CN104956782 A CN 104956782A CN 201480003922 A CN201480003922 A CN 201480003922A CN 104956782 A CN104956782 A CN 104956782A
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Abstract
一种集成电路装置,包括基本上定位在第一平面中的大致平坦管芯附接焊盘(DAP)130;和基本上定位在第二平面中的大致平坦引线条160,其中,第二平面在第一平面上方且平行于第一平面,并且大致平坦引线条160具有至少一个向下且向外延伸的引线条引线162从其突出并基本上终止在第一平面中;具有多个大致平坦触点焊盘30和多个引线50的顶部引线框12,其中,触点焊盘30基本上定位在位于第二平面上方且平行于第二平面的第三平面中,引线50具有连接到触点焊盘30的近端部分60并具有基本上终止在第一平面中、向下且向外延伸的远端部分62;连接到顶部引线框12和DAP 130的IC管芯72;以及封装DAP 130、引线条162、顶部引线框12和IC管芯72的至少部分的封装材料200。
Description
背景技术
集成电路(IC)封装通常包括附接到引线框的IC管芯,引线框使得管芯上的触点能够附接到外部电路。管芯和引线框部分常常封装在环氧树脂或保护管芯和引线框的其他材料的覆盖件中。由于IC管芯随时间变小,管芯上的触点的数量和密度变大。因此,在IC封装件内的信号路由和IC封装件的散热已经具有挑战性。一项最近的开发是双引线框IC封装件,在该双引线框IC封装件中,在单个封装件中设置一个以上的引线框以增多信号路由选项。但是,双引线框封装件常常对自身造成增加的挑战,诸如两个引线框彼此发生不期望的电接触的趋向。这种接触可能导致短路和封装失败。
附图说明
图1是顶部引线框带和倒装芯片管芯的底部透视图。
图2是图1的引线框带的底部透视图,其中倒装芯片安装在每个引线框上。
图3是顶部引线框带和底部引线框带在附接之前的顶部透视图。
图4是附接的顶部及底部引线框带和附接在顶部及底部引线框带之间的倒装芯片管芯的顶部透视图,并且还示出离散电路部件安装在一个顶部引线框上。
图5是图4的附接的顶部及底部引线框带的顶部透视图,其中离散电路部件安装在其每个顶部引线框上。
图6是三个封装的双引线框组件诸如图5所示组件的顶部透视图。
图7是从模塑的双引线框组件诸如图6所示组件分割的集成电路封装件的剖面侧视图。
图8是图7所示集成电路封装件的底部透视图。
图9是图7和图8所示集成电路封装件的顶部透视图。
图10是制作集成电路模块的方法的一个实施例的流程图。
具体实施方式
图1示出具有整体连接的顶部引线框12、14、16、18的顶部引线框带10。顶部引线框带10具有底表面22和顶表面24(如图3所示)。每个顶部引线框12、14等具有多个大致共面的触点焊盘部分30,所述触点焊盘部分30包括单独的触点焊盘31、32、33、34、36、38等。触点焊盘中的一些(例如31、33等)安装在每个顶部引线框(例如,12)的大致矩形的管芯安装区域37中。每个引线框还包括多个外围引线部分50,这些外围引线部分50可以包括多个相对大的引线部分52、54、56、58和多个相对小的引线部分53、55、57等。一个或更多个内部引线部分59也可以设置在每个顶部引线框12等上。内部引线部分59可以附接到底部引线框110的管芯附接焊盘(DAP)部分130,如以下描述的。每个外围引线部分50具有附接到至少一个触点焊盘部分30的近端60,并且还包括向下且向外延伸的远端62。至少一些外围引线部分50包括连接器延伸部64、65,该连接器延伸部64、65可以具有大致倒U形或倒L形,这取决于是否存在相邻连接引线框。连接器延伸部64、65有助于顶部引线框带10附接到底部引线框带110,如图3所示。连接器延伸部64、65可以包括适于帮助顶部引线框带10和底部引线框带110之间的连接的其他形状。
参考图1和图2,多个倒装芯片72、74、76、78分别安装在顶部引线框12、14、16、18上。每个倒装芯片具有第一侧或活动侧82(activeside)和第二侧或非活动侧84,如图7的剖视图最佳看到的。活动侧82具有以矩形网格图案形成于其上的多个焊料凸块85、87、89等。每个焊料凸块在回流加热期间接合到管芯安装区域37中的相关联触点焊盘部分(例如,31、33)。顶部引线框带10可以被移动到回流焊炉(未示出)以将倒装芯片72等焊接到顶部引线框12等,当在图2所示的构造中时,这在顶部引线框带10附接到底部引线框带之前发生。
图3示出具有互连的底部引线框112、114、116、118的底部引线框带110。底部引线框带110具有顶表面122和底表面124。管芯附接焊盘(DAP)部分130连接到外围框架部分132,该外围框架部分132可以由多个伸长的框架构件134、136、138、142形成。每个DAP部分130由关联的外围框架部分132限制。DAP部分130通过多个系杆152、154、156、158连接到周边外围框架部分132。每个底部引线框112、114等包括伸长的引线条160,该引线条160定位在与DAP部分130、外围框架部分132和系杆部分152等所定位的平面平行且在此平面上方的平面中。第一引线条引线部分162和第二引线条引线部分164附接到引线条160的相对端部。引线条引线部分162、164与关联的外围框架部分132的伸长侧构件134一体形成,并且在其远端处附接到所述伸长侧构件134。因此,每个引线条引线部分162、164处的远端168基本上定位在与DAP部分130和外围框架部分132相同的平面中。当顶部及底部引线框(例如,16、116)如下述连接时,引线条160基本上定位在与顶部引线框触点焊盘部分30相同的平面中,并与触点焊盘部分30中的至少一个的底表面结合。
在倒装芯片72、74、76、78附接到顶部引线框带10之后,顶部引线框带10(底表面22向下)附接到底部引线框带110以形成双引线框带170。在一个实施例中,这是通过将焊膏放置在外围框架部分132和底部引线框带110的引线条160上,然后定位顶部引线框外围引线部分50的连接器延伸部64、65以使它们接触关联的外围框架部分132,以及定位底部引线框引线条160使其接触顶部引线框触点焊盘部分130实现的。通过引线部分连接器延伸部64、65与外围框架部分132的正定位结合(positive and locating engagement),顶部引线框带10“嵌套”在底部引线框带110上。顶部引线框外围引线部分50中的每个的远端62和引线条引线部分162、164充当图4所示双引线框带组件170中的竖直隔离件。顶部引线框10、12等的外围引线部分50还与底部引线框110、112等的外围框架部分132共同动作,以用于引线框的合适横向和角度定位。引线远端部分62和引线条引线部分162、164将顶部引线框触点焊盘部分30保持在底部引线框DAP部分130和外围框架部分132上方的预定高度处。引线远端部分62还将触点焊盘部分30相对于每个底部引线框112、114、116、118的外围框架部分132保持大致横向居中的关系。
接着,如图4进一步所示,多个离散部件(可以为无源电路部件182、184、186)可以安装在每个顶部引线框12、14、16、18的顶表面上。这可以通过首先对每个顶部引线框的关联触点焊盘部分30施加焊膏完成。接着通过将双引线框带170放置在回流炉中,离散的电路部件182、184、186被焊料接合到关联的顶部引线框(例如,16)。在一种方法中,每个离散部件182、184、186下方的焊膏的回流加热可以与外围框架部分132等上的焊膏的回流同时发生。在另一个实施例中,在离散构件182、184、186被放置在关联的顶部引线框(例如,16)上之前,底部引线框上的焊膏在第一操作中被回流。图5示出将离散部件182、184、186安装在每个顶部引线框12、14、16、18上之后的双引线框带170。
接着,图5的双引线框组件放置在支撑框架194上,如图6所示,并被移动到封装站(诸如压铸模站),其中在该封装站处将塑封材料施加到双引线框带组件170以提供封装的双引线框带190。顶部引线框带10及底部引线框带110和倒装芯片72、74等以及无源电路部件182、184、186的至少部分被封装材料200覆盖,所述封装材料200(诸如常规塑封材料)固化以提供硬保护覆盖件。因此形成的封装的双引线框带190可以是各种尺寸和长度,这取决于初始附接在一起的顶部引线框10及底部引线框110的尺寸和长度。图6所示的封装的双引线框带190具有由封装材料200覆盖的三个2x2双引线框组件170。封装的双引线框带190具有大致平坦的顶表面192和平坦的底表面(未示出)以及侧表面195。196处示出的虚线代表三个4x4封装的双引线框带190的边界。每个4x4封装引线框组件190然后被沿着切割道100、101、102、103(图1至图5)围绕每个单独的附接的顶部及底部引线框组件(例如,12、112)分割。
如图7、图8、和图9最佳示出的,封装的双引线框带190的分割提供多个单独的集成电路(IC)封装件210,每个封装件具有平坦的顶面212、平坦的底面214和多个平坦的侧面216。DAP部分130的底表面131在每个IC封装件的底面214处暴露。而且,在底面214和侧面216上暴露的是顶部引线框引线部分50的底表面部分66和端子端表面部分68,包括较小的引线部分53、55等以及较大的引线部分52、54等。暴露的还有底部引线框引线部分162、164的表面部分。DAP部分130的暴露的底表面131可以与封装层200的底面214基本上齐平。顶部引线框外围引线50的分离的远端部分62的暴露表面以及每个引线条引线部分162、164的分离的远端部分168的暴露表面,可以与封装层200的底面214和侧面216基本上齐平。
作为上述将每个顶部引线框(例如,12)附接到每个底部引线框(例如,112),以及外围引线部分50的外端和附接的外围框架部分132的后续分割和移除的方法的结果,如图7示出,在DAP部分130与最近、向外延伸的外围引线部分50之间提供明显的间隙92。因此,避免了顶部引线框引线与底部引线框的不期望接触以及短路的一般双引线框问题。还应当理解,通过提供所述底部引线框引线条构造或类似结构,向封装件设计者提供附加的信号路由选项。尽管在具体描述的实施例中,只提供一个引线条和两个附加引线,但应当理解,可以提供附加引线并因此提供附加信号路由选项。
图10示出制作集成电路封装件的方法。如图10所示,该方法包括如在框231处示出的,提供顶部引线框带10,该顶部引线框带10包括多个整体连接的顶部引线框12、14等。该方法还包括,如在框232处示出的,将多个倒装芯片管芯72、74等安装在顶部引线框带10上,其中每个倒装芯片管芯的焊料凸块85、87等接合到顶部引线框12、14等中的每个上的预定触点焊盘部分30。该方法还包括,如在233处示出的,提供底部引线框带110,该底部引线框带110包括多个整体连接的底部引线框112、114等,每个具有中心管芯附接焊盘(DAP)部分130和外围框架部分132。该方法还包括,如在框234处示出的,将顶部引线框带10附接到底部引线框带110,其中每个倒装芯片管芯72等的背面84接触每个底部引线框112、114等的DAP部分130,并且其中每个顶部引线框12、14等的外围引线部分50附接到每个底部引线框112、114等的外围框架部分132。
本发明相关领域的技术人员应当理解,在所要求保护的发明的范围内,所述实施例可作出修改,并且许多其他实施例是可能的。
Claims (20)
1.一种集成电路装置,即IC装置,其包括:
基本上定位在第一平面中的大致平坦管芯附接焊盘,即大致平坦DAP;
基本上定位在第二平面中的大致平坦引线条,其中所述第二平面在所述第一平面上方且平行于所述第一平面,并且所述大致平坦引线条具有至少一个向下且向外延伸的引线条引线从其突出并基本终止在所述第一平面中;
包括多个大致平坦触点焊盘和多个引线的顶部引线框,其中所述触点焊盘基本上定位在位于所述第二平面上方且平行于所述第二平面的第三平面中,所述引线具有连接到所述焊盘部分的近端部分并具有基本上终止在所述第一平面中、向下且向外延伸的远端部分;
具有多个电触点和表面的IC管芯,其中所述电触点连接到所述顶部引线框的所述多个触点焊盘中的至少一些,所述表面附接到所述DAP;和
封装所述DAP、所述引线条、所述顶部引线框以及所述IC管芯的至少部分的封装材料。
2.根据权利要求1所述的装置,所述IC管芯包括倒装芯片,所述倒装芯片具有第一侧并具有第二侧,其中所述第一侧在其上具有操作性电连接到所述顶部引线框的所述多个触点焊盘中的一些的多个焊料凸块,所述第二侧与所述第一侧相对且包括连接到所述DAP的所述表面。
3.根据权利要求1所述的装置,所述顶部引线框包括至少一个引线,所述引线具有连接到所述多个触点焊盘中的至少一个的近端和连接到所述DAP的远端。
4.根据权利要求1所述的装置,所述大致平坦引线条连接到所述顶部引线框。
5.根据权利要求1所述的装置,至少一个无源部件电气地且物理地连接到所述顶部引线框上的所述触点焊盘中的至少一个。
6.根据权利要求1所述的装置,所述封装层具有大致矩形的盒状形状,具有大致平坦顶面、底面和侧面,其中所述DAP的底表面在所述底面处暴露,并且所述多个顶部引线框引线的所述远端部分和所述至少一个向下且向外延伸的引线条引线的远端部分在所述封装层的所述底面和所述侧面处暴露。
7.根据权利要求6所述的装置,所述DAP的暴露底表面与所述封装层的所述底面基本上齐平,并且所述顶部引线框引线的所述远端部分的暴露表面和所述引线条引线的所述远端部分的暴露表面与所述封装层的所述底面和所述侧面基本上齐平。
8.一种集成电路装置,即IC装置,其包括:
底部引线框,包括:
基本上定位在第一平面中的大致平坦外围框架部分;
由所述外围框架部分限制且基本上定位在所述第一平面中的大致平坦管芯附接焊盘部分,即大致平坦DAP部分;和
具有连接到所述外围框架部分的第一端部和从所述外围框架部分向上且向内定位的第二端部的至少一个底部引线框引线部分;
顶部引线框,包括:
基本上定位在第二平面中的多个大致平坦触点焊盘部分,其中所述第二平面平行于所述第一平面且在所述第一平面上方;和
多个向下且向外延伸的顶部引线框外围引线部分,其具有连接到所述触点焊盘的近端和连接到所述底部引线框外围框架部分的远端;
其中所述底部引线框引线部分的所述第二端部连接到所述顶部引线框。
9.根据权利要求8所述的装置,其中所述向外延伸的顶部引线框引线部分的所述远端部分包括一体形成的连接器延伸部,所述外围框架部分在距离所述触点焊盘部分预定距离的位置处嵌套在所述引线部分的所述连接器延伸部中。
10.一种制作集成电路装置即IC装置的方法,包括:
提供包括多个整体连接的顶部引线框的顶部引线框带;
将多个倒装芯片管芯安装在所述顶部引线框带上,其中每个倒装芯片的焊料凸块接合到所述顶部引线框中的每个顶部引线框上的预定焊盘部分;
提供包括多个整体连接的底部引线框的底部引线框带,其中每个所述底部引线框具有中心管芯附接焊盘部分即中心DAP部分和外围框架部分;以及
将所述顶部引线框带附接到所述底部引线框带,其中每个倒装芯片管芯的背面接触每个底部引线框的所述DAP部分,并且其中每个顶部引线框的引线部分附接到每个底部引线框的所述外围框架部分。
11.根据权利要求10所述的方法,进一步包括将所述倒装芯片管芯和每个顶部引线框带和底部引线框带的至少一部分封装在塑封材料中。
12.根据权利要求11所述的方法,进一步包括分离并移除每个底部引线框的所述外围框架部分和附接到其的所述顶部引线框引线部分的部分。
13.根据权利要求12所述的方法,其中所述分离和移除包括将所述封装的倒装芯片管芯和顶部引线框带以及底部引线框带分割成多个IC封装件,每个所述IC封装件具有暴露的管芯焊盘表面并具有多个暴露的引线表面,所述引线表面与所述塑封材料的侧面和所述底面的分离表面齐平。
14.根据权利要求10所述的方法,进一步包括将至少一个无源电路部件安装在所述多个顶部引线框中的每个顶部引线框上。
15.根据权利要求10所述的方法,其中所述附接包括用焊料将所述顶部引线框带接合到所述底部引线框带,包括用焊料将每个顶部引线框上的引线接合到每个底部引线框上的DAP。
16.根据权利要求15所述的方法,进一步包括以下列方式将所述顶部引线框带和底部引线框带分割成多个IC模块:暴露与所述底部引线框一体形成的至少一个引线和与所述顶部引线框一体形成的至少一个引线的剖面部分。
17.根据权利要求10所述的方法,其中所述提供底部引线框带包括提供多个整体连接的底部引线框,每个底部引线框具有中心管芯附接焊盘即中心DAP和外围框架组件,所述外围框架组件布置在围绕所述DAP并与所述DAP呈基本上共面关系的大致矩形构造中,并且其中DAP系结构件将所述DAP附接到所述外围框架。
18.根据权利要求17所述的方法,其中所述提供底部引线框带包括提供多个整体连接的底部引线框,每个底部引线框具有基本上位于在所述DAP和所述外围框架上方的平面中的大致平坦引线条,并具有从其突出并附接到所述外围框架部分的至少一个引线条引线。
19.根据权利要求10所述的方法,其中将所述顶部引线框带附接到所述底部引线框带包括,以嵌套和焊接的方式,将所述底部引线框带的每个底部引线框上的所述外围框架部分与所述顶部引线框带的每个顶部引线框上的引线的端部结合。
20.根据权利要求19所述的方法,进一步包括沿着切割道分割所附接的顶部引线框带和底部引线框带,其中所述切割道定位在嵌套和焊接结合的点的内部。
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CN108630654A (zh) * | 2017-03-23 | 2018-10-09 | 恩智浦美国有限公司 | 具有波纹引线的半导体装置及其形成方法 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105895606A (zh) * | 2014-12-29 | 2016-08-24 | 飞思卡尔半导体公司 | 具有带状线的封装半导体器件 |
JP1537979S (zh) * | 2015-04-20 | 2015-11-16 | ||
JP1537980S (zh) * | 2015-04-20 | 2015-11-16 | ||
US9922904B2 (en) * | 2015-05-26 | 2018-03-20 | Infineon Technologies Ag | Semiconductor device including lead frames with downset |
US10381293B2 (en) * | 2016-01-21 | 2019-08-13 | Texas Instruments Incorporated | Integrated circuit package having an IC die between top and bottom leadframes |
US10636729B2 (en) * | 2017-06-19 | 2020-04-28 | Texas Instruments Incorporated | Integrated circuit package with pre-wetted contact sidewall surfaces |
US10896869B2 (en) * | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
US10867894B2 (en) * | 2018-10-11 | 2020-12-15 | Asahi Kasei Microdevices Corporation | Semiconductor element including encapsulated lead frames |
DE102019118174B3 (de) * | 2019-07-04 | 2020-11-26 | Infineon Technologies Ag | Verarbeitung von einem oder mehreren trägerkörpern und elektronischen komponenten durch mehrfache ausrichtung |
US11158567B2 (en) | 2019-08-09 | 2021-10-26 | Texas Instruments Incorporated | Package with stacked power stage and integrated control die |
US11715679B2 (en) | 2019-10-09 | 2023-08-01 | Texas Instruments Incorporated | Power stage package including flexible circuit and stacked die |
US11302615B2 (en) | 2019-12-30 | 2022-04-12 | Texas Instruments Incorporated | Semiconductor package with isolated heat spreader |
US11264310B2 (en) | 2020-06-04 | 2022-03-01 | Texas Instruments Incorporated | Spring bar leadframe, method and packaged electronic device with zero draft angle |
US11450593B2 (en) * | 2020-07-02 | 2022-09-20 | Infineon Technologies Ag | Spacer frame for semiconductor packages |
US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
US11848244B2 (en) * | 2021-09-30 | 2023-12-19 | Texas Instruments Incorporated | Leaded wafer chip scale packages |
US20230197576A1 (en) * | 2021-12-20 | 2023-06-22 | Texas Instruments Incorporated | Leadframe strip with complimentary design |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5686698A (en) * | 1994-06-30 | 1997-11-11 | Motorola, Inc. | Package for electrical components having a molded structure with a port extending into the molded structure |
US5789806A (en) * | 1995-08-02 | 1998-08-04 | National Semiconductor Corporation | Leadframe including bendable support arms for downsetting a die attach pad |
US6268646B1 (en) * | 1996-08-27 | 2001-07-31 | Hitachi Cable, Ltd. | Lead frame for lead on chip |
CN1334603A (zh) * | 2000-06-28 | 2002-02-06 | 国际商业机器公司 | 集成电路的平面化塑料封装模块 |
CN101326636A (zh) * | 2005-12-09 | 2008-12-17 | 飞兆半导体公司 | 用于组装顶部与底部暴露的封装半导体的装置和方法 |
CN102403298A (zh) * | 2010-09-07 | 2012-04-04 | 飞思卡尔半导体公司 | 用于半导体器件的引线框 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5229329A (en) | 1991-02-28 | 1993-07-20 | Texas Instruments, Incorporated | Method of manufacturing insulated lead frame for integrated circuits |
JP3773855B2 (ja) * | 2001-11-12 | 2006-05-10 | 三洋電機株式会社 | リードフレーム |
JP2004079760A (ja) * | 2002-08-19 | 2004-03-11 | Nec Electronics Corp | 半導体装置及びその組立方法 |
JP4100332B2 (ja) * | 2003-11-12 | 2008-06-11 | 株式会社デンソー | 電子装置およびその製造方法 |
US7285849B2 (en) * | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US20070290303A1 (en) | 2006-06-07 | 2007-12-20 | Texas Instruments Deutschland Gmbh | Dual leadframe semiconductor device package |
US20080036078A1 (en) | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
US20090057855A1 (en) * | 2007-08-30 | 2009-03-05 | Maria Clemens Quinones | Semiconductor die package including stand off structures |
US8049312B2 (en) | 2009-01-12 | 2011-11-01 | Texas Instruments Incorporated | Semiconductor device package and method of assembly thereof |
US8354303B2 (en) | 2009-09-29 | 2013-01-15 | Texas Instruments Incorporated | Thermally enhanced low parasitic power semiconductor package |
US8222716B2 (en) * | 2009-10-16 | 2012-07-17 | National Semiconductor Corporation | Multiple leadframe package |
US8304887B2 (en) | 2009-12-10 | 2012-11-06 | Texas Instruments Incorporated | Module package with embedded substrate and leadframe |
US8203199B2 (en) | 2009-12-10 | 2012-06-19 | National Semiconductor Corporation | Tie bar and mold cavity bar arrangements for multiple leadframe stack package |
CN102473700B (zh) * | 2010-06-11 | 2015-05-20 | 松下电器产业株式会社 | 树脂封装型半导体装置及其制造方法 |
JP5410465B2 (ja) * | 2011-02-24 | 2014-02-05 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
-
2013
- 2013-01-09 US US13/737,697 patent/US8884414B2/en active Active
-
2014
- 2014-01-09 CN CN201480003922.6A patent/CN104956782B/zh active Active
- 2014-01-09 JP JP2015552768A patent/JP6261055B2/ja active Active
- 2014-01-09 WO PCT/US2014/010860 patent/WO2014110247A1/en active Application Filing
- 2014-05-01 US US14/267,565 patent/US9029194B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5686698A (en) * | 1994-06-30 | 1997-11-11 | Motorola, Inc. | Package for electrical components having a molded structure with a port extending into the molded structure |
US5789806A (en) * | 1995-08-02 | 1998-08-04 | National Semiconductor Corporation | Leadframe including bendable support arms for downsetting a die attach pad |
US6268646B1 (en) * | 1996-08-27 | 2001-07-31 | Hitachi Cable, Ltd. | Lead frame for lead on chip |
CN1334603A (zh) * | 2000-06-28 | 2002-02-06 | 国际商业机器公司 | 集成电路的平面化塑料封装模块 |
CN101326636A (zh) * | 2005-12-09 | 2008-12-17 | 飞兆半导体公司 | 用于组装顶部与底部暴露的封装半导体的装置和方法 |
CN102403298A (zh) * | 2010-09-07 | 2012-04-04 | 飞思卡尔半导体公司 | 用于半导体器件的引线框 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108630654A (zh) * | 2017-03-23 | 2018-10-09 | 恩智浦美国有限公司 | 具有波纹引线的半导体装置及其形成方法 |
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CN104956782B (zh) | 2018-05-11 |
US20140191381A1 (en) | 2014-07-10 |
US8884414B2 (en) | 2014-11-11 |
JP2016503240A (ja) | 2016-02-01 |
JP6261055B2 (ja) | 2018-01-17 |
WO2014110247A1 (en) | 2014-07-17 |
US9029194B2 (en) | 2015-05-12 |
US20140242755A1 (en) | 2014-08-28 |
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