CN104956468B - 形成金属接触窗口的方法 - Google Patents

形成金属接触窗口的方法 Download PDF

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Publication number
CN104956468B
CN104956468B CN201480005937.6A CN201480005937A CN104956468B CN 104956468 B CN104956468 B CN 104956468B CN 201480005937 A CN201480005937 A CN 201480005937A CN 104956468 B CN104956468 B CN 104956468B
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CN
China
Prior art keywords
hard mask
mask layer
layer
top surface
patterned photoresist
Prior art date
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Application number
CN201480005937.6A
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English (en)
Chinese (zh)
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CN104956468A (zh
Inventor
D·G·法伯
T·李
S·莱特尔
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Texas Instruments Inc
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Texas Instruments Inc
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Publication of CN104956468A publication Critical patent/CN104956468A/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/069—Manufacture or treatment of conductive parts of the interconnections by forming self-aligned vias or self-aligned contact plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CN201480005937.6A 2013-02-08 2014-02-10 形成金属接触窗口的方法 Active CN104956468B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/762,529 2013-02-08
US13/762,529 US9054158B2 (en) 2013-02-08 2013-02-08 Method of forming a metal contact opening with a width that is smaller than the minimum feature size of a photolithographically-defined opening
PCT/US2014/015595 WO2014124376A1 (en) 2013-02-08 2014-02-10 Method of forming metal contact opening

Publications (2)

Publication Number Publication Date
CN104956468A CN104956468A (zh) 2015-09-30
CN104956468B true CN104956468B (zh) 2017-09-08

Family

ID=51297723

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480005937.6A Active CN104956468B (zh) 2013-02-08 2014-02-10 形成金属接触窗口的方法

Country Status (5)

Country Link
US (1) US9054158B2 (https=)
EP (1) EP3033766B1 (https=)
JP (1) JP6293171B2 (https=)
CN (1) CN104956468B (https=)
WO (1) WO2014124376A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583609B2 (en) 2013-03-25 2017-02-28 Texas Instruments Incorporated MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts
CN108666263B (zh) * 2018-04-13 2020-06-16 上海华力集成电路制造有限公司 接触孔的制造方法
CN108470745A (zh) * 2018-04-28 2018-08-31 德淮半导体有限公司 图像传感器及其形成方法
US10867842B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for shrinking openings in forming integrated circuits
CN110690282B (zh) * 2019-08-23 2022-10-18 福建省福联集成电路有限公司 一种基于晶体管的电阻结构及其制作方法
DE102020113616A1 (de) * 2020-02-24 2021-08-26 Taiwan Semiconductor Manufacturing Co., Ltd. Hartmaskenschicht unter einer durchkontaktierungsstruktur in einer anzeigevorrichtung
US11682692B2 (en) 2020-02-24 2023-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Hard mask layer below via structure in display device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7037850B2 (en) * 2003-04-04 2006-05-02 Hynix Semiconductor Inc. Method for fabricating semiconductor device with fine patterns
US7196003B2 (en) * 2003-03-18 2007-03-27 Fujitsu Limited Method for manufacturing a semiconductor device suitable for the formation of a wiring layer
CN101211761A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 半导体器件以及在半导体器件中形成图案的方法

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JP3288884B2 (ja) * 1995-03-13 2002-06-04 株式会社東芝 レジストパターン形成方法
JP3305932B2 (ja) * 1995-09-19 2002-07-24 株式会社東芝 半導体装置およびその製造方法
JP4613364B2 (ja) * 2000-06-14 2011-01-19 学校法人東京電機大学 レジストパタン形成方法
US6570214B1 (en) * 2002-03-01 2003-05-27 Ching-Yuan Wu Scalable stack-gate flash memory cell and its contactless memory array
JP3585039B2 (ja) * 2002-03-25 2004-11-04 株式会社半導体先端テクノロジーズ ホール形成方法
JP3988592B2 (ja) * 2002-08-30 2007-10-10 ソニー株式会社 半導体装置の製造方法
JP4278497B2 (ja) * 2003-11-26 2009-06-17 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
KR100819673B1 (ko) * 2006-12-22 2008-04-04 주식회사 하이닉스반도체 반도체 소자 및 그의 패턴 형성 방법
JP2009238998A (ja) * 2008-03-27 2009-10-15 Epson Imaging Devices Corp コンタクトホールの形成方法、パターン形成方法、及び電気光学装置の製造方法
US20100099255A1 (en) * 2008-10-20 2010-04-22 Conley Willard E Method of forming a contact through an insulating layer
JP2010135624A (ja) * 2008-12-05 2010-06-17 Tokyo Electron Ltd 半導体装置の製造方法
US8252192B2 (en) * 2009-03-26 2012-08-28 Tokyo Electron Limited Method of pattern etching a dielectric film while removing a mask layer
KR101073075B1 (ko) * 2009-03-31 2011-10-12 주식회사 하이닉스반도체 이중 패터닝 공정을 이용한 반도체장치 제조 방법
US20120100717A1 (en) * 2010-10-26 2012-04-26 Texas Instruments Incorporated Trench lithography process
KR101671464B1 (ko) * 2010-12-02 2016-11-02 삼성전자주식회사 반도체 소자의 제조 방법
JP2012182474A (ja) * 2012-04-26 2012-09-20 Tokyo Electron Ltd 半導体装置の製造方法及び記憶媒体

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7196003B2 (en) * 2003-03-18 2007-03-27 Fujitsu Limited Method for manufacturing a semiconductor device suitable for the formation of a wiring layer
US7037850B2 (en) * 2003-04-04 2006-05-02 Hynix Semiconductor Inc. Method for fabricating semiconductor device with fine patterns
CN101211761A (zh) * 2006-12-28 2008-07-02 海力士半导体有限公司 半导体器件以及在半导体器件中形成图案的方法

Also Published As

Publication number Publication date
EP3033766A4 (en) 2017-08-09
EP3033766A1 (en) 2016-06-22
EP3033766B1 (en) 2021-10-20
JP6293171B2 (ja) 2018-03-14
CN104956468A (zh) 2015-09-30
US20140227877A1 (en) 2014-08-14
JP2016510515A (ja) 2016-04-07
WO2014124376A1 (en) 2014-08-14
US9054158B2 (en) 2015-06-09

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