CN104952990A - Epitaxial wafer of light emitting diode and method for manufacturing epitaxial wafer - Google Patents
Epitaxial wafer of light emitting diode and method for manufacturing epitaxial wafer Download PDFInfo
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- CN104952990A CN104952990A CN201510212949.2A CN201510212949A CN104952990A CN 104952990 A CN104952990 A CN 104952990A CN 201510212949 A CN201510212949 A CN 201510212949A CN 104952990 A CN104952990 A CN 104952990A
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 24
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 13
- 230000004888 barrier function Effects 0.000 claims description 22
- 230000003139 buffering effect Effects 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 230000008859 change Effects 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 18
- 230000007547 defect Effects 0.000 abstract description 5
- 238000005036 potential barrier Methods 0.000 abstract description 4
- 230000008901 benefit Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 230000000903 blocking effect Effects 0.000 abstract 2
- 230000006911 nucleation Effects 0.000 abstract 2
- 238000010899 nucleation Methods 0.000 abstract 2
- 239000013078 crystal Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
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- B—PERFORMING OPERATIONS; TRANSPORTING
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- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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Abstract
The invention discloses an epitaxial wafer of a light emitting diode and a method for manufacturing the epitaxial wafer, and belongs to the field of semiconductor photoelectric technologies. The epitaxial wafer comprises a substrate, a low-temperature buffer layer, a three-dimensional nucleation layer, a two-dimensional buffer restoration layer, an intrinsic gallium nitride layer, an n-type layer, a multi-quantum well layer, an electron blocking layer, a p-type layer and a p-type contact layer. The low-temperature buffer layer, the three-dimensional nucleation layer, the two-dimensional buffer restoration layer, the intrinsic gallium nitride layer, the n-type layer, the multi-quantum well layer, the electron blocking layer, the p-type layer and the p-type contact layer are sequentially stacked on the substrate, the p-type layer is of a super-lattice structure, and low-temperature p-type layers and high-temperature p-type layers are alternately stacked on one another to form the super-lattice structure. The method includes growing a low-temperature p-type layer, then quickly growing a high-temperature p-type layer and allowing the high temperature of the high-temperature p-type layer to repair low-temperature defects of the low-temperature p-type layer; growing another high-temperature p-type layer, then quickly growing another low-temperature p-type layer and allowing the low temperature of the other low-temperature p-type layer to prevent the activity of the multi-quantum well layer from being destroyed by the continuous high temperature of the other high-temperature p-type layer. The epitaxial wafer and the method have the advantages that potential barrier difference can be formed between layers in the p-type layers of the super-lattice structure, and accordingly extension effects of holes can be improved advantageously.
Description
Technical field
The present invention relates to optical semiconductor electro-technical field, particularly a kind of LED epitaxial slice and preparation method thereof.
Background technology
LED (Light Emitting Diodes, semiconductor light-emitting-diode) advantage such as energy-conserving and environment-protective, reliability are high because having, long service life and being paid close attention to widely, yield unusually brilliant results at background light source and display screen field in recent years, and start to march to domestic lighting market.Therefore, the luminous efficiency increasing LED and the antistatic effect improving LED seem particularly crucial.
In prior art, there is a kind of LED epitaxial slice, comprise stack gradually substrate, low temperature buffer layer, three-dimensional nucleating layer, two dimension buffering retrieving layer, intrinsic gallium nitride layer, n-layer, multiple quantum well layer, low-temperature p-type layer, electronic barrier layer, high temperature p-type layer and P type contact layer, this epitaxial wafer generally uses MOCVD (Metal-organic Chemical Vapor DePosition, metallorganic chemical vapor deposition) mode grows up, and can doped portion During growing GaN quantum well layer in multiple quantum well layer; Because the In composition in GaN quantum well layer is very responsive for temperature; too high temperature easily makes In composition separate out from GaN crystal; thus multiple quantum well layer activity is reduced; so usually one deck low-temperature p-type layer can be produced when having grown quantum well layer, while providing hole, protect multiple quantum well layer not by high temperature.
Realizing in process of the present invention, inventor finds that prior art at least exists following problem:
The growth temperature of low-temperature p-type layer is too low, easily causes the poor existing defects of crystal mass of low-temperature p-type layer itself, and then makes the defect concentration of epitaxial wafer large, and luminous efficiency reduces, and antistatic effect is deteriorated.
Summary of the invention
In order to solve the problem of prior art, embodiments provide a kind of LED epitaxial slice and preparation method thereof, technical scheme is as follows:
On the one hand, embodiments provide a kind of LED epitaxial slice, described LED epitaxial slice comprises substrate and stacks gradually low temperature buffer layer over the substrate, three-dimensional nucleating layer, two dimension buffering retrieving layer, intrinsic gallium nitride layer, n-layer, multiple quantum well layer, electronic barrier layer, p-type layer and P type contact layer, described p-type layer is superlattice structure, and described superlattice structure is by low-temperature p-type layer and high temperature p-type layer is alternately laminated forms.
Further, not luminous front quantum well layer is provided with between described n-layer and described multiple quantum well layer.
Further, described not luminous front quantum well layer forms by InGaN and GaN in 5 ~ 11 cycles is alternately laminated.
Further, be all 1 × 10 doped with the doping content of Mg, Mg in described high temperature p-type layer and described low-temperature p-type layer
18~ 1 × 10
20cm
-3.
Further, the side of the close P type contact layer from the side of the close electronic barrier layer of described p-type layer to described p-type layer, the doping content of Mg is for change from small to big from large to small again.
Further, in described low-temperature p-type layer doped with In or Al.
Further, the doping content of described In is 1 × 10
2cm
-3, the doping content of described Al is 5 × 10
4cm
-3.
Further, the growth temperature of described low-temperature p-type layer is 600 ~ 800 DEG C, and the growth temperature of described high temperature p-type layer is 800 ~ 1000 DEG C.
Further, the thickness of described low-temperature p-type layer is 2 ~ 10nm, and the thickness of described high temperature p-type layer is 5 ~ 50nm, and the thickness of described p-type layer is 50 ~ 200nm.
On the other hand, the embodiment of the present invention additionally provides a kind of manufacture method of LED epitaxial slice, and described manufacture method comprises:
One substrate is provided, and described substrate is put into MOVCD system carries out high-temperature heat treatment;
On the described substrate handled well, low temperature growth buffer layer, three-dimensional nucleating layer, two dimension cushion retrieving layer, intrinsic gallium nitride layer, n-layer, multiple quantum well layer and electronic barrier layer successively;
Described electronic barrier layer grows p-type layer, and described p-type layer is the alternately laminated superlattice structure of low-temperature p-type layer and high temperature p-type layer;
Described p-type layer grows P type contact layer, and epitaxial wafer growth terminates;
To epitaxial wafer annealing in process in nitrogen atmosphere.
The beneficial effect of the technical scheme that the embodiment of the present invention provides is:
Obtained the p-type layer of superlattice structure by alternately laminated growing low temperature p-type layer and high temperature p-type layer, ramp one deck high temperature p-type layer again after growth one deck low-temperature p-type layer, the temperature that high temperature p-type layer is higher can be repaired the cold temperature deficiency of low-temperature p-type layer; Ramp one deck low-temperature p-type layer again after growth one deck highly p-type layer, the activity of the high temperature multiple quantum well layer that the temperature that low-temperature p-type layer is lower can prevent again high temperature p-type layer from continuing; The difference of formation potential barrier between layers in the p-type layer of superlattice structure, is conducive to the expansion effect improving hole, the antistatic effect of epitaxial wafer is got a promotion.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structure chart of a kind of LED epitaxial slice that the embodiment of the present invention 1 provides;
Fig. 2 is the flow chart of the manufacture method of a kind of LED epitaxial slice that the embodiment of the present invention 2 provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.
Embodiment 1
See Fig. 1, embodiments provide a kind of LED epitaxial slice, this epitaxial wafer comprises substrate 11 and stacks gradually low temperature buffer layer 12 on the substrate 11, three-dimensional nucleating layer 13, two dimension buffering retrieving layer 14, intrinsic gallium nitride layer 15, n-layer 16, multiple quantum well layer 17a, electronic barrier layer 18, p-type layer 19 and P type contact layer 20, p-type layer 19 is superlattice structure, and this superlattice structure is by low-temperature p-type layer 19a and high temperature p-type layer 19b is alternately laminated forms.
Particularly, in the present embodiment, substrate 11 can be Sapphire Substrate; Low temperature buffer layer 12 can be GaN layer, and the growth temperature of this low temperature buffer layer 12 is 400 ~ 600 DEG C, and growth pressure is 100 ~ 300torr, and thickness is 15 ~ 35nm; Three-dimensional nucleating layer 13 can be GaN layer, and the growth temperature of this three-dimensional nucleating layer 13 is 1000 ~ 1100 DEG C, and growth pressure is 100 ~ 500torr, and thickness is 100 ~ 500nm; Two dimension buffering retrieving layer 14 can be GaN layer, and the growth temperature of this two dimension buffering retrieving layer 14 is 1000 ~ 1200 DEG C, and growth pressure is 100 ~ 500torr, and thickness is 500 ~ 800nm; Intrinsic gallium nitride layer 15 undopes, and can be GaN layer, and the growth temperature of this intrinsic gallium nitride layer 15 is 1000 ~ 1200 DEG C, growth pressure is 100 ~ 500torr, and thickness is 800 ~ 1200nm; N-layer 16 can be the GaN layer of N-shaped doping, and the growth temperature of this n-layer 16 is 1000 ~ 1200 DEG C, and pressure is 100 ~ 500torr, and thickness is 1 ~ 3 μm, and N-shaped doping can be adulterated for Si, and the doping content of Si is 1 × 10
18~ 1 × 10
20cm
-3; Multiple quantum well layer 17a can by the InGaN quantum well layer in 5 ~ 11 cycles and GaN quantum barrier layer be alternately laminated forms, wherein, the thickness of InGaN quantum well layer can be 3nm, and growth temperature is 720 ~ 829 DEG C, the thickness of GaN quantum barrier layer is 9 ~ 20nm, and growth temperature is 850 ~ 959 DEG C; Electronic barrier layer 18 can be p-type Al
yga
1-yn layer, wherein, 0.1<y<0.5, the growth temperature of this electronic barrier layer 18 is 850 ~ 950 DEG C, and pressure is 100 ~ 500torr, and thickness is 50 ~ 150nm; The growth temperature of P type contact layer 20 is 850 ~ 1050 DEG C, and growth pressure is 100 ~ 300torr, and thickness is 10 ~ 100nm.
In the present embodiment, p-type layer 19 is by the alternately laminated superlattice structure of the low-temperature p-type layer 19a in 5 ~ 20 cycles and high temperature p-type layer 19b, wherein, the growth pressure of low-temperature p-type layer 19a is 200Torr ~ 600Torr, growth temperature is 600 ~ 800 DEG C, growth rate is between 0.2 ~ 0.6nm/sec, and thickness is 2 ~ 10nm; The growth pressure of high temperature p-type layer 19b is 200Torr ~ 600Torr, and growth temperature is 800 ~ 1000 DEG C, and growth rate is 0.2 ~ 0.6nm/sec, and thickness is 5 ~ 50nm; The gross thickness of p-type layer 19 can be 50 ~ 200nm.
Wherein, the growth temperature interval of above-mentioned p-type layer 19 is preferable range, for low-temperature p-type layer 19a and high temperature p-type layer 19b, when both growth temperatures are lower than respective temperature range minimum value, crystal mass can reduce, and defect state can increase, and the V-pits that MQW outputs also can amplify further; When both growth temperatures are higher than respective temperature range maximum, the temperature difference between p-type layer and MQW can be caused to widen thus be baked to MQW, the In component in MQW can be made like this to separate out, affect outward appearance and luminance.
Further, not luminous front quantum well layer 17b is provided with between n-layer 16 and multiple quantum well layer 17a.Wherein, not luminous front quantum well layer 17b can form by InGaN and GaN in 5 ~ 11 cycles is alternately laminated.
Particularly, larger lattice mismatch is there is between which floor epitaxial loayer of substrate 11 and initial preparation, thus cause the generation of stress, the Stress Release that these lattice mismatches can produce by not luminous front quantum well layer 17b, make stress not affect the growth of the multiple quantum well layer 17a of follow-up luminescence; Simultaneously, because in diode, the concentration of electronics is greater than the concentration in hole, and the effective mass of electronics is less than hole, so electronics speed in the transmission will much larger than hole, not luminous front quantum well layer 17b has and slows down the effect of electric transmission speed, as much as possible electronics can be limited in multiple quantum well layer 17a with hole-recombination, prevent electronics from overflowing to p-type layer 19.
Wherein, GaN in not luminous front quantum well layer can adulterate, the such as element such as doped with Al, In, InGaN and GaN is set and replaces 5 ~ 11 cycles of growth, when periodicity is lower than this scope, easily occur electronics overflow, when periodicity is higher than this scope, the operating voltage of diode can be caused to raise, the transmission range in hole also can be caused simultaneously to become far away, reduce the luminous efficiency of diode.
Further, in the present embodiment, can doped with Mg in high temperature p-type layer 19b and low-temperature p-type layer 19a, and the doping content of Mg is 1 × 10
18~ 1 × 10
20cm
-3, wherein, in each layer of p-type layer 19, the doping content of Mg can be identical, also can be different.
Further, in p-type layer 19, the side from the side of the close electronic barrier layer 18 of p-type layer 19 to close P type contact layer 20, the doping content of Mg can be change from small to big from large to small again.
Particularly, the first heavy doping in side of the close electronic barrier layer 18 of p-type layer 19, because this side is near multiple quantum well layer 17a, a large amount of hole can be provided to improve combined efficiency, near the side also heavy doping of P type contact layer 20, be conducive to bright dipping to increase brightness on the one hand, the contact berrier near P type contact layer 20 place can be reduced on the other hand, to form good ohmic contact layer, reduce operating voltage, the Mg doping content of whole p-type layer 19, in high the sprawling doped with the transverse direction being beneficial to hole of height, enhances the antistatic effect of diode.
Further, can adulterate in low-temperature p-type layer 19a In or Al, and wherein, the doping content of In can be 1 × 10
2cm
-3, the doping content of Al can be 5 × 10
4cm
-3.
Particularly, doping In or Al can form barrier potential difference in low-temperature p-type layer, and to strengthen the expansion effect in hole in diode, the doping content scope of In can be 0.5 × 10
2~ 1.5 × 10
2cm
-3, the doping content of Al is 3 × 10
4~ 8 × 10
4cm
-3, the selection of this doping content is a preferable range, during lower than this doping scope, may not reach the doping effect of expection, and during higher than this doping scope, easily causes the lattice of diode adaptive large, can introduce more defect.
A kind of LED epitaxial slice that the embodiment of the present invention provides, the p-type layer of superlattice structure is obtained by alternately laminated growing low temperature p-type layer and high temperature p-type layer, ramp one deck high temperature p-type layer again after growth one deck low-temperature p-type layer, the temperature that high temperature p-type layer is higher can be repaired the cold temperature deficiency of low-temperature p-type layer; Ramp one deck low-temperature p-type layer again after growth one deck highly p-type layer, the activity of the high temperature multiple quantum well layer that the temperature that low-temperature p-type layer is lower can prevent again high temperature p-type layer from continuing; The difference of formation potential barrier between layers in the p-type layer of superlattice structure, is conducive to the expansion effect improving hole, the antistatic effect of epitaxial wafer is got a promotion.
Embodiment 2
As shown in Figure 2, embodiments provide a kind of manufacture method of LED epitaxial slice, be applicable to the LED epitaxial slice prepared as described in example 1 above, this manufacture method comprises the following steps:
S1: provide a substrate 11, is placed in hydrogen atmosphere annealing 1 ~ 10 minute by substrate 11; Wherein, substrate 11 can be the Al in crystal orientation 0001
2o
3sapphire, the high temperature anneal can the surface of clean substrate, after completing annealing, under the hot environment of 1000 ~ 1200 DEG C, carries out nitrogen treatment to substrate 11.
S2: temperature is dropped to 400 ~ 600 DEG C, grows one deck low temperature buffer layer 12 on the substrate 11; Wherein, low temperature buffer layer 12 is the GaN layer that 15 ~ 40nm is thick, and growth pressure is between 400 ~ 600Torr.
S3: temperature is risen to 1000 ~ 1040 DEG C, low temperature buffer layer 12 grows the three-dimensional nucleating layer 13 of one deck; Wherein, the thickness of three-dimensional nucleating layer 13 is between 400 ~ 600nm, and growth pressure is between 400 ~ 600Torr, and growth time is 10 ~ 20 minutes.
S4: temperature is risen to 1040 ~ 1080 DEG C, three-dimensional nucleating layer 13 grows one deck two dimension buffering retrieving layer 14; Wherein, two dimension buffering retrieving layer 14 can be GaN layer, and growth temperature is 1000 ~ 1200 DEG C, and growth pressure is 100 ~ 500torr, and thickness is between 500 ~ 800nm.
S5: temperature is adjusted to 1050 ~ 1100 DEG C, two dimension buffering retrieving layer 14 grows one deck intrinsic gallium nitride layer 15; Wherein, intrinsic gallium nitride layer 15 undopes, and growth pressure is 100 ~ 500torr, and thickness is 1 ~ 2um.
S6: temperature is adjusted to 1000 ~ 1100 DEG C, intrinsic gallium nitride layer 15 grows one deck n-layer 16; Wherein, the n-type GaN layer that n-layer 16 is adulterated for Si, growth pressure is 100 ~ 500Torr, and thickness is 1 ~ 3um.
S7: grow multiple quantum well layer 17a in n-layer 16; Wherein, multiple quantum well layer 17a is by the In in 5 ~ 11 cycles
xga
1-xn (0<x<1) quantum well layer and GaN quantum barrier layer is alternately laminated forms, In
xga
1-xthe thickness of N quantum well layer is between 3 ~ 4nm, and growth pressure is between 100 ~ 500Torr, and the thickness of GaN quantum barrier layer is between 9 ~ 15nm, and growth pressure is between 100 ~ 500Torr.In the present embodiment, before growth multiple quantum well layer 17a, can also grow not luminous front quantum well layer 17b in n-layer 16, not luminous front quantum well layer 17b forms by InGaN and GaN in 5 ~ 11 cycles is alternately laminated.
S8: temperature is adjusted to 850 ~ 950 DEG C, multiple quantum well layer 17a grows one deck electronic barrier layer 18; Wherein, electronic barrier layer 18 can be Al
yga
1-yn (0.1<y<0.5), thickness is 50 ~ 100nm.
S9: grow p-type layer 19 on electronic barrier layer 18; Wherein, p-type layer 19 is by low-temperature p-type layer 19a and high temperature p-type layer 19b is alternately laminated forms, and the growth temperature of low-temperature p-type layer 19a is 600 ~ 800 DEG C, and growth rate is 0.2 ~ 0.6nm/sec, and growth time is 10 ~ 30s, and thickness is 2 ~ 10nm; The growth temperature of high temperature p-type layer 19b is 800 ~ 1000 DEG C, and growth rate is 0.2 ~ 0.6nm/sec, and thickness is 5 ~ 50nm, and the gross thickness of p-type layer 19 is 50 ~ 200nm.
S10: temperature is adjusted to 850 ~ 1000 DEG C, p-type layer 19 grows one deck P type contact layer 20; Wherein, the growth pressure of P type contact layer 20 is 100 ~ 300Torr, and thickness is 5 ~ 10nm.
S11: reduce temperature to 650 ~ 850 DEG C, annealing in process is carried out to LED epitaxial slice; Wherein, annealing in process is carried out in nitrogen atmosphere, and annealing time, at 5 ~ 15 minutes, cools the temperature to room temperature after having annealed, and epitaxial wafer growth terminates.
The manufacture method of a kind of LED epitaxial slice that the embodiment of the present invention provides, the p-type layer of superlattice structure is obtained by alternately laminated growing low temperature p-type layer and high temperature p-type layer, ramp one deck high temperature p-type layer again after growth one deck low-temperature p-type layer, the temperature that high temperature p-type layer is higher can be repaired the cold temperature deficiency of low-temperature p-type layer; Ramp one deck low-temperature p-type layer again after growth one deck highly p-type layer, the activity of the high temperature multiple quantum well layer that the temperature that low-temperature p-type layer is lower can prevent again high temperature p-type layer from continuing; The difference of formation potential barrier between layers in the p-type layer of superlattice structure, is conducive to the expansion effect improving hole, the antistatic effect of epitaxial wafer is got a promotion.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a LED epitaxial slice, described LED epitaxial slice comprises substrate and stacks gradually low temperature buffer layer over the substrate, three-dimensional nucleating layer, two dimension buffering retrieving layer, intrinsic gallium nitride layer, n-layer, multiple quantum well layer, electronic barrier layer, p-type layer and P type contact layer, it is characterized in that, described p-type layer is superlattice structure, and described superlattice structure is by low-temperature p-type layer and high temperature p-type layer is alternately laminated forms.
2. LED epitaxial slice according to claim 1, is characterized in that, is provided with not luminous front quantum well layer between described n-layer and described multiple quantum well layer.
3. LED epitaxial slice according to claim 2, is characterized in that, described not luminous front quantum well layer forms by InGaN and GaN in 5 ~ 11 cycles is alternately laminated.
4. LED epitaxial slice according to claim 1, is characterized in that, is all 1 × 10 doped with the doping content of Mg, Mg in described high temperature p-type layer and described low-temperature p-type layer
18~ 1 × 10
20cm
-3.
5. LED epitaxial slice according to claim 4, is characterized in that, the side of the close P type contact layer from the side of the close electronic barrier layer of described p-type layer to described p-type layer, the doping content of Mg is for change from small to big from large to small again.
6. LED epitaxial slice according to claim 1, is characterized in that, doped with In or Al in described low-temperature p-type layer.
7. LED epitaxial slice according to claim 6, is characterized in that, the doping content of described In is 1 × 10
2cm
-3, the doping content of described Al is 5 × 10
4cm
-3.
8. the LED epitaxial slice according to any one of claim 1 ~ 7, is characterized in that, the growth temperature of described low-temperature p-type layer is 600 ~ 800 DEG C, and the growth temperature of described high temperature p-type layer is 800 ~ 1000 DEG C.
9. the LED epitaxial slice according to any one of claim 1 ~ 7, is characterized in that, the thickness of described low-temperature p-type layer is 2 ~ 10nm, and the thickness of described high temperature p-type layer is 5 ~ 50nm, and the thickness of described p-type layer is 50 ~ 200nm.
10. a manufacture method for LED epitaxial slice, is characterized in that, described manufacture method comprises:
One substrate is provided, and described substrate is put into MOVCD system carries out high-temperature heat treatment;
On the described substrate handled well, low temperature growth buffer layer, three-dimensional nucleating layer, two dimension cushion retrieving layer, intrinsic gallium nitride layer, n-layer, multiple quantum well layer and electronic barrier layer successively;
Described electronic barrier layer grows p-type layer, and described p-type layer is the alternately laminated superlattice structure of low-temperature p-type layer and high temperature p-type layer;
Described p-type layer grows P type contact layer, and epitaxial wafer growth terminates;
To epitaxial wafer annealing in process in nitrogen atmosphere.
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| CN107359229A (en) * | 2017-06-30 | 2017-11-17 | 华灿光电(苏州）有限公司 | A kind of LED epitaxial slice and its manufacture method |
| CN108336203A (en) * | 2017-12-29 | 2018-07-27 | 华灿光电(苏州）有限公司 | A kind of gallium nitride based LED epitaxial slice and its manufacturing method |
| CN108389894A (en) * | 2018-03-29 | 2018-08-10 | 南昌大学 | A kind of high electronic migration rate transmistor epitaxial structure |
| CN108417484A (en) * | 2018-04-13 | 2018-08-17 | 中国电子科技集团公司第四十六研究所 | A method of promoting photoelectric sensor silicon epitaxy layer doping concentration uniformity |
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| CN109256445B (en) * | 2018-07-25 | 2020-11-10 | 华灿光电（浙江）有限公司 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
| CN109087977A (en) * | 2018-07-25 | 2018-12-25 | 华灿光电（浙江）有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109244206A (en) * | 2018-07-25 | 2019-01-18 | 华灿光电（浙江）有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109256445A (en) * | 2018-07-25 | 2019-01-22 | 华灿光电（浙江）有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109244206B (en) * | 2018-07-25 | 2020-09-25 | 华灿光电（浙江）有限公司 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
| CN109216514A (en) * | 2018-07-26 | 2019-01-15 | 华灿光电（浙江）有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109103312B (en) * | 2018-07-26 | 2020-10-27 | 华灿光电（浙江）有限公司 | Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof |
| CN109103312A (en) * | 2018-07-26 | 2018-12-28 | 华灿光电（浙江）有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109326692A (en) * | 2018-09-03 | 2019-02-12 | 淮安澳洋顺昌光电技术有限公司 | A kind of gallium nitride based LED epitaxial slice and preparation method thereof |
| CN109326698A (en) * | 2018-09-27 | 2019-02-12 | 华灿光电（浙江）有限公司 | A kind of manufacturing method of LED epitaxial slice |
| CN113793886A (en) * | 2021-08-04 | 2021-12-14 | 河源市众拓光电科技有限公司 | PGaN improved LED epitaxial structure and preparation method thereof |
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