CN108336203B - Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents

Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof Download PDF

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CN108336203B
CN108336203B CN201711479757.3A CN201711479757A CN108336203B CN 108336203 B CN108336203 B CN 108336203B CN 201711479757 A CN201711479757 A CN 201711479757A CN 108336203 B CN108336203 B CN 108336203B
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sublayer
sapphire substrate
epitaxial wafer
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CN108336203A (en
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丁涛
韦春余
周飚
胡加辉
李鹏
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure

Abstract

The invention discloses a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof, belonging to the technical field of semiconductors.A gallium nitride-based light emitting diode epitaxial wafer comprises a sapphire substrate, and an AlN buffer layer, a 3D nucleating layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer and a high-temperature P-type layer which are sequentially stacked on the sapphire substrate, wherein the 3D nucleating layer comprises a first sublayer and a second sublayer, the first sublayer is a GaN layer grown at 800-1100 ℃, the second sublayer is a GaN layer grown at 1000-1200 ℃, the growth temperature of the first sublayer is lower, the formed grains are smaller and denser, the grains can be stretched and deformed to close gaps and reduce the surface energy, so that tensile stress can be generated to promote the epitaxial wafer to develop towards the direction of concavity, thereby improving warpage and wavelength concentration, the temperature of the second sublayer is higher, the surface energy of the grains is reduced, and the whole epitaxial wafer is ensured not to occur, thereby improving the photoelectric performance of L.

Description

Gallium nitride-based light emitting diode epitaxial wafer and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof.
Background
GaN (gallium nitride) has good thermal conductivity, high temperature resistance, acid and alkali resistance, high hardness, and the like, and is widely used in light emitting diodes of various wave bands, the core component of GaN-based light emitting diodes is L ED (L light emitting diode) chips, and L ED chips include an epitaxial wafer and electrodes arranged on the epitaxial wafer.
In order to improve the productivity of the light emitting diode and the photoelectric performance of an L ED chip, when the GaN-based light emitting diode epitaxial wafer is manufactured, the AlN buffer layer is generally grown on the sapphire substrate by adopting a physical Vapor Deposition method, then the sapphire substrate on which the AlN buffer layer is grown is placed in MOCVD (Metal-organic Chemical Vapor Deposition) equipment, and the epitaxial wafer is continuously grown by adopting a Metal-organic Chemical Vapor Deposition method.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the sapphire substrate behaves differently in different types of MOCVD equipment after growth of the AlN buffer layer. For example, when a GaN-based light emitting diode is grown in a domestic MOCVD, the center of a sapphire substrate on which an AlN buffer layer is grown is raised upward (the raising direction is the same as the growth direction of an epitaxial wafer), and the edge of the sapphire substrate is bent downward (the bending direction is opposite to the growth direction of the epitaxial wafer), so that the whole epitaxial wafer of the manufactured GaN-based light emitting diode has a certain warping degree. In addition, the heating base arranged below the sapphire substrate can transfer heat to the epitaxial wafer layer by layer, so that when the multiple quantum well layer grows, the sapphire substrate has a certain warping degree, the heat is non-uniformly transferred to the multiple quantum well layer, and the uniformity of the light emitting wavelength of the multiple quantum well layer is greatly influenced.
Disclosure of Invention
In order to solve the problem that in the prior art, in different MOCVD equipment, an epitaxial wafer is warped to influence the uniformity of the light emitting wavelength of a multi-quantum well layer, the embodiment of the invention provides a gallium nitride-based light emitting diode epitaxial wafer and a manufacturing method thereof. The technical scheme is as follows:
in one aspect, the invention provides a gallium nitride-based light emitting diode epitaxial wafer, which comprises a sapphire substrate, and an AlN buffer layer, a 3D nucleating layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a high-temperature P-type layer and a P-type contact layer which are sequentially stacked on the sapphire substrate,
the 3D nucleating layer comprises a first sublayer and a second sublayer, the first sublayer is a GaN layer grown at 800-1100 ℃, and the second sublayer is a GaN layer grown at 1000-1200 ℃;
the thickness of the 3D nucleation layer is 2-30 nm, the thickness of the first sub-layer is 1-10 nm, and the thickness of the second sub-layer is 1-20 nm.
Further, the first sub-layer is a GaN layer grown at 1000 ℃, and the second sub-layer is a GaN layer grown at 1100 ℃.
In another aspect, the present invention provides a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode, the method comprising:
providing a sapphire substrate;
growing an AlN buffer layer on the sapphire substrate;
growing a 3D nucleation layer on the AlN buffer layer, wherein the 3D nucleation layer comprises a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are GaN layers, the growth temperature of the first sub-layer is 800-1100 ℃, the growth temperature of the second sub-layer is 1000-1200 ℃, the thickness of the 3D nucleation layer is 2-30 nm, the thickness of the first sub-layer is 1-10 nm, and the thickness of the second sub-layer is 1-20 nm;
and growing an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a high-temperature P-type layer and a P-type contact layer on the 3D nucleating layer in sequence.
Further, the growing an AlN buffer layer on the sapphire substrate includes:
and putting the sapphire substrate into PVD equipment, and sputtering a layer of AlN on the sapphire substrate to obtain the AlN buffer layer.
Further, growing a 3D nucleation layer on the AlN buffer layer, comprising:
placing the sapphire substrate with the AlN buffer layer in MOCVD equipment, and carrying out high-temperature heat treatment on the sapphire substrate in a hydrogen atmosphere for 10-15 minutes;
growing the 3D nucleation layer on the AlN buffer layer.
Further, the manufacturing method further includes:
and after the growth of the P-type contact layer is finished, reducing the temperature in the MOCVD equipment to 650-850 ℃, and annealing the GaN-based light-emitting diode epitaxial wafer for 5-15 minutes in a nitrogen atmosphere.
Furthermore, the growth pressure of the first sublayer and the growth pressure of the second sublayer are both 200-400 torr.
Further, the growth temperature of the first sub-layer is 1000 ℃, and the growth temperature of the second sub-layer is 1100 ℃.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the 3D nucleation layer is divided into a first sublayer and a second sublayer, the first sublayer is a GaN layer grown at 800-1100 ℃, and the second sublayer is a GaN layer grown at 1000-1200 ℃. Because the growth mode of the GaN epitaxial wafer is mainly a nuclear growth mode, deposited atoms are firstly condensed and nucleated after reaching the sapphire substrate, and the subsequent deposited atoms are continuously gathered near the nuclei, so that the nuclei are continuously grown in the three-dimensional direction to finally form the film. In the growth stage of the 3D nucleation layer, crystal nuclei are mainly formed on the AlN buffer layer and are continuously grown to form small islands. In the application, the growth temperature of the first sublayer is low, and formed grains are small and dense; when the crystal grains are mutually fused, gaps exist at the junctions due to the inconsistent orientation, so that larger surface energy exists, in order to reduce the surface energy, the crystal grains are stretched and deformed to close the gaps, the surface energy is reduced, tensile stress is generated, the epitaxial wafer is promoted to develop towards the direction of dishing (namely the direction opposite to the growth direction of the epitaxial wafer), the warping of the epitaxial wafer is improved, the surface of the sapphire substrate is flat, and heat can be uniformly transferred to the multiple quantum well layer when the multiple quantum well layer is grown, so that the uniformity of the light emitting wavelength is improved. And the whole epitaxial wafer is warped and concaved, so that the improvement of the lattice stress of the multi-quantum well layer is facilitated, and the photoelectric performance of the light emitting diode chip is improved. The growth temperature of the second sublayer is higher in the application, so that the surface energy of the crystal grains is reduced, and the epitaxial wafer is ensured not to be further warped.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a gan-based led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a gallium nitride-based light emitting diode according to an embodiment of the present invention;
fig. 3 is a graph illustrating warpage variations of a first quantum well layer of a different chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Example one
Fig. 1 is a schematic structural diagram of a gallium nitride-based light emitting diode epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 1, the gallium nitride-based light emitting diode includes a sapphire substrate 1, and an AlN buffer layer 2, a 3D nucleation layer 3, an undoped GaN layer 4, an N-type layer 5, a multi-quantum well layer 6, an electron blocking layer 7, a high-temperature P-type layer 8, and a P-type contact layer 9 sequentially stacked on the sapphire substrate 1.
The 3D nucleation layer 3 comprises a first sublayer 31 and a second sublayer 32, the first sublayer 31 is a GaN layer grown at 800-1100 ℃, and the second sublayer 32 is a GaN layer grown at 1000-1200 ℃.
According to the embodiment of the invention, the 3D nucleation layer is divided into a first sublayer and a second sublayer, the first sublayer is a GaN layer grown at 800-1100 ℃, and the second sublayer is a GaN layer grown at 1000-1200 ℃. Because the growth mode of the GaN epitaxial wafer is mainly a nuclear growth mode, deposited atoms are firstly condensed and nucleated after reaching the sapphire substrate, and the subsequent deposited atoms are continuously gathered near the nuclei, so that the nuclei are continuously grown in the three-dimensional direction to finally form the film. In the growth stage of the 3D nucleation layer, crystal nuclei are mainly formed on the AlN buffer layer and are continuously grown to form small islands. In the application, the growth temperature of the first sublayer is low, and formed grains are small and dense; when the crystal grains are mutually fused, gaps exist at the junctions due to the inconsistent orientation, so that larger surface energy exists, in order to reduce the surface energy, the crystal grains are stretched and deformed to close the gaps, the surface energy is reduced, tensile stress is generated, the epitaxial wafer is promoted to develop towards the direction of dishing (namely the direction opposite to the growth direction of the epitaxial wafer), the warping of the epitaxial wafer is improved, the surface of the sapphire substrate is flat, and heat can be uniformly transferred to the multiple quantum well layer when the multiple quantum well layer is grown, so that the uniformity of the light emitting wavelength is improved. And the whole epitaxial wafer is warped and concaved, so that the improvement of the lattice stress of the multi-quantum well layer is facilitated, and the photoelectric performance of the light emitting diode chip is improved. The growth temperature of the second sublayer is higher in the application, so that the surface energy of the crystal grains is reduced, and the epitaxial wafer is ensured not to be further warped.
Further, the thickness of the 3D nucleation layer 3 is 2-30 nm. If the thickness of the 3D nucleation layer 3 is less than 2nm, the improvement effect of the 3D nucleation layer 3 on the warpage of the epitaxial wafer is not good, and if the thickness of the 3D nucleation layer 3 is greater than 30nm, waste is caused.
Wherein, the thickness of the first sub-layer 31 is 1-10 nm, and the thickness of the second sub-layer 32 is 1-20 nm.
Preferably, the thickness of the 3D nucleation layer 3 is 15 nm. The thickness of the first sub-layer 31 is 5nm, and the thickness of the second sub-layer 32 is 10 nm. The first sublayer 31 and the second sublayer 32 have the best effect of improving the warpage of the epitaxial wafer.
Preferably, the first sub-layer 31 is an undoped GaN layer grown at 1000 ℃, and the second sub-layer 32 is an undoped GaN layer grown at 1100 ℃. In this case, the effect of improving the warpage of the epitaxial wafer is best.
Optionally, the growth pressure of the first sublayer 31 and the growth pressure of the second sublayer 32 are both 200-400 torr.
Optionally, the thickness of the undoped GaN layer 4 is 1-5 μm.
Optionally, the thickness of the N-type layer 5 is 1-5 μm, the N-type layer 5 is a GaN layer doped with Si, and the doping concentration of Si may be 1 × 1018～1×1019cm-3。
Optionally, the multiple quantum well layer 6 is a superlattice structure comprising an InGaN well layer and a GaN barrier layer, and the number of cycles of the multiple quantum well layer 6 is 5-11. Wherein the thickness of each InGaN potential well layer is 2-3nm, and the thickness of each GaN barrier layer is 9-20 nm.
Optionally, the electron blocking layer 7 is Al with a thickness of 20-100 nmyGa1-yN layer, y is more than 0.1 and less than 0.5.
Optionally, the high-temperature P-type layer 8 is a GaN layer with a thickness of 100-800 nm.
Optionally, the P-type contact layer 9 is a GaN layer with a thickness of 5-300 nm.
Example two
The embodiment of the present invention provides a method for manufacturing a gallium nitride-based light emitting diode epitaxial wafer, which is suitable for a gallium nitride-based light emitting diode epitaxial wafer provided in the first embodiment of the present invention, and fig. 2 is a flowchart of a method for manufacturing a gallium nitride-based light emitting diode epitaxial wafer provided in the first embodiment of the present invention, and as shown in fig. 2, the method for manufacturing the gallium nitride-based light emitting diode epitaxial wafer includes:
step 201, a sapphire substrate is provided.
Specifically, the sapphire substrate is sapphire with a thickness of 630-650 um.
In this example, a growth method of L ED was carried out using a Veeco K465i or C4 MOCVD (Metal Organic Chemical vapor deposition) apparatus2(Hydrogen) or high purity N2(Nitrogen) or high purity H2And high purity N2The mixed gas of (2) is used as a carrier gas, high-purity NH3As the N source, trimethyl gallium (TMGa) and triethyl gallium (TEGa) were used as the gallium source, trimethyl indium (T min) was used as the indium source, silane (SiH4) was used as the N-type dopant, and trimethyl aluminum (TMAl) was used as the aluminumSource, magnesium Dicyclopenta (CP)2Mg) as a P-type dopant. The pressure in the reaction chamber is 100-600 torr.
Specifically, the step 201 includes:
and processing the sapphire substrate at a high temperature for 5-20 minutes in a hydrogen atmosphere. Wherein the temperature of the reaction chamber is 1000-1200 ℃, the pressure of the reaction chamber is controlled at 200-500torr, and the sapphire substrate is subjected to nitridation treatment.
Step 202, growing an AlN buffer layer on the sapphire substrate.
Specifically, step 202 may include: after the sapphire substrate is processed at high temperature, the sapphire substrate is placed into PVD equipment, and a layer of AlN is sputtered on the sapphire substrate to obtain an AlN buffer layer.
When growing the AlN buffer layer, the growth temperature may be 500-700 ℃.
Further, after the AlN buffer layer is grown, the temperature of the reaction chamber is raised to 1000-1100 ℃, and the sapphire substrate plated with the AlN buffer layer is annealed for 10-15 minutes.
Step 203, growing a 3D nucleation layer on the AlN buffer layer.
Specifically, step 203 may include: and placing the sapphire substrate with the AlN buffer layer in MOCVD equipment, carrying out high-temperature heat treatment on the sapphire substrate in a hydrogen atmosphere for 10-15 minutes, and growing a 3D nucleating layer on the AlN buffer layer.
In this embodiment, the 3D nucleation layer includes a first sublayer and a second sublayer, the first sublayer is a GaN layer, the growth temperature is 800 to 1100 ℃, the second sublayer is a GaN layer, and the growth temperature is 1000 to 1200 ℃.
Preferably, the growth temperature of the first sub-layer is 900-1100 ℃, and the growth temperature of the second sub-layer is 1000-1200 ℃.
More preferably, the growth temperature of the first sub-layer is 1000 ℃, and the growth temperature of the second sub-layer is 1100 ℃, at which the first sub-layer and the second sub-layer grown at the temperature have the best effect of improving the lattice stress of the multiple quantum well layer, and the photoelectric performance of the L ED chip is the best.
Furthermore, the growth pressure of the first sublayer and the second sublayer is 200-400 torr.
Further, the thickness of the 3D nucleation layer is 1-30 nm. If the thickness of the 3D nucleation layer is less than 1nm, the 3D nucleation layer has a poor effect of improving the warpage of the epitaxial wafer, and if the thickness of the 3D nucleation layer is greater than 30nm, waste is caused.
Preferably, the thickness of the first sub-layer is 1-10 nm, and the thickness of the second sub-layer is 1-20 nm.
Preferably, the thickness of the 3D nucleation layer 3 is 15 nm. The thickness of the first sub-layer 31 is 5nm, and the thickness of the second sub-layer 32 is 10 nm. The first sublayer 31 and the second sublayer 32 have the best effect of improving the warpage of the epitaxial wafer.
Step 204, growing an undoped GaN layer on the 3D nucleation layer.
In the present embodiment, the thickness of the undoped GaN layer is 1-5 um. When growing the undoped GaN layer, the temperature of the reaction chamber is 1000-1100 ℃, and the pressure of the reaction chamber is controlled at 100-500 torr.
Step 205, an N-type layer is grown on the undoped GaN layer.
In the present embodiment, the N-type layer is a Si-doped GaN layer, and when the N-type layer is grown with a thickness of 1-5 um., the temperature of the reaction chamber is 1000-1200 deg.C, and the pressure of the reaction chamber is controlled at 100-500torr, wherein the doping concentration of Si is 1 × 1018～1×1019cm-3。
Step 206: and growing the multi-quantum well layer on the N-type layer.
The multi-quantum well layer is of a superlattice structure comprising an InGaN well layer and a GaN barrier layer, and the periodicity of the multi-quantum well layer is 5-11. Wherein the growth temperature of the InGaN well layer is 720-829 ℃, the growth pressure is 100-500Torr, the thickness is 2-3nm, the growth temperature of the GaN barrier layer is 850-959 ℃, the growth pressure is 100-500Torr, and the thickness is 9-20 nm.
Step 207: and growing an electron barrier layer on the multi-quantum well layer.
Optionally, the electron blocking layer is AlyGa1-yAnd the N layer, y is more than 0.1 and less than 0.5, the growth temperature is 200-1000 ℃, the growth pressure is 50-500 Torr, and the growth thickness is 20-100 nm.
Step 208, a high temperature P-type layer is grown on the electron blocking layer.
Optionally, the high-temperature P-type layer is a GaN layer, the growth temperature is 600-1000 ℃, the growth pressure is 100-300Torr, and the thickness is 100-800 nm.
Step 209 is to grow a P-type contact layer on the high temperature P-type layer.
Optionally, the P-type contact layer is a GaN layer, the growth temperature is 850-1050 ℃, the growth pressure is 100-300Torr, and the thickness is 5-300 nm.
After the growth of the GaN-based light emitting diode epitaxial wafer is finished, the temperature in the MOCVD equipment is reduced to 650-850 ℃, and the GaN-based light emitting diode epitaxial wafer is annealed for 5-15 minutes in a nitrogen atmosphere. Then, the temperature was gradually decreased to room temperature. Subsequently, a single 9 × 27mil chip was fabricated by subsequent processing of cleaning, deposition, photolithography, and etching.
Fig. 3 is a graph showing warpage changes of a first quantum well layer of a different chip according to an embodiment of the present invention, as shown in fig. 3, where the first quantum well layer is one of multiple quantum well layers closest to an N-type layer, an ordinate of the warpage changes shows warpage values, and an abscissa of the warpage changes shows sample numbers, where 1 st to 15 th are chip samples manufactured by using the prior art, and 16 th to 30 th are chip samples manufactured by using the manufacturing method according to the second embodiment. Referring to fig. 3, a line segment a represents an average value of warpage values of a first quantum well in a plurality of chips manufactured by a manufacturing method in the related art, a point near the line segment a represents a warpage value of a first quantum well in a plurality of chips manufactured by a manufacturing method in the related art, a line segment B represents an average value of warpage values of a first quantum well in a plurality of chips manufactured by a manufacturing method in the second embodiment, and a point near the line segment B represents a warpage value of a first quantum well in a plurality of chips manufactured by a manufacturing method in the second embodiment.
When the epitaxial wafer is integrally warped and deformed to be concave, the improvement of the lattice stress of the multiple quantum well layer is facilitated, and the photoelectric performance of the L ED chip is improved.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A gallium nitride-based light emitting diode epitaxial wafer comprises a sapphire substrate, and an AlN buffer layer, a 3D nucleating layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electron blocking layer, a high-temperature P-type layer and a P-type contact layer which are sequentially stacked on the sapphire substrate,
the 3D nucleation layer comprises a first sublayer and a second sublayer, the first sublayer is a GaN layer grown at 1000 ℃, the second sublayer is a GaN layer grown at 1100 ℃, the thickness of the 3D nucleation layer is 2-30 nm, the thickness of the first sublayer is 1-10 nm, and the thickness of the second sublayer is 1-20 nm.
2. A manufacturing method of a gallium nitride-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a sapphire substrate;
growing an AlN buffer layer on the sapphire substrate;
growing a 3D nucleation layer on the AlN buffer layer, wherein the 3D nucleation layer comprises a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are GaN layers, the growth temperature of the first sub-layer is 1000 ℃, the growth temperature of the second sub-layer is 1100 ℃, the thickness of the 3D nucleation layer is 2-30 nm, the thickness of the first sub-layer is 1-10 nm, and the thickness of the second sub-layer is 1-20 nm;
and growing an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a high-temperature P-type layer and a P-type contact layer on the 3D nucleating layer in sequence.
3. The manufacturing method according to claim 2, wherein growing an AlN buffer layer on the sapphire substrate includes:
and putting the sapphire substrate into PVD equipment, and sputtering a layer of AlN on the sapphire substrate to obtain the AlN buffer layer.
4. A method of manufacturing according to claim 2 or 3, wherein growing a 3D nucleation layer on the AlN buffer layer comprises:
placing the sapphire substrate with the AlN buffer layer in MOCVD equipment, and carrying out high-temperature heat treatment on the sapphire substrate in a hydrogen atmosphere for 10-15 minutes;
growing the 3D nucleation layer on the AlN buffer layer.
5. The manufacturing method according to claim 4, characterized by further comprising:
and after the growth of the P-type contact layer is finished, reducing the temperature in the MOCVD equipment to 650-850 ℃, and annealing the GaN-based light-emitting diode epitaxial wafer for 5-15 minutes in a nitrogen atmosphere.
6. The method of claim 2 or 3, wherein the first and second sublayers are grown at a pressure of 200 to 400 torr.
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CN113690350B (en) * 2021-07-29 2023-05-09 华灿光电（浙江）有限公司 Micro light-emitting diode epitaxial wafer and manufacturing method thereof
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