CN109659407B - GaN-based light emitting diode epitaxial wafer and preparation method thereof - Google Patents

GaN-based light emitting diode epitaxial wafer and preparation method thereof Download PDF

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CN109659407B
CN109659407B CN201811288866.1A CN201811288866A CN109659407B CN 109659407 B CN109659407 B CN 109659407B CN 201811288866 A CN201811288866 A CN 201811288866A CN 109659407 B CN109659407 B CN 109659407B
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CN109659407A (en
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苏晨
王慧
肖扬
吕蒙普
胡加辉
李鹏
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HC Semitek Suzhou Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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Abstract

The invention discloses a GaN-based light-emitting diode epitaxial wafer and a preparation method thereof, and belongs to the technical field of light-emitting diodes. The method comprises the following steps: providing a substrate, wherein the substrate is a patterned sapphire substrate, and the bottom width of the patterned sapphire substrate is equal to or more than 2.9 micrometers; depositing a buffer layer on the substrate; depositing a GaN nucleating layer on the buffer layer, wherein the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, and the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer; and depositing a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer on the GaN nucleating layer in sequence.

Description

GaN-based light emitting diode epitaxial wafer and preparation method thereof
Technical Field
The invention relates to the technical field of light emitting diodes, in particular to a GaN-based light emitting diode epitaxial wafer and a preparation method thereof.
Background
GaN (gallium nitride) is a typical representative of third generation wide bandgap semiconductor materials, has excellent characteristics such as high thermal conductivity, high temperature resistance, acid and alkali resistance, high hardness and the like, and is widely used for manufacturing blue, green and ultraviolet light emitting diodes. GaN-based light emitting diodes generally include an epitaxial wafer and an electrode provided on the epitaxial wafer.
An existing epitaxial wafer of a GaN-based light emitting diode includes a substrate, and a buffer layer, a GaN nucleation layer, a filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer (also called as an active layer), an electron blocking layer, and a P-type layer sequentially grown on the substrate. When current flows, electrons of the N-type layer and holes of the P-type layer enter the well region of the multi-quantum well layer and are combined to emit visible light. Wherein the substrate is patterned blueGem substrate (Al)2O3). The patterned sapphire substrate is used for growing a GaN epitaxial layer (comprising other layers deposited on a buffer layer) to increase the reflection of the bottom layer of the epitaxial layer (comprising a GaN nucleating layer and a filling layer), and the wider the bottom width of the pattern is, the more favorable the light emission of the device is.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems: growing the GaN epitaxial layer on the patterned sapphire substrate mainly obtains the GaN epitaxial layer generated based on the c-direction of sapphire. For patterned sapphire substrates, the substrate surface between the patterns is the c-plane of the sapphire substrate. When the pattern period is constant and the bottom width of the pattern becomes large, the area of the sapphire c-plane between the patterns becomes small, which increases the difficulty of growing an epitaxial layer on the c-plane.
Disclosure of Invention
The embodiment of the invention provides a GaN-based light emitting diode epitaxial wafer and a preparation method thereof, which can grow a GaN-based epitaxial layer under the condition that the area of a c-direction surface of sapphire is smaller. The technical scheme is as follows:
in one aspect, a method for preparing a GaN-based light emitting diode epitaxial wafer is provided, the method comprising:
providing a substrate, wherein the substrate is a patterned sapphire substrate, and the bottom width of the patterned sapphire substrate is equal to or more than 2.9 micrometers;
depositing a buffer layer on the substrate;
depositing a GaN nucleating layer on the buffer layer, wherein the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, and the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer;
and depositing a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer on the GaN nucleating layer in sequence.
Optionally, the depositing a GaN nucleation layer on the buffer layer includes:
the drive is deposited the substrate of buffer layer rotates to the pivoted deposit on the buffer layer high temperature low pressure GaN layer with low temperature high pressure GaN layer, the growth temperature on high temperature low pressure GaN layer is 1030 ~ 1060 ℃, and growth pressure is 100 ~ 300torr, the growth temperature on low temperature high pressure GaN layer is 1000 ~ 1030 ℃, and growth pressure is 400 ~ 600torr, the thickness on high temperature low pressure GaN layer is less than the thickness on low temperature high pressure GaN layer, the thickness on GaN nucleation layer is 1 ~ 2 microns.
Optionally, when the high-temperature low-pressure GaN layer is deposited, the rotation speed of the substrate is 1000-1200 rpm,
and when the low-temperature high-pressure GaN layer is deposited, the rotating speed of the substrate is 400-600 revolutions per minute.
Optionally, the buffer layer includes an AlN layer and a BGaN layer, the AlN layer is located between the substrate and the BGaN layer, and the depositing the buffer layer on the substrate includes:
depositing the AlN layer on the substrate, wherein the thickness of the AlN layer is 5-20 nm, the growth pressure of the AlN layer is 100-200 torr, and the growth temperature of the AlN layer is 500-600 ℃;
and depositing the BGaN layer on the AlN layer, wherein the thickness of the BGaN layer is 10-30 nm, the growth pressure of the BGaN layer is 100-200 torr, and the growth temperature of the BGaN layer is 500-600 ℃.
Optionally, the depositing the BGaN layer on the AlN layer includes:
placing the substrate deposited with the AlN layer into a growth chamber of metal organic compound chemical vapor deposition equipment;
continuously introducing a first reaction gas into the growth chamber and introducing a second reaction gas into the growth chamber at intervals to deposit the BGaN layer on the AlN layer, wherein the first reaction gas comprises TEB and NH3And the second reaction gas includes TMGa or TEGa.
Optionally, the thickness of the GaN high-temperature filling layer is 1-2 micrometers, the growth pressure of the GaN high-temperature filling layer is 100-300 torr, and the growth temperature of the GaN high-temperature filling layer is 1100-1150 ℃.
In another aspect, there is provided a GaN-based light emitting diode epitaxial wafer, including: the GaN-based high-temperature and low-pressure patterned sapphire substrate comprises a patterned sapphire substrate, and a buffer layer, a GaN nucleating layer, a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer which are sequentially deposited on the patterned sapphire substrate, wherein the bottom width of the patterned sapphire substrate is equal to or larger than 2.9 micrometers, the GaN nucleating layer comprises a high-temperature and low-pressure GaN layer and a low-temperature and high-pressure GaN layer, and the high-temperature and low-pressure GaN layer is positioned between the buffer layer and the low-temperature and high.
Optionally, the thickness of the high-temperature low-pressure GaN layer is smaller than that of the low-temperature high-pressure GaN layer, and the thickness of the GaN nucleation layer is 1-2 microns.
Optionally, the buffer layer comprises an AlN layer and a BGaN layer, the AlN layer being located between the substrate and the BGaN layer.
Optionally, the AlN layer is 5-20 nm thick, and the BGaN layer is 10-30 nm thick.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer, the growth of the GaN nucleating layer mainly forms crystal nuclei on the buffer layer and continuously grows to form small islands, the initial growth stage of the GaN nucleating layer is beneficial to forming initial GaN islands on the patterns on the patterned sapphire substrate and on the c-direction surfaces of the sapphire among the patterns in a high-temperature low-pressure growth mode, and the three-dimensional direction of the initial GaN islands is mostly the same as that of the GaN islands formed on the c-direction surfaces of the sapphire; in the later growth stage of the GaN nucleating layer, the three-dimensional growth of a GaN island formed on the c-direction surface of the sapphire is facilitated by a low-temperature and high-pressure growth mode, so that the two-step growth mode of the GaN nucleating layer is adopted, the nucleation can be better performed on a large-bottom-width patterned sapphire substrate and the smaller area of the c-direction surface of the sapphire is realized, and the external quantum efficiency of the device is increased on the basis of ensuring that the crystal quality is not deteriorated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for fabricating an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 illustrates a method for preparing an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention. Referring to fig. 1, the process flow includes the following steps.
Step 101, providing a substrate.
The substrate is a patterned sapphire substrate, and the bottom width of the patterned sapphire substrate is equal to or larger than 2.9 micrometers.
Step 102, depositing a buffer layer on a substrate.
Illustratively, the buffer layer includes an AlN layer; alternatively, the buffer layer includes an AlN layer and a BGaN layer, the AlN layer being located between the substrate and the BGaN layer.
When the buffer layer comprises the AlN layer and the BGaN layer, as the radiuses of B atoms are respectively smaller than those of Al atoms and Ga atoms, B and Ga in the BGaN material are integrated, and the lattice constant of the BGaN material is close to that of the sapphire substrate, the AlN material and the GaN material, then, the transition from the sapphire substrate, the AlN material to the GaN material is carried out through the BGaN material, so that reverse compressive stress can be provided, the lattice mismatch among the sapphire substrate, the AlN material and the GaN material and the tensile stress caused by the large-bottom wide substrate are offset, the partial convex phenomenon of the multiple quantum well layer is reduced or eliminated, and the photoelectric conversion efficiency of the device is improved; meanwhile, on the basis of ensuring that the crystal quality is not deteriorated, the external quantum efficiency of the device can be increased due to the larger bottom width.
And 103, depositing a GaN nucleating layer on the buffer layer.
The GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, and the high-temperature low-pressure GaN layer is located between the buffer layer and the low-temperature high-pressure GaN layer.
And step 104, depositing a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer on the GaN nucleating layer in sequence.
According to the embodiment of the invention, the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer, the growth of the GaN nucleating layer mainly forms crystal nuclei on the buffer layer and continuously grows to form small islands, in the initial growth stage of the GaN nucleating layer, the initial GaN islands are formed on the patterns on the patterned sapphire substrate and on the sapphire c-direction surfaces between the patterns in a high-temperature low-pressure growth mode, and the three-dimensional directions of the initial GaN islands are mostly the same as the three-dimensional directions of the GaN islands formed on the sapphire c-direction surfaces; in the later growth stage of the GaN nucleating layer, the three-dimensional growth of a GaN island formed on the c-direction surface of the sapphire is facilitated by a low-temperature and high-pressure growth mode, so that the two-step growth mode of the GaN nucleating layer is adopted, the nucleation can be better performed on a large-bottom-width patterned sapphire substrate and the smaller area of the c-direction surface of the sapphire is realized, and the external quantum efficiency of the device is increased on the basis of ensuring that the crystal quality is not deteriorated.
Fig. 2 shows a method for preparing an epitaxial wafer of a GaN-based light emitting diode according to an embodiment of the invention. Referring to fig. 2, the process flow includes the following steps.
Step 201, a substrate is provided.
Illustratively, the Substrate may be a Patterned Sapphire Substrate (PSS). The GaN-based light emitting diode epitaxial wafer is grown by the PSS, so that the emergent light brightness of the light emitting diode can be enhanced, the reverse leakage current is reduced, and the service life of the light emitting diode is prolonged.
Illustratively, the base width of the PSS is equal to or greater than 2.9 microns. The base width is the diameter of the pattern on the PSS. PSS with a base width equal to or greater than 2.9 microns is also known as large cell base width substrate.
Illustratively, the base width of the PSS is 2.9 micrometers, and the pattern period of the PSS may be 3.0 micrometers or 3.05 micrometers, in which case the c-plane length between adjacent patterns is 0.1 or 0.15 micrometers. The c surface is the surface of the GaN-based epitaxial layer grown on the PSS.
Illustratively, the pattern height of the PSS is 1.7 to 2.0 microns.
Step 202, an AlN layer is deposited on the substrate.
Illustratively, a Physical Vapor Deposition (PVD) method, such as magnetron sputtering, is used to deposit an AlN layer on a substrate. The thickness of the AlN layer is 5-20 nm, the growth pressure of the AlN layer is 100-200 torr, and the growth temperature of the AlN layer is 500-600 ℃.
Illustratively, the BGaN layer, the GaN nucleation layer, the GaN high temperature fill layer, the undoped GaN layer, the N-type layer, the multi-quantum well layer, and the P-type layer may be deposited in a Metal-organic chemical vapor Deposition (MOCVD) method. The preparation method can be realized by MOCVD equipment. In the preparation process, high purity H is used2(hydrogen gas), and N2(Nitrogen) as carrier gas, TMGa (trimethyl gallium) or TEGa (triethyl gallium) as Ga source, TMAl (trimethyl aluminum) as Al source, TEB (triethyl boron) as B source, TMIn (trimethyl indium) as In source, and NH3(Ammonia) as N source, SiH4(silane) as N-type dopant, with CP2Mg (magnesium dicylocene) as a P-type dopant.
Step 203, at H2And carrying out preheating treatment on the substrate deposited with the AlN layer in the atmosphere.
Specifically, the substrate on which the AlN layer is deposited is placed in an MOCVD apparatus so that the substrate is in H2Heat treatment is carried out for 10-15 minutes in the atmosphere, and the heat treatment temperature can be 1000-1040 ℃.
And 204, driving the substrate deposited with the AlN layer to rotate, and sequentially depositing a BGaN layer, a GaN nucleating layer, a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer on the substrate.
Specifically, the substrate on which the AlN layer is deposited is placed on a tray of a growth chamber of the MOCVD apparatus. In the process of growing the GaN-based epitaxial layer by the MOCVD apparatus, the tray is driven to rotate to grow the GaN-based epitaxial layer on the rotating substrate. Step 204 includes steps 2041-2049 as follows.
And 2041, depositing a BGaN layer on the rotating AlN layer.
Illustratively, step 2041 may include: and continuously introducing a first reaction gas into the growth chamber and introducing a second reaction gas into the growth chamber at intervals so as to deposit the BGaN layer on the AlN layer. Wherein the first reaction gas comprises TEB and NH3And the second reaction gas includes TMGa or TEGa.
Exemplary implementations of the spaced introduction of the second reactant gas include: and electrifying to generate a pulse signal, and then introducing a second reaction gas into the growth chamber within the electrifying time of the pulse period. Wherein, the duty ratio of the pulse signal can be 10% -60%.
Illustratively, the thickness of the BGaN layer is 10-30 nm, the growth pressure of the BGaN layer is 100-200 torr, and the growth temperature of the BGaN layer is 500-600 ℃.
The growth temperature of the BGaN layer is low. The nucleation island is formed in favor of the lower growth temperature. However, the surface mobility of B atoms is also low at low temperature, and if Ga source and B source are continuously introduced into the growth chamber, the low surface mobility of B will result in too dense nucleation islands, resulting in more defects at the fill interface between patterns on the substrate. In order to solve the problem, a mode of introducing TMGa or TEGa at intervals is adopted, the number of B atoms is increased, and the surface mobility of B is improved, so that the defect that a filling interface generates more defects due to the fact that nucleation islands are too dense due to the low surface mobility of B can be avoided, and the crystal quality of a GaN epitaxial layer is improved. In addition, the mode of introducing TMGa or TEGa at intervals is adopted, so that the pre-reaction generated between the introduced Ga source and the Al source can be reduced, and the influence of the pre-reaction on the crystal quality of the GaN epitaxial layer is avoided.
And 2042, depositing a high-temperature low-pressure GaN layer on the rotating BGaN layer.
Illustratively, the growth temperature of the high-temperature low-pressure GaN layer is 1030-1060 ℃, and the growth pressure is 100-300 torr.
Illustratively, the substrate is rotated at a speed of 1000 to 1200 rpm when the high temperature and low pressure GaN layer is deposited.
2043, depositing a low-temperature high-pressure GaN layer on the rotating high-temperature low-pressure GaN layer.
Illustratively, the growth temperature of the low-temperature high-pressure GaN layer is 1000-1030 ℃ and the growth pressure is 400-600 torr.
Illustratively, the substrate is rotated at a speed of 400-600 rpm when the low-temperature high-pressure GaN layer is deposited.
Illustratively, the flow rate of TMGa or TEGa introduced by the growth high-temperature low-pressure GaN layer is smaller than that of TMGa or TEGa introduced by the growth low-temperature high-pressure GaN layer. Therefore, the growth rate of the low-temperature high-pressure GaN layer is far greater than that of the high-temperature low-pressure GaN layer under the growth conditions of high pressure and high flow, and the formation of GaN islands is facilitated.
Illustratively, the thickness of the high-temperature low-pressure GaN layer is smaller than that of the low-temperature high-pressure GaN layer, and the thickness of the GaN nucleating layer is 1-2.0 microns.
The growth temperature of the GaN nucleation layer is higher compared to the BGaN layer. A part of the low-temperature BGaN layer is melted at a higher temperature, and because the growth temperature of the BGaN layer is lower and the crystal quality is poor, a part of the BGaN layer is melted, and the GaN nucleating layer is grown at a high temperature, so that the crystal quality can be improved.
In addition, the substrate rotation speed ratio is large when depositing the high-temperature low-pressure GaN layer, and is small when depositing the low-temperature high-pressure GaN layer, which is beneficial to better nucleation.
And 2044, depositing a GaN high-temperature filling layer on the rotating low-temperature high-pressure GaN layer.
Illustratively, the thickness of the GaN high-temperature filling layer is 1-2 microns, the growth pressure of the GaN high-temperature filling layer is 100-300 torr, and the growth temperature of the GaN high-temperature filling layer is 1100-1150 ℃.
Illustratively, the sum of the thicknesses of the GaN nucleation layer and the GaN high temperature fill layer does not exceed 2 microns. Thus, it is sufficient to fully grow the gaps between the patterns of the PSS.
Compared with the GaN nucleating layer, the temperature of the GaN high-temperature filling layer is higher, which is beneficial to filling gaps between the patterns, increasing the area of the c surface and obtaining better crystal quality.
Step 2045, an undoped GaN layer is deposited on the GaN high temperature fill-level layer.
Illustratively, the growth temperature of the undoped GaN layer may be 1000 deg.C to 1100 deg.C, and the growth pressure may be between 100Torr and 500 Torr. The growth thickness of the undoped GaN layer may be 1.0 to 5.0 micrometers.
Step 2046, deposit an N-type layer on the undoped GaN layer.
Illustratively, the N-type layer is an N-type doped GaN layer, the thickness of the N-type doped GaN layer is between 1 and 5 microns, the growth temperature of the N-type doped GaN layer can be 1000-1200 ℃, and the growth pressure is between 100Torr and 500 Torr. The N-type doped GaN layer is doped with Si with a doping concentration of 1018cm-3～1019cm-3In the meantime.
Step 2047, deposit the multiple quantum well layer on the N-type layer.
Illustratively, the multiple quantum well layer may be composed of 3 to 15 periods of quantum well barrier layers. The quantum well barrier layer comprises InxGa1-xN(0<x<1) The quantum well and the GaN quantum barrier, the thickness of the quantum well is about 3nm, the growth temperature range is 720-829 ℃, and the growth pressure range is between 100Torr and 500 Torr. The thickness of the quantum barrier is between 9nm and 20nm, the growth temperature is between 850 ℃ and 959 ℃, and the growth pressure is between 100Torr and 500 Torr.
Step 2048, deposit a P-type layer on the multiple quantum well layer.
Illustratively, the P-type layer is a P-type doped GaN layer. The growth temperature of the P-type doped GaN layer is 850-1080 ℃, and the growth pressure interval is 200-300 Torr. The thickness of the P-type doped GaN layer is between 100nm and 800 nm.
Step 2049, a P-type composite contact layer is deposited on the P-type layer.
Illustratively, the growth temperature range of the P-type composite contact layer is 850-1050 ℃, and the growth pressure range is 100-300 Torr. The thickness of the P-type composite contact layer is between 5nm and 300 nm.
After the P-type composite contact layer is deposited, the temperature in the growth chamber of the MOCVD can be reduced, the epitaxial wafer is annealed in a nitrogen atmosphere, the annealing temperature can be 650-850 ℃, the annealing time can be 5-15 minutes, and then the temperature is reduced to the room temperature, so that the growth of the epitaxial wafer is finished.
According to the embodiment of the invention, the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer, the growth of the GaN nucleating layer mainly forms crystal nuclei on the buffer layer and continuously grows to form small islands, in the initial growth stage of the GaN nucleating layer, the initial GaN islands are formed on the patterns on the patterned sapphire substrate and on the sapphire c-direction surfaces between the patterns in a high-temperature low-pressure growth mode, and the three-dimensional directions of the initial GaN islands are mostly the same as the three-dimensional directions of the GaN islands formed on the sapphire c-direction surfaces; in the later growth stage of the GaN nucleating layer, the three-dimensional growth of a GaN island formed on the c-direction surface of the sapphire is facilitated by a low-temperature and high-pressure growth mode, so that the two-step growth mode of the GaN nucleating layer is adopted, the nucleation can be better performed on a large-bottom-width patterned sapphire substrate and the smaller area of the c-direction surface of the sapphire is realized, and the external quantum efficiency of the device is increased on the basis of ensuring that the crystal quality is not deteriorated.
Fig. 3 shows a GaN-based light emitting diode epitaxial wafer according to an embodiment of the present invention, referring to fig. 3, the epitaxial wafer includes: a substrate 31, a buffer layer 32, a GaN nucleation layer 33, a GaN high temperature fill layer 34, an undoped GaN layer 35, an N-type layer 36, a multiple quantum well layer 37, and a P-type layer 38 sequentially deposited on the substrate 31. The substrate 31 is PSS having a base width equal to or greater than 2.9 micrometers. The GaN nucleation layer 33 includes a high-temperature and low-pressure GaN layer 331 and a low-temperature and high-pressure GaN layer 332, and the high-temperature and low-pressure GaN layer 331 is located between the buffer layer 32 and the low-temperature and high-pressure GaN layer 332.
Illustratively, the thickness of the high-temperature and low-pressure GaN layer 331 is smaller than that of the low-temperature and high-pressure GaN layer 332, and the thickness of the GaN nucleation layer 33 is 1-2 microns.
Illustratively, buffer layer 32 includes an AlN layer 321 and a BGaN layer 322, AlN layer 321 being located between substrate 31 and BGaN layer 322.
Illustratively, the AlN layer is a low-temperature AlN layer, and the thickness of the AlN layer is 5-20 nm; the BGaN layer is a low-temperature BGaN layer, and the thickness of the BGaN layer is 10-30 nm.
Illustratively, the thickness of the GaN high-temperature flat-filling layer is 1-2 microns.
Illustratively, the pattern height of the PSS is 1.7-2.0 microns, and the sum of the thicknesses of the GaN nucleating layer and the GaN high-temperature filling layer is not more than 2 microns. Thus, it is sufficient to fully grow the gaps between the patterns of the PSS.
According to the embodiment of the invention, the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer, the growth of the GaN nucleating layer mainly forms crystal nuclei on the buffer layer and continuously grows to form small islands, in the initial growth stage of the GaN nucleating layer, the initial GaN islands are formed on the patterns on the patterned sapphire substrate and on the sapphire c-direction surfaces between the patterns in a high-temperature low-pressure growth mode, and the three-dimensional directions of the initial GaN islands are mostly the same as the three-dimensional directions of the GaN islands formed on the sapphire c-direction surfaces; in the later growth stage of the GaN nucleating layer, the three-dimensional growth of a GaN island formed on the c-direction surface of the sapphire is facilitated by a low-temperature and high-pressure growth mode, so that the two-step growth mode of the GaN nucleating layer is adopted, the nucleation can be better performed on a large-bottom-width patterned sapphire substrate and the smaller area of the c-direction surface of the sapphire is realized, and the external quantum efficiency of the device is increased on the basis of ensuring that the crystal quality is not deteriorated.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (9)

1. A preparation method of a GaN-based light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate, wherein the substrate is a patterned sapphire substrate, and the bottom width of the patterned sapphire substrate is equal to or more than 2.9 micrometers;
depositing a buffer layer on the substrate;
depositing a GaN nucleating layer on the buffer layer, wherein the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, and the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer;
depositing a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer on the GaN nucleating layer in sequence,
the depositing a GaN nucleation layer on the buffer layer includes:
the substrate deposited with the buffer layer is driven to rotate, the high-temperature low-pressure GaN layer and the low-temperature high-pressure GaN layer are deposited on the rotating buffer layer, the growth temperature of the high-temperature low-pressure GaN layer is 1030-1060 ℃, the growth pressure of the high-temperature low-pressure GaN layer is 100-300 torr, the growth temperature of the low-temperature high-pressure GaN layer is 1000-1030 ℃, the growth pressure of the low-temperature high-pressure GaN layer is 400-600 torr, the thickness of the high-temperature low-pressure GaN layer is smaller than that of the low-temperature high-pressure GaN layer, and the thickness of the GaN nucleating layer is 1-2,
the flow of TMGa or TEGa introduced for growing the high-temperature low-pressure GaN layer is smaller than that of TMGa or TEGa introduced for growing the low-temperature high-pressure GaN layer.
2. The method of claim 1,
when the high-temperature low-pressure GaN layer is deposited, the rotating speed of the substrate is 1000-1200 r/min,
and when the low-temperature high-pressure GaN layer is deposited, the rotating speed of the substrate is 400-600 revolutions per minute.
3. The method of claim 1, wherein the buffer layer comprises an AlN layer and a BGaN layer, the AlN layer being between the substrate and the BGaN layer, the depositing a buffer layer on the substrate comprising:
depositing the AlN layer on the substrate, wherein the thickness of the AlN layer is 5-20 nm, the growth pressure of the AlN layer is 100-200 torr, and the growth temperature of the AlN layer is 500-600 ℃;
and depositing the BGaN layer on the AlN layer, wherein the thickness of the BGaN layer is 10-30 nm, the growth pressure of the BGaN layer is 100-200 torr, and the growth temperature of the BGaN layer is 500-600 ℃.
4. The method of claim 3, wherein said depositing said BGaN layer on said AlN layer comprises:
placing the substrate deposited with the AlN layer into a growth chamber of metal organic compound chemical vapor deposition equipment;
continuously introducing a first reaction gas into the growth chamber and introducing a second reaction gas into the growth chamber at intervals to deposit the BGaN layer on the AlN layer, wherein the first reaction gas comprises TEB and NH3And the second reaction gas includes TMGa or TEGa.
5. The method of claim 1, wherein the thickness of the GaN high temperature flat-fill layer is 1-2 μm, the growth pressure of the GaN high temperature flat-fill layer is 100-300 torr, and the growth temperature of the GaN high temperature flat-fill layer is 1100-1150 ℃.
6. A GaN-based light emitting diode epitaxial wafer, comprising: the patterned sapphire substrate comprises a patterned sapphire substrate, a buffer layer, a GaN nucleating layer, a GaN high-temperature filling layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer and a P-type layer which are sequentially deposited on the patterned sapphire substrate, wherein the bottom width of the patterned sapphire substrate is equal to or more than 2.9 microns, the GaN nucleating layer comprises a high-temperature low-pressure GaN layer and a low-temperature high-pressure GaN layer, the high-temperature low-pressure GaN layer is positioned between the buffer layer and the low-temperature high-pressure GaN layer,
the GaN nucleating layer is prepared in the following way:
the drive is deposited the substrate of buffer layer rotates, and is in the pivoted deposit on the buffer layer high temperature low pressure GaN layer with low temperature high pressure GaN layer, the growth temperature on high temperature low pressure GaN layer is 1030 ~ 1060 ℃, and growth pressure is 100 ~ 300torr, the growth temperature on low temperature high pressure GaN layer is 1000 ~ 1030 ℃, and growth pressure is 400 ~ 600torr, the thickness on high temperature low pressure GaN layer is less than the thickness on low temperature high pressure GaN layer, the thickness on GaN nucleation layer is 1 ~ 2 microns, grows the flow of TMGa or TEGa that high temperature low pressure GaN layer lets in, be less than the growth the flow of TMGa or TEGa that low temperature high pressure GaN layer lets in.
7. The epitaxial wafer of claim 6, wherein the thickness of the high-temperature low-pressure GaN layer is less than that of the low-temperature high-pressure GaN layer, and the thickness of the GaN nucleation layer is 1-2 microns.
8. The epitaxial wafer of claim 6, wherein the buffer layer comprises an AlN layer and a BGaN layer, the AlN layer being located between the substrate and the BGaN layer.
9. The epitaxial wafer of claim 8, wherein the AlN layer has a thickness of 5 to 20nm, and the BGaN layer has a thickness of 10 to 30 nm.
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