CN109786513B

CN109786513B - Epitaxial wafer of light emitting diode and manufacturing method thereof

Info

Publication number: CN109786513B
Application number: CN201811608439.7A
Authority: CN
Inventors: 陶章峰; 张武斌; 程金连; 乔楠; 胡加辉; 李鹏
Original assignee: HC Semitek Zhejiang Co Ltd
Current assignee: HC Semitek Zhejiang Co Ltd
Priority date: 2018-12-27
Filing date: 2018-12-27
Publication date: 2020-08-18
Anticipated expiration: 2038-12-27
Also published as: CN109786513A

Abstract

The invention discloses an epitaxial wafer of a light emitting diode and a manufacturing method thereof, belonging to the technical field of photoelectron manufacturing. The epitaxial wafer comprises a substrate and a plurality of epitaxial layers sequentially formed on the substrateAlN buffer layer on bottom, B_xAl_1‑xThe LED comprises an N buffer layer, a three-dimensional nucleating layer, a two-dimensional buffer recovery layer, a u-type GaN layer, an N-type GaN layer, a stress release layer, a light-emitting layer and a p-type layer. By forming B between the AlN buffer layer and the three-dimensional nucleation layer_xAl_1‑xN buffer layer by adjusting B_xAl_1‑xThe content of B in the N buffer layer can be adjusted to_xAl_1‑xThe N buffer layer is well matched with the crystal lattices of the AlN buffer layer and the three-dimensional nucleating layer, so that the defect density is reduced. Since the atomic size of B is small, B is set_xAl_1‑xAfter the N buffer layer, stress opposite to the stress direction of the AlN buffer layer can be formed, so that the warping of the epitaxial wafer caused by the stress of the AlN buffer layer is reduced, and the wavelength uniformity is favorably improved.

Description

Epitaxial wafer of light emitting diode and manufacturing method thereof

Technical Field

The invention relates to the technical field of photoelectron manufacturing, in particular to an epitaxial wafer of a light emitting diode and a manufacturing method thereof.

Background

An LED (Light Emitting Diode) has the advantages of small size, long service life, low power consumption, and the like, and is currently widely used in automobile signal lamps, traffic signal lamps, display screens, and lighting devices.

The GaN-based LED epitaxial wafer generally comprises a substrate, and an AlN buffer layer, a three-dimensional nucleating layer, a two-dimensional buffer recovery layer, a u-type GaN layer, an n-type GaN layer, a stress release layer, a light-emitting layer and a p-type layer which are sequentially grown on the substrate. When the LED is powered on, carriers (including electrons of the n-type GaN layer and holes of the p-type layer) will migrate to the light-emitting layer and recombine in the light-emitting layer to emit light.

In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:

the existence of large stress between AlN and GaN due to lattice mismatch results in a higher density of threading and stacking dislocations and larger stress in the epitaxial wafer.

Disclosure of Invention

The embodiment of the invention provides an epitaxial wafer of a light emitting diode and a manufacturing method thereof, which can reduce stress of defect density in the epitaxial wafer. The technical scheme is as follows:

in one aspect, an embodiment of the present invention provides an epitaxial wafer of a light emitting diode, where the epitaxial wafer includes a substrate, and an AlN buffer layer and a B layer sequentially formed on the substrate_xAl_1-xThe N buffer layer, the three-dimensional nucleation layer, the two-dimensional buffer recovery layer, the u-type GaN layer, the N-type GaN layer, the stress release layer, the light-emitting layer and the p-type layer, wherein x is more than or equal to 0 and less than or equal to 0.2.

Optionally, B is_xAl_1-xThe composition content of B in the N buffer layer gradually increases from the AlN buffer layer side to the three-dimensional nucleation layer side.

Optionally, B is_xAl_1-xThe N buffer layer comprises a plurality of B_xAl_1-xN sublayers, the same as B_xAl_1-xThe component content of B in the N sub-layers is unchanged, and the plurality of B_xAl_1-xThe component content of B of the N sub-layer gradually increases from one side of the AlN buffer layer to one side of the three-dimensional nucleation layer.

Optionally, the plurality of B_xAl_1-xThe thickness of the N sublayers is the same.

Optionally, B is_xAl_1-xThe thickness of the N buffer layer is 15-30 nm.

On the other hand, the embodiment of the invention also provides a manufacturing method of the epitaxial wafer of the light emitting diode, which comprises the following steps:

providing a substrate;

epitaxially growing an AlN buffer layer and B on the substrate in sequence_xAl_1-xThe N buffer layer, the three-dimensional nucleation layer, the two-dimensional buffer recovery layer, the u-type GaN layer, the N-type GaN layer, the stress release layer, the light-emitting layer and the p-type layer, wherein x is more than or equal to 0 and less than or equal to 0.2.

Optionally, the plurality of B_xAl_1-xThe growth temperature of the N sub-layer is increased layer by layer from the AlN buffer layer side to the three-dimensional nucleation layer side.

Optionally, the plurality of B_xAl_1-xThe growth pressure of the N sub-layer is increased layer by layer from the AlN buffer layer side to the three-dimensional nucleation layer side.

Optionally, B is_xAl_1-xThe growth temperature of the N buffer layer is 1000-1100 ℃, and the growth pressure is 150-500 torr.

The technical scheme provided by the embodiment of the invention has the following beneficial effects: by forming B between the AlN buffer layer and the three-dimensional nucleation layer_xAl_1-xN buffer layer by adjusting B_xAl_1-xThe content of B in the N buffer layer can be adjusted to_xAl_1-xThe N buffer layer is well matched with the crystal lattices of the AlN buffer layer and the three-dimensional nucleating layer, so that the defect density is reduced. Meanwhile, because the atomic size of B is smaller, B is arranged_xAl_1-xAfter the N buffer layer, stress opposite to the stress direction of the AlN buffer layer can be formed, so that the warping of the epitaxial wafer caused by the stress of the AlN buffer layer is reduced, and the wavelength uniformity is favorably improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;

fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;

fig. 3 is a flowchart of another method for manufacturing a light emitting diode according to an embodiment of the present invention;

fig. 4 to 11 are schematic views illustrating a manufacturing process of an epitaxial wafer of a light emitting diode according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. As shown in FIG. 1, the epitaxial wafer comprises a substrate 10 and AlN buffer layers 20, B formed on the substrate 10 in this order_xAl_1-xThe N buffer layer 30, the three-dimensional nucleation layer 40, the two-dimensional buffer recovery layer 50, the u-type GaN layer 60, the N-type GaN layer 70, the stress release layer 80, the light emitting layer 90 and the p-type layer 100, wherein x is more than or equal to 0 and less than or equal to 0.2.

The embodiment of the invention forms B between the AlN buffer layer and the three-dimensional nucleation layer_xAl_1-xN buffer layer by adjusting B_xAl_1-xThe content of B in the N buffer layer can be adjusted to_xAl_1-xThe N buffer layer is well matched with the crystal lattices of the AlN buffer layer and the three-dimensional nucleating layer, so that the defect density is reduced. Meanwhile, because the atomic size of B is smaller, B is arranged_xAl_1-xAfter the N buffer layer, stress opposite to the stress direction of the AlN buffer layer can be formed, so that the warping of the epitaxial wafer caused by the stress of the AlN buffer layer is reduced, and the wavelength uniformity is favorably improved.

In addition, AlN material has large piezoelectric polarization and spontaneous polarization, and the luminous efficiency is lowered by setting B_xAl_1-xAfter N buffer layer, BAlN material has piezoelectric polarization opposite to AlN direction, and thus light emitting efficiency can also be improved.

Alternatively, the substrate 10 may be a sapphire substrate, which is a common substrate and has mature technology and low cost. In other embodiments, a Si substrate and a SiC substrate may be used. Preferably a patterned sapphire substrate.

The thickness of the AlN buffer layer 20 may be 10-15 nm, the grown AlN buffer layer 20 has different thicknesses, and the quality of the finally formed epitaxial layer may also be different, if the AlN buffer layer 20 is too thin, the surface of the AlN buffer layer 20 may be loose and rough, which may not provide a good template for the growth of the subsequent structure, and as the thickness of the AlN buffer layer 20 increases, the surface of the AlN buffer layer 20 gradually becomes more compact and smoother, which is beneficial to the growth of the subsequent structure, but if the AlN buffer layer 20 is too thick, the surface of the AlN buffer layer 20 may be too compact, which is not beneficial to the growth of the subsequent structure, and may not reduce the lattice defects in the epitaxial layer.

Alternatively, B_xAl_1-xThe composition content of B in the N buffer layer 30 may gradually increase from the AlN buffer layer 20 side toward the three-dimensional nucleation layer 40 side. The component content of B is set to be gradually increased, so that B can be made to be gradually increased_xAl_1-xThe lattice constant of the N buffer layer 30 on the side closer to the AlN buffer layer 20 is closer to that of the AlN buffer layer 20 so that B is closer to the AlN buffer layer 20_xAl_1-xThe lattice constant of the N buffer layer 30 on the side closer to the three-dimensional nucleation layer 40 is closer to the three-dimensional nucleation layer 40, which is beneficial to further reducing the defect density and improving the quality of the epitaxial wafer.

Alternatively, B_xAl_1-xThe N buffer layer 30 may have a thickness of 15 to 30 nm. If B is present_xAl_1-xThe N buffer layer 30 is too thin at B_xAl_1-xThe component content of B on both sides of the N buffer layer 30 is not changed, so that B is not changed_xAl_1-xThe variation gradient of the composition content of B in the N buffer layer 30 is too large, which is disadvantageous in reducing the defect density and stress. If B is present_xAl_1-xThe N buffer layer 30 is too thick, which increases the thickness of the epitaxial wafer, increases the manufacturing cost, and prolongs the production cycle.

As shown in FIG. 1, B_xAl_1-xThe N buffer layer 30 may include a plurality of B_xAl_1-xAnd an N sublayer 31. Same B_xAl_1-xThe component content of B in the N sublayer 31 is constant, and a plurality of B_xAl_1-xB of the N sublayer 31The component content of (a) gradually increases from the AlN buffer layer 20 side toward the three-dimensional nucleation layer 40 side. By mixing B_xAl_1-xThe N buffer layer 30 is provided to include a plurality of B_xAl_1-xThe structural form of the N sublayer 31 can facilitate B_xAl_1-xThe composition content of B of the N buffer layer 30 gradually changes.

Exemplarily, B_xAl_1-xThe N buffer layer 30 may include 5B_xAl_1-xN sublayer 31, 5B_xAl_1-xThe value of x in the N sublayer 31 may be 0, 0.05, 0.1, 0.15, and 0.2, respectively.

Alternatively, B_xAl_1-xThe thickness of the N sublayer 31 may be 4nm to 6 nm. Such as B_xAl_1-xThe thickness of the N sublayer 31 may be 5 nm. B is_xAl_1-xThe thickness of the N sublayer 31 is too thin to be easily controlled during growth, B_xAl_1-xThe N sublayer 31 is too thick at B_xAl_1-xWhen the total thickness of the N buffer layer 30 is constant, B is reduced_xAl_1-xNumber of N sublayers 31, which will be adjacent to B_xAl_1-xWhen the component content difference of B in the N sublayers 31 is constant, B_xAl_1-xThe lattice constant of the N buffer layer 30 on the side closer to the AlN buffer layer 20 is not close enough to the AlN buffer layer 20, B_xAl_1-xThe lattice constant of the N-buffer layer 30 on the side closer to the three-dimensional nucleation layer 40 is not close enough to the three-dimensional nucleation layer 40 to affect a reduction in defect density.

Optionally, the three-dimensional nucleation layer 40 may be a GaN layer. The thickness of the three-dimensional nucleation layer 40 may be 400nm to 600 nm. In this embodiment, the thickness of the three-dimensional nucleation layer 40 is 500 nm. Too thin a three-dimensional nucleation layer 40 reduces B_xAl_1-xThe lattice mismatch between the N-buffer layer 30 and the three-dimensional nucleation layer 40 is insignificant, and the growth cycle is extended if the three-dimensional nucleation layer 40 is too thick.

Optionally, the two-dimensional buffer recovery layer 50 may be a GaN layer, and the thickness of the two-dimensional buffer recovery layer 50 may be 500-800 nm. By growing the two-dimensional buffer recovery layer 50, the patterned sapphire substrate can be continuously filled and leveled, which is beneficial to the growth of subsequent structures. In this embodiment, the thickness of the two-dimensional buffer recovery layer 50 may be 650 nm.

Alternatively, the thickness of the u-type GaN layer 60 may be 1-2 μm, and in the present embodiment, the thickness of the u-type GaN layer 60 is 1.5 μm.

Alternatively, the thickness of the n-type GaN layer 70 may be 1-3 μm, and in the present embodiment, the thickness of the n-type GaN layer 70 is 2 μm.

The doping concentration of Si in the n-type GaN layer 70 may be 10¹⁸～10²⁰cm^-3。

As shown in fig. 1, the stress relieving layer 80 may include a periodic structure 82 in which a first n-type GaN sublayer 81, a multilayer InGaN layer 821, and a multilayer GaN layer 822 are alternately stacked, and a second n-type GaN sublayer 83. In the periodic structure 82, the number of layers of the InGaN layer 821 and the number of layers of the GaN layer 822 may be 2 to 10 (only 2 InGaN layers 821 and 2 GaN layers 822 are exemplarily shown in fig. 1), wherein one InGaN layer 821 is directly grown on the first n-type GaN sublayer 81. By alternately stacking the InGaN layers 821 and the GaN layers 822, the stress in the epitaxial wafer can be gradually reduced, which is beneficial to the growth of the subsequent light emitting layer and improves the crystal quality of the final epitaxial wafer.

Illustratively, the thickness of the first n-type GaN sublayer 81 may be 50nm, the thickness of the InGaN layer 821 may be 2nm, the thickness of the GaN layer 822 may be 20nm, and the thickness of the second n-type GaN sublayer 83 may be 40 nm. Other values may be set for specific implementations, and are merely illustrative.

As shown in fig. 1, the light emitting layer 90 may include 6 to 12 periods of InGaN layers 91 and GaN layers 92 alternately stacked. The thickness of the InGaN layer 91 may be 3-4 nm, the thickness of the GaN layer 92 may be 9-20 nm, in this embodiment, the thickness of the InGaN layer 91 is 3.5nm, and the thickness of the GaN layer 92 is 11 nm.

The number of layers of the InGaN layer 91 and the GaN layer 92 shown in fig. 1 is merely illustrative, and is not intended to limit the number of layers.

Alternatively, the p-type layer 100 may include a p-type AlGaN electron blocking layer 101, a p-type GaN layer 102, and a p-type GaN contact layer 103, which are sequentially stacked.

Illustratively, the p-type AlGaN electron blocking layer 101 may have a thickness of 30 anm to 100 nm. The thickness of the p-type GaN layer 102 may be 100nm to 300nm, and the doping concentration of Mg in the p-type GaN layer 102 may be 10¹⁸～10²⁰cm^-3. The thickness of the p-type GaN contact layer 103 may be 5nm to 100 nm.

Fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention, for manufacturing the epitaxial wafer shown in fig. 1, as shown in fig. 2, the manufacturing method includes:

s11: a substrate is provided.

In this embodiment, a patterned sapphire substrate is selected.

S12: epitaxially growing an AlN buffer layer and B on the substrate in sequence_xAl_1-xThe LED comprises an N buffer layer, a three-dimensional nucleating layer, a two-dimensional buffer recovery layer, a u-type GaN layer, an N-type GaN layer, a stress release layer, a light-emitting layer and a p-type layer. Wherein x is more than or equal to 0 and less than or equal to 0.2.

Fig. 3 is a flowchart of another method for manufacturing a light emitting diode according to an embodiment of the present invention, and the following describes the manufacturing method provided in fig. 3 in detail with reference to fig. 4 to 11:

s21: a substrate is provided.

In practice, the substrate can be a sapphire substrate, which is a common substrate, and the technology is mature and the cost is low. The present embodiment selects a patterned sapphire substrate.

In step S21, the sapphire substrate may be pretreated, and specifically, the annealing may be performed in a hydrogen atmosphere at 1000 to 1200 ℃ for 8 minutes, and then the sapphire substrate may be subjected to nitridation treatment.

In other embodiments, a Si substrate and a SiC substrate may be used.

S22: an AlN buffer layer is epitaxially grown on the substrate.

As shown in fig. 4, an AlN buffer layer 20 is grown on the substrate 10.

After step S21 is completed, the substrate may be placed in a tray of SiC material, and the substrate may be placed in a PVD (Physical Vapor Deposition) reaction chamber together with the tray. .

After the substrate is placed in the reaction chamber, the reaction chamber may be evacuated to reduce the pressure in the reaction chamber to 10 deg.f^- ⁷torr. And heating the substrate during vacuum pumping, stabilizing the temperature of the substrate at 350-750 ℃ finally, and baking the substrate for 2-12 minutes.

After the substrate is baked, Ar and N can be introduced into the PVD reaction chamber₂、O₂The flow rate of Ar is 20-80 sccm, N₂The flow rate of (A) can be 50-300 sccm, O₂The flow rate of (C) can be 0to 5 sccm.

Ar and N₂The flow rate ratio of (A) to (B) may be 1: 2 to 1: 10, O₂The flow rate of Ar and N₂1 to 10% of the sum of the flow rates.

The growth pressure of the AlN buffer layer 20 may be 1mtorr to 20mtorr, and the growth temperature of the AlN buffer layer 20 may be 500to 750 ℃.

When the AlN buffer layer 20 is manufactured, after the temperature of the PVD reaction cavity is stabilized at 500-750 ℃ for 10-60 s, a sputtering power supply can be switched on, the time control baffle is switched on, the pre-deposition is carried out for 5-10 s, and after the deposition speed is stabilized, the time control baffle can be switched off, and the deposition of the AlN buffer layer 20 is continued. During the deposition process, the pulse frequency of the sputtering power supply is 200-300 kHZ and is kept unchanged.

The thickness of the AlN buffer layer 20 can be controlled by the sputtering time, wherein the thickness of the AlN buffer layer 20 can be 10-15 nm, the grown AlN buffer layers have different thicknesses, the quality of the finally formed epitaxial layer is also different, if the thickness of the AlN buffer layer is too thin, the surface of the AlN buffer layer is loose and rough, a good template cannot be provided for the growth of a subsequent structure, along with the increase of the thickness of the AlN buffer layer, the surface of the AlN buffer layer gradually becomes compact and flat, the growth of the subsequent structure is facilitated, but if the thickness of the AlN buffer layer is too thick, the surface of the AlN buffer layer is too compact, the growth of the subsequent structure is not facilitated, and the lattice defects in the epitaxial layer cannot be reduced.

After the sputtering of the AlN buffer layer 20 is completed, the substrate on which the AlN buffer layer 20 is grown may be lowered to room temperature, and then the substrate on which the AlN buffer layer 20 is grown may be taken out to prepare for the growth of the subsequent structure.

S23: growing B on the AlN buffer layer_xAl_1-xAnd an N buffer layer.

As shown in FIG. 5, B is grown on the AlN buffer layer_xAl_1-xAn N buffer layer 30.

After step S22 is completed, the substrate 10 on which the AlN buffer layer 20 is grown may be placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber for pretreatment to clean the surface of the substrate 10.

The pre-treatment may include heating and pressure regulation. Illustratively, the temperature of the MOCVD reaction chamber can be heated to 1000 ℃, the pressure can be adjusted to 200-500 torr, and the temperature can be kept for 5-10 minutes.

As shown in FIG. 5, B_xAl_1-xThe N buffer layer 30 may include a plurality of B_xAl_1-xN sublayer 31, one and the same B_xAl_1-xThe component content of B in the N sublayer 31 is constant, and a plurality of B_xAl_1-xThe B component content of the N sublayer 31 increases layer by layer from the AlN buffer layer 20 side toward the three-dimensional nucleation layer 40 side. By mixing B_xAl_1-xThe N buffer layer 30 is provided to include a plurality of B_xAl_1-xThe structural form of the N sublayer 31 can facilitate B_xAl_1-xThe composition content of B of the N buffer layer 30 gradually changes. Exemplarily, B_xAl_1-xThe N buffer layer 30 may include 5B_xAl_1-xN sublayer 31, 5B_xAl_1-xThe value of x in the N sublayer can be 0, 0.05, 0.1, 0.15 and 0.2 respectively.

Alternatively, B_xAl_1-xThe N buffer layer 30 may be grown at a temperature of 1000 to 1100 deg.c and a growth pressure of 150to 500 torr.

Further, a plurality of B_xAl_1-xThe growth temperature of the N sublayer 31 may be raised layer by layer from the AlN buffer layer 20 side toward the three-dimensional nucleation layer 40 side. Exemplarily, B_xAl_1-xThe N buffer layer 30 may include 5B_xAl_1-xN sublayers 31, each B_xAl_1-xThe growth temperature of the N sublayer 31 may be 1020 ℃, 1040 ℃, 1060 ℃, 1080 ℃ and 1100 ℃ in sequence.

Further, a plurality of B_xAl_1-xThe growth pressure of the N sublayer 31 may be raised layer by layer from the AlN buffer layer 20 side toward the three-dimensional nucleation layer 40 side. Exemplarily, B_xAl_1-xThe N buffer layer 30 may include 5B_xAl_1-xN sublayers 31, each B_xAl_1-xThe growth pressure of the N sublayer 31 may be 350torr, 400torr, 450torr, 500torr, 550torr, 600torr in this order.

In growth of B_xAl_1-xNH may be controlled during the N buffer layer 30₃At a flow rate of 3 × 10^-3～10×10^-3mol/min. In the growth of each B_xAl_1-xN sublayer 31, NH₃The flow rate of (a) may be decreased layer by layer. Such as B_xAl_1-xThe N buffer layer 30 may include 5B_xAl_1-xN sublayers 31, in each growth of B_xAl_1-xN sublayer 31, NH₃May be 8 × 10 respectively^-3mol/min、7×10^-3mol/min、6×10^-3mol/min、5×10^-3mol/min、4×10^-3mol/min。

By adjusting the growth temperature, growth pressure and NH layer by layer₃At a flow rate such that each B_xAl_1-x The N sublayer 31 grows better.

S24: in B_xAl_1-xAnd growing a three-dimensional nucleation layer on the N buffer layer.

As shown in FIG. 6, at B_xAl_1-xA three-dimensional nucleation layer 40 is grown on the N buffer layer 30.

The thickness of the three-dimensional nucleation layer 40 may be 400nm to 600nm, and in the present embodiment, B_xAl_1-xA three-dimensional nucleation layer 40 with a thickness of 500nm is grown on the N buffer layer 30.

The three-dimensional nucleation layer 40 may be grown in a high temperature, low pressure environment.

Specifically, the growth temperature of the three-dimensional nucleation layer 40 may be 1000 to 1080 ℃, and the growth pressure may be 250 to 550 torr. The growth of the three-dimensional nucleation layer 40 is facilitated by using a high temperature, low pressure environment. In this embodiment, the three-dimensional nucleation layer 40 is grown at 1050 ℃ and 300 torr. The growth time can be 10-30 minutes.

S25: and growing a two-dimensional buffer recovery layer on the three-dimensional nucleation layer.

As shown in fig. 7, a two-dimensional buffer recovery layer 50 is grown on the three-dimensional nucleation layer 40.

The two-dimensional buffer recovery layer 50 may be a GaN layer. The thickness of the two-dimensional buffer recovery layer 50 may be 500-800 nm, and in this embodiment, the two-dimensional buffer recovery layer 50 with a thickness of 650nm is grown on the three-dimensional nucleation layer 40.

Optionally, the growth temperature of the two-dimensional buffer recovery layer 50 may be 1050 ℃ to 1150 ℃, and the growth pressure is 100to 500torr, in this embodiment, the growth temperature of the two-dimensional buffer recovery layer 50 is 1100 ℃, and the growth pressure is 400 torr. The growth time can be 20-40 minutes.

S26: and growing a u-shaped GaN layer on the two-dimensional buffer recovery layer.

As shown in fig. 8, a u-type GaN layer 60 is grown on the two-dimensional buffer recovery layer 50. The thickness of the u-type GaN layer 60 may be 1-2 μm, and in the present embodiment, the thickness of the u-type GaN layer 60 is 1.5 μm.

The growth temperature of the u-shaped GaN layer 60 may be 1050-1200 deg.C, and the growth pressure may be 100-500 torr. In this example, the growth temperature of the u-type GaN layer 60 was 1100 deg.C, and the growth pressure was 300 torr.

S27: and growing an n-type GaN layer on the u-type GaN layer.

As shown in fig. 9, an n-type GaN layer 70 is grown on the u-type GaN layer 60.

In practice, the thickness of the n-type GaN layer 70 may be 1-3 μm, and in the present embodiment, the thickness of the n-type GaN layer 70 is 2 μm. The doping concentration of Si in the n-type GaN layer 70 may be 10¹⁸～10²⁰cm^-3。

The growth temperature of the n-type GaN layer 70 may be 1050-1200 deg.C, and the growth pressure may be 100-500 torr. In this embodiment, the growth temperature of the n-type GaN layer 70 is 1100 deg.C, and the growth pressure is 300 torr.

It should be noted that other doping, such as Ge, may also be used for the n-type GaN layer 70.

S28: and growing a stress release layer on the n-type GaN layer.

As shown in fig. 10, a stress relief layer 80 is grown on the n-type GaN layer 70.

The stress relieving layer 80 may include a periodic structure 82 in which a first n-type GaN sublayer 81, a multilayer InGaN layer 821 and a multilayer GaN layer 822 are alternately stacked, and a second n-type GaN sublayer 83. In which an InGaN layer 821 is grown directly on the first n-type GaN sublayer 81. (only the 2 InGaN layer 821 and the 2 GaN layer 822 are exemplarily shown in fig. 10). The number of layers of the InGaN layer 821 and the number of layers of the GaN layer 822 can be 2-10, and through the alternate lamination of the InGaN layer 821 and the GaN layer 822, stress in the epitaxial wafer can be gradually reduced, the growth of a subsequent light emitting layer is facilitated, and the crystal quality of the final epitaxial wafer is improved.

The growth temperature of the stress release layer 80 can be 800-900 deg.C, and the growth pressure can be 100-500 torr. In this embodiment, the growth temperature of each layer in the stress release layer 80 may be 850 ℃, and the growth pressure may be 300 torr.

S29: and growing a light emitting layer on the stress release layer.

As shown in fig. 11, a light emitting layer 90 is grown on the stress relieving layer 80.

Specifically, the light emitting layer 90 may include 6 to 12 periods of InGaN layers 91 and GaN layers 92 alternately stacked.

Optionally, the thickness of the InGaN layer 91 may be 3 to 4nm, and the thickness of the GaN layer 92 may be 9 to 20nm, in this embodiment, the thickness of the InGaN layer 91 is 3.5nm, and the thickness of the GaN layer 92 is 11 nm.

In practice, the growth temperature of the InGaN layer 91 may be 750-800 ℃, and the growth pressure may be 400-600 torr. The growth temperature of the GaN layer 92 can be 850-900 ℃, and the growth pressure can be 400-600 torr. In this embodiment, the growth temperature of the InGaN layer 91 is set to 780 ℃, the growth temperature of the GaN layer 92 is set to 880 ℃, and the growth pressures of the InGaN layer 91 and the GaN layer 92 are both 500 torr.

The number of layers of the InGaN layer 91 and the GaN layer 92 shown in fig. 11 is merely illustrative, and is not intended to limit the number of layers.

S30: a p-type layer is grown over the light emitting layer.

Referring to fig. 1, a p-type layer 100 is grown on the light emitting layer 90.

Alternatively, the p-type layer 100 is a composite layer, and specifically, the p-type layer 100 may include a p-type AlGaN electron blocking layer 101, a p-type GaN layer 102, and a p-type GaN contact layer 103, which are sequentially stacked.

The growth temperature of the p-type AlGaN electron blocking layer 101 can be 900-1000 ℃, and the growth pressure can be 100-500 torr.

The growth temperature of the p-type GaN layer 102 may be 850-950 ℃, and the growth pressure may be 100-300 torr. The doping concentration of Mg in the p-type GaN layer 102 may be 10¹⁸～10²⁰cm^-3。

The growth temperature of the p-type GaN contact layer 103 may be 850-1000 deg.C, and the growth pressure may be 100-300 torr.

After the growth of the p-type layer 100 is completed, annealing treatment can be performed in an ammonia atmosphere, wherein the annealing temperature is 650-850 ℃, and the annealing treatment time is 5-15 minutes.

After step S30 is completed, the epitaxial wafer may be subjected to subsequent processing to complete the fabrication of the LED chip.

In particular implementations, embodiments of the invention may employ high purity H₂Or N₂As the carrier gas, TEGa or TMGa, TMAl, TMIn and NH were used, respectively₃As Ga source, Al source, In source and N source, respectively, and SiH can be used respectively₄And Cp₂Mg as n-type and p-type dopants, TeESi (tetraethyl silicon) and Si may also be used₂H₆As the Si source, a metal organic chemical vapor deposition device or other devices can be adopted to complete the growth of the epitaxial wafer.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims

1. The epitaxial wafer of the light-emitting diode is characterized by comprising a substrate, and an AlN buffer layer which are sequentially formed on the substrate_xAl_1-xThe LED structure comprises an N buffer layer, a three-dimensional nucleating layer, a two-dimensional buffer recovery layer, a u-type GaN layer, an N-type GaN layer, a stress release layer, a light-emitting layer and a p-type layer, wherein x is more than 0 and less than or equal to 0.2.

2. Epitaxial wafer according to claim 1, characterized in that B is defined as_xAl_1-xThe composition content of B in the N buffer layer gradually increases from the AlN buffer layer side to the three-dimensional nucleation layer side.

3. Epitaxial wafer according to claim 2, characterized in that B is as defined in claim 2_xAl_1-xThe N buffer layer comprises a plurality of B_xAl_1-xN sublayers, the same as B_xAl_1-xThe component content of B in the N sub-layers is unchanged, and the plurality of B_xAl_1-xThe component content of B of the N sub-layer gradually increases from one side of the AlN buffer layer to one side of the three-dimensional nucleation layer.

4. Epitaxial wafer according to claim 3, characterized in that the plurality of Bs_xAl_1-xThe thickness of the N sublayers is the same.

5. Epitaxial wafer according to any of claims 1 to 4, characterized in that B is_xAl_1-xThe thickness of the N buffer layer is 15-30 nm.

6. A manufacturing method of an epitaxial wafer of a light emitting diode is characterized by comprising the following steps:

providing a substrate;

epitaxially growing an AlN buffer layer and B on the substrate in sequence_xAl_1-xThe LED structure comprises an N buffer layer, a three-dimensional nucleating layer, a two-dimensional buffer recovery layer, a u-type GaN layer, an N-type GaN layer, a stress release layer, a light-emitting layer and a p-type layer, wherein x is more than 0 and less than or equal to 0.2.

7. The method of claim 6, wherein B is_xAl_1-xThe N buffer layer comprises a plurality of B_xAl_1-xN sublayers, the same as B_xAl_1-xThe component content of B in the N sub-layers is unchanged, and the plurality of B_xAl_1-xThe component content of B of the N sub-layer gradually increases from one side of the AlN buffer layer to one side of the three-dimensional nucleation layer.

8. The method of claim 7, wherein the plurality of B' s_xAl_1-xThe growth temperature of the N sub-layer is increased layer by layer from the AlN buffer layer side to the three-dimensional nucleation layer side.

9. The method of claim 7, wherein the plurality of B' s_xAl_1-xThe growth pressure of the N sub-layer is increased layer by layer from the AlN buffer layer side to the three-dimensional nucleation layer side.

10. The method according to any one of claims 6 to 9, wherein B is_xAl_1-xThe growth temperature of the N buffer layer is 1000-1100 ℃, and the growth pressure is 150-500 torr.