CN109659407A - A kind of GaN base light emitting epitaxial wafer and preparation method thereof - Google Patents

A kind of GaN base light emitting epitaxial wafer and preparation method thereof Download PDF

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CN109659407A
CN109659407A CN201811288866.1A CN201811288866A CN109659407A CN 109659407 A CN109659407 A CN 109659407A CN 201811288866 A CN201811288866 A CN 201811288866A CN 109659407 A CN109659407 A CN 109659407A
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layer
gan
pressure
substrate
growth
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CN109659407B (en
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苏晨
王慧
肖扬
吕蒙普
胡加辉
李鹏
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HC Semitek Suzhou Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

The invention discloses a kind of GaN base light emitting epitaxial wafers and preparation method thereof, belong to LED technology field.The described method includes: providing substrate, the substrate is graphical sapphire substrate, and the bottom width of the graphical sapphire substrate is equal to or more than 2.9 microns;Buffer layer over the substrate;GaN nucleating layer is deposited on the buffer layer, the GaN nucleating layer includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, and the high-temperature low-pressure GaN layer is between the buffer layer and the cryogenic high pressure GaN layer;GaN high temperature is sequentially deposited on the GaN nucleating layer fills and leads up layer, layer of undoped gan, N-type layer, multiple quantum well layer and P-type layer.

Description

A kind of GaN base light emitting epitaxial wafer and preparation method thereof
Technical field
The present invention relates to LED technology field, in particular to a kind of GaN base light emitting epitaxial wafer and its system Preparation Method.
Background technique
GaN (gallium nitride) is the Typical Representative of third generation semiconductor material with wide forbidden band, has excellent high heat conductance, resistance to height The special types such as temperature, acid and alkali-resistance, high rigidity are widely used in making blue, green and UV LED.GaN base light-emitting diodes Pipe generally includes epitaxial wafer and the electrode on epitaxial wafer.
The epitaxial wafer of existing a kind of GaN base light emitting comprising substrate and successively grow on substrate slow Rush layer, GaN nucleating layer, fill and lead up layer, undoped GaN layer, N-type layer, multiple quantum well layer (also known as active layer), electronic barrier layer and P-type layer.When a current passes through, the electronics of N-type layer and the hole of P-type layer enter multiple quantum well layer well region and compound, sending Visible light.Wherein, substrate is graphical sapphire substrate (Al2O3).Graphical sapphire substrate growth GaN epitaxial layer (including it is heavy Product other layers on the buffer layer) it can increase epitaxial layer bottom (including GaN nucleating layer and fill and lead up layer) reflection, and figure Bottom width is bigger, is more conducive to device and goes out light.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems: graphical blue precious GaN epitaxial layer is grown on stone lining bottom is principally obtaining the GaN epitaxial layer generated based on sapphire c to face.For graphical blue precious Stone lining bottom, the substrate surface between figure are Sapphire Substrate c to face.When the figure period is constant and the bottom width of figure becomes larger, Sapphire c between figure becomes smaller to the area in face, and which increase the difficulty in c to face growing epitaxial layers.
Summary of the invention
The embodiment of the invention provides a kind of GaN base light emitting epitaxial wafers and preparation method thereof, can be in sapphire c GaN base epitaxial layer is grown in the lesser situation of area ratio in face.The technical solution is as follows:
On the one hand, a kind of preparation method of GaN base light emitting epitaxial wafer is provided, which comprises
There is provided substrate, the substrate be graphical sapphire substrate, the bottom width of the graphical sapphire substrate be equal to or Greater than 2.9 microns;
Buffer layer over the substrate;
GaN nucleating layer is deposited on the buffer layer, the GaN nucleating layer includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, the high-temperature low-pressure GaN layer is between the buffer layer and the cryogenic high pressure GaN layer;
Sequentially on the GaN nucleating layer deposit GaN high temperature fill and lead up layer, layer of undoped gan, N-type layer, multiple quantum well layer and P-type layer.
It is optionally, described that GaN nucleating layer is deposited on the buffer layer, comprising:
Driving is deposited with the substrate rotation of the buffer layer, and deposits the high-temperature low-pressure on the buffer layer of rotation GaN layer and the cryogenic high pressure GaN layer, the growth temperature of the high-temperature low-pressure GaN layer is 1030~1060 DEG C, growth pressure is 100~300torr, the growth temperature of the cryogenic high pressure GaN layer is 1000~1030 DEG C, growth pressure be 400~ 600torr, the thickness of the high-temperature low-pressure GaN layer are less than the thickness of the cryogenic high pressure GaN layer, the thickness of the GaN nucleating layer Degree is 1~2 micron.
Optionally, when depositing the high-temperature low-pressure GaN layer, the revolving speed of the substrate is 1000~1200 revs/min,
When depositing the cryogenic high pressure GaN layer, the revolving speed of the substrate is 400~600 revs/min.
Optionally, the buffer layer includes AlN layers and BGaN layers, and described AlN layers is located at the substrate and BGaN layers described Between, the buffer layer over the substrate, comprising:
Deposit over the substrate it is AlN layers described, described AlN layers with a thickness of 5~20nm, described AlN layers of growth pressure Power is 100~200torr, and AlN layers of the growth temperature is 500~600 DEG C;
Deposited on AlN layers described it is BGaN layers described, described BGaN layers with a thickness of 10~30nm, BGaN layers of the life Long pressure is 100~200torr, and BGaN layers of the growth temperature is 500~600 DEG C.
Optionally, it is described deposited on AlN layers described it is BGaN layers described, comprising:
The growth room for AlN layers of the substrate will be deposited with being placed into metallo-organic compound chemical gaseous phase deposition equipment It is interior;
The first reaction gas is continually fed into the growth room and is passed through the second reaction gas to the growth interventricular septum Body, BGaN layers described to deposit on AlN layers described, first reaction gas includes TEB and NH3, second reaction gas Body includes TMGa or TEGa.
Optionally, the GaN high temperature fill and lead up layer with a thickness of 1~2 micron, the GaN high temperature fills and leads up the growth pressure of layer For 100~300torr, the growth temperature that the GaN high temperature fills and leads up layer is 1100~1150 DEG C.
On the other hand, a kind of GaN base light emitting epitaxial wafer is provided, the epitaxial wafer includes: graphic sapphire Substrate, the buffer layer sequentially deposited on the graphical sapphire substrate, GaN nucleating layer, GaN high temperature fill and lead up layer, undoped The bottom width of GaN layer, N-type layer, multiple quantum well layer and P-type layer, the graphical sapphire substrate is equal to or more than 2.9 microns, institute Stating GaN nucleating layer includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, the high-temperature low-pressure GaN layer be located at the buffer layer with Between the cryogenic high pressure GaN layer.
Optionally, the thickness of the high-temperature low-pressure GaN layer is less than the thickness of the cryogenic high pressure GaN layer, the GaN nucleation Layer with a thickness of 1~2 micron.
Optionally, the buffer layer includes AlN layers and BGaN layers, and described AlN layers is located at the substrate and BGaN layers described Between.
Optionally, described AlN layers with a thickness of 5~20nm, described BGaN layers with a thickness of 10~30nm.
Technical solution provided in an embodiment of the present invention has the benefit that by GaN nucleating layer include high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, high-temperature low-pressure GaN layer is between buffer layer and cryogenic high pressure GaN layer, the life of GaN nucleating layer Length mainly forms nucleus on the buffer layer, and constantly grows up to form island, in the initial growth stages of GaN nucleating layer, passes through The growth pattern of high-temperature low-pressure, be beneficial to sapphire c on the figure on graphical sapphire substrate and between figure to Form the initial island GaN on face, and the three-dimensional on the initial island GaN formed mostly with sapphire c on face the three of the island GaN It is identical to tie up direction;And in the back segment growth phase of GaN nucleating layer, by the growth pattern of cryogenic high pressure, be conducive to sapphire c to The three dimensional growth on the island GaN formed on face, in this way, by the way of two-step growth GaN nucleating layer, it can be in the figure of big bottom width The area in change Sapphire Substrate and sapphire c to face is preferably nucleated when smaller, in the base for guaranteeing that crystal quality is not deteriorated On plinth, increase the external quantum efficiency of device.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention;
Fig. 2 is a kind of flow chart of the preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention;
Fig. 3 is a kind of structural schematic diagram of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
Fig. 1 shows a kind of preparation method of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure 1, this method process includes the following steps.
Step 101 provides substrate.
Wherein, substrate is graphical sapphire substrate, and the bottom width of graphical sapphire substrate is equal to or more than 2.9 microns.
Step 102, on substrate buffer layer.
Illustratively, buffer layer includes AlN layers;Alternatively, buffer layer includes AlN layers and BGaN layers, AlN layers be located at substrate with Between BGaN layers.
When buffer layer includes AlN layers and BGaN layers, since the radius of B atom is respectively than the radius of Al atom and Ga atom Small, B and Ga is integrated in BGaN material, and the lattice constant of BGaN material is close to Sapphire Substrate, AlN material and GaN material The lattice constant of material, then, transition is carried out from Sapphire Substrate, AlN material to GaN material by BGaN material, is capable of providing Reversed compression, between Sapphire Substrate, AlN material and GaN material lattice mismatch and big bottom width substrate institute Bring tensile stress is offset, to reduce or eliminate the inclined bulgy phenomenon of multiple quantum well layer, improves the photoelectric conversion of device Efficiency;Simultaneously on the basis of guaranteeing that crystal quality is not deteriorated, biggish bottom width can increase the external quantum efficiency of device.
Step 103 deposits GaN nucleating layer on the buffer layer.
Wherein, GaN nucleating layer includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, and high-temperature low-pressure GaN layer is located at buffering Between layer and cryogenic high pressure GaN layer.
Step 104, sequentially deposition GaN high temperature fills and leads up layer, layer of undoped gan, N-type layer, multiple quantum wells on GaN nucleating layer Layer and P-type layer.
The embodiment of the present invention includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, high-temperature low-pressure GaN by GaN nucleating layer Layer is between buffer layer and cryogenic high pressure GaN layer, and the growth of GaN nucleating layer mainly forms nucleus on the buffer layer, not It is disconnected to grow up to form island, it is beneficial to by the growth pattern of high-temperature low-pressure in figure in the initial growth stages of GaN nucleating layer Change the sapphire c on the figure in Sapphire Substrate and between figure and forms the initial island GaN, and initial GaN on face The three-dimensional on island is mostly identical as the three-dimensional on the island GaN that sapphire c is formed on face;And in the back segment of GaN nucleating layer Growth phase is conducive to the three dimensional growth on the island GaN that sapphire c is formed on face by the growth pattern of cryogenic high pressure, this Sample, by the way of two-step growth GaN nucleating layer, can big bottom width graphical sapphire substrate and sapphire c to face It is preferably nucleated when area is smaller, on the basis of guaranteeing that crystal quality is not deteriorated, increases the external quantum efficiency of device.
Fig. 2 shows a kind of preparation methods of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention.Referring to figure 2, this method process includes the following steps.
Step 201 provides substrate.
Illustratively, substrate can be graphical sapphire substrate (Patterned Sapphire Substrate, abbreviation PSS).GaN base light emitting epitaxial wafer is grown using PSS, the outgoing brightness of light emitting diode can be enhanced, while reversed Leakage current reduces, and the service life of light emitting diode is also extended.
Illustratively, the bottom width of PSS is equal to or more than 2.9 microns.Bottom width is the diameter of figure on PSS.Bottom width be equal to or PSS greater than 2.9 microns is also referred to as big structure cell bottom width substrate.
Illustratively, the bottom width of PSS is 2.9 microns, and the figure period of PSS can be 3.0 microns or 3.05 microns, this When, the face the c length between adjacent pattern is 0.1 or 0.15 micron.The face c is the face that GaN base epitaxial layer is grown on PSS.
Illustratively, the pattern height of PSS is 1.7~2.0 microns.
Step 202, depositing Al N layers on substrate.
Illustratively, using physical vapour deposition (PVD) (Physical Vapor Deposition, abbreviation PVD) method, such as Magnetron sputtering method, depositing Al N layers on substrate.AlN layers with a thickness of 5~20nm, AlN layers of growth pressure is 100~ 200torr, AlN layers of growth temperature is 500~600 DEG C.
It illustratively, can be in metallo-organic compound chemical gaseous phase deposition (Metal-organic Chemical Vapor Deposition, abbreviation MOCVD) method deposit BGaN layer, GaN nucleating layer, GaN high temperature fill and lead up layer, undoped GaN Layer, N-type layer, multiple quantum well layer and P-type layer.The preparation method can be realized using MOCVD device.In the preparation method, with High-purity H2(hydrogen) and N2(nitrogen) is used as carrier gas, using TMGa (trimethyl is sowed) or TEGa (triethyl group is sowed) as the source Ga, Using TMAl (trimethyl aluminium) as the source Al, using TEB (boron triethyl) as the source B, using TMIn (trimethyl indium) as the source In, with NH3(ammonia) is used as the source N, uses SiH4(silane) is used as N type dopant, uses CP2Mg (two luxuriant magnesium) is used as P-type dopant.
Step 203, in H2The pre-heat treatment is carried out to the substrate for being deposited with AlN layers in atmosphere.
Specifically, the substrate for being deposited with AlN layers is put into MOCVD device, makes substrate in H2In atmosphere heat treatment 10~ 15 minutes, heat treatment temperature can be 1000~1040 DEG C.
Step 204, driving be deposited with AlN layer substrate rotation, sequentially on substrate deposition BGaN layers, GaN nucleating layer, GaN high temperature fills and leads up layer, layer of undoped gan, N-type layer, multiple quantum well layer and P-type layer.
Specifically, on the pallet for the growth room that the substrate for being deposited with AlN layers is placed on MOCVD device.It is set by MOCVD During standby growth GaN base epitaxial layer, driving pallet rotation, to grow GaN base epitaxial layer on the substrate of rotation.Step 204 include the following steps 2041- step 2049.
Step 2041 deposits BGaN layers on the AlN layer of rotation.
Illustratively, step 2041 may include: to growth room to be continually fed into the first reaction gas and between growth room Every being passed through the second reaction gas, to deposit BGaN layers on AlN layer.Wherein, the first reaction gas includes TEB and NH3, second is anti- Answering gas includes TMGa or TEGa.
Illustratively, it includes: the generation pulse signal that is first powered that interval, which is passed through the implementation of the second reaction gas, then in arteries and veins The conduction time for rushing the period is passed through the second reaction gas to growth room.Wherein, the duty ratio of pulse signal can be 10%- 60%.
Illustratively, BGaN layers with a thickness of 10~30nm, BGaN layers of growth pressure is 100~200torr, BGaN layers Growth temperature be 500~600 DEG C.
BGaN layers of growth temperature is lower.When growth temperature is lower, nuclear island is advantageously formed into.But B is former when low temperature The surface mobility of son is also relatively low, if being constantly passed through the source Ga and the source B to growth room, the low surface mobility of B be will lead to It is overstocked at nuclear island, cause the interface of filling and leading up on substrate between figure and figure to generate more defect.In order to solve this problem, it adopts It is passed through the mode of TMGa or TEGa with interval, increases B atomic quantity, improves the surface mobility of B, this way it is possible to avoid by It is overstocked at nuclear island caused by the low surface mobility of B, so that causing to fill and lead up interface generates more defect, improve GaN epitaxy The crystal quality of layer.In addition, in such a way that interval is passed through TMGa or TEGa, it is possible to reduce between the source Ga being passed through and the source Al Pre-reaction is generated, pre-reaction is avoided to influence the crystal quality of GaN epitaxial layer.
Step 2042, the depositing high temperature low pressure GaN layer on the BGaN layer of rotation.
Illustratively, the growth temperature of high-temperature low-pressure GaN layer be 1030~1060 DEG C, growth pressure be 100~ 300torr。
Illustratively, in depositing high temperature low pressure GaN layer, the revolving speed of substrate is 1000~1200 revs/min.
Step 2043, the deposit low temperature high voltage gan layer in the high-temperature low-pressure GaN layer of rotation.
Illustratively, the growth temperature of cryogenic high pressure GaN layer be 1000~1030 DEG C, growth pressure be 400~ 600torr。
Illustratively, in deposit low temperature high voltage gan layer, the revolving speed of substrate is 400~600 revs/min.
Illustratively, the flow of growth high-temperature low-pressure GaN layer is passed through TMGa or TEGa are less than growing low temperature high pressure The flow of TMGa or TEGa that GaN layer is passed through.In this way, cryogenic high pressure GaN layer is under the growth conditions of high pressure and high flow capacity, it is low The growth rate of warm high voltage gan layer is much larger than the growth rate of high-temperature low-pressure GaN layer, this is conducive to the formation on the island GaN.
Illustratively, the thickness of high-temperature low-pressure GaN layer be less than cryogenic high pressure GaN layer thickness, GaN nucleating layer with a thickness of 1~2.0 micron.
Compared to BGaN layers, the growth temperature of GaN nucleating layer is higher.Higher temperature will melt a part of low temperature BGaN Layer, since BGaN layers of growth temperatures are lower, crystal quality is bad, melts BGaN layers a part of, and gives birth under the high temperature conditions Long GaN nucleating layer, can be improved crystal quality.
In addition, the revolving speed of substrate is bigger when passing through depositing high temperature low pressure GaN layer, and in deposit low temperature high voltage gan layer When, the revolving speed of substrate is smaller, this is conducive to preferably be nucleated.
Step 2044, deposition GaN high temperature fills and leads up layer in the cryogenic high pressure GaN layer of rotation.
Illustratively, GaN high temperature fill and lead up layer with a thickness of 1~2 micron, GaN high temperature fill and lead up the growth pressure of layer be 100~ The growth temperature that 300torr, GaN high temperature fill and lead up layer is 1100~1150 DEG C.
Illustratively, GaN nucleating layer and GaN high temperature fill and lead up the sum of thickness of layer no more than 2 microns.In this way, enough by PSS Figure between gap cover with.
Compared to GaN nucleating layer, GaN high temperature fill and lead up the temperature of layer more it is high once, this is conducive to fill and lead up between figure and figure Gap, increase the area in the face c, and obtain better crystal quality.
Step 2045 is filled and led up in GaN high temperature and deposits layer of undoped gan on layer.
Illustratively, the growth temperature of layer of undoped gan can be 1000 DEG C~1100 DEG C, and growth pressure can be 100Torr is between 500Torr.The growth thickness of layer of undoped gan can be 1.0 to 5.0 microns.
Step 2046, the deposited n-type layer in layer of undoped gan.
Illustratively, N-type layer is n-type doping GaN layer, and the thickness of n-type doping GaN layer is between 1~5 micron, n-type doping The growth temperature of GaN layer can be 1000 DEG C~1200 DEG C, and growth pressure is in 100Torr between 500Torr.N-type doping GaN Layer is that Si is adulterated, and Si doping concentration is 1018cm-3~1019cm-3Between.
Step 2047 deposits multiple quantum well layer in N-type layer.
Illustratively, multiple quantum well layer can be made of the Quantum Well barrier layer in 3 to 15 periods.Quantum Well barrier layer includes InxGa1-xN (0 < x < 1) Quantum Well and GaN quantum are built, and the thickness of Quantum Well is in 3nm or so, and the range of growth temperature is at 720 DEG C Between~829 DEG C, growth pressure range is between 100Torr and 500Torr.For the thickness that quantum is built in 9nm between 20nm, growth is warm Degree is between 850 DEG C~959 DEG C, and growth pressure is between 100Torr to 500Torr.
Step 2048 deposits P-type layer on multiple quantum well layer.
Illustratively, P-type layer is p-type doped gan layer.The growth temperature of p-type doped gan layer 850 DEG C~1080 DEG C it Between, growth pressure section is 200Torr~300Torr.The thickness of p-type doped gan layer is in 100nm between 800nm.
Step 2049 deposits p-type composite contact layer in P-type layer.
Illustratively, the growth temperature section of p-type composite contact layer is 850 DEG C~1050 DEG C, and growth pressure section is 100Torr~300Torr.P-type composite contact layer with a thickness of 5nm between 300nm.
After depositing p-type composite contact layer, the growth room temperature of MOCVD can be reduced, in nitrogen atmosphere externally Prolong piece to be made annealing treatment, annealing temperature can be 650 DEG C~850 DEG C, and annealing time can be 5 to 15 minutes, then be down to Room temperature terminates the growth of epitaxial wafer.
The embodiment of the present invention includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, high-temperature low-pressure GaN by GaN nucleating layer Layer is between buffer layer and cryogenic high pressure GaN layer, and the growth of GaN nucleating layer mainly forms nucleus on the buffer layer, not It is disconnected to grow up to form island, it is beneficial to by the growth pattern of high-temperature low-pressure in figure in the initial growth stages of GaN nucleating layer Change the sapphire c on the figure in Sapphire Substrate and between figure and forms the initial island GaN, and initial GaN on face The three-dimensional on island is mostly identical as the three-dimensional on the island GaN that sapphire c is formed on face;And in the back segment of GaN nucleating layer Growth phase is conducive to the three dimensional growth on the island GaN that sapphire c is formed on face by the growth pattern of cryogenic high pressure, this Sample, by the way of two-step growth GaN nucleating layer, can big bottom width graphical sapphire substrate and sapphire c to face It is preferably nucleated when area is smaller, on the basis of guaranteeing that crystal quality is not deteriorated, increases the external quantum efficiency of device.
Fig. 3 shows a kind of GaN base light emitting epitaxial wafer provided in an embodiment of the present invention, referring to Fig. 3, the epitaxial wafer It include: that substrate 31, the buffer layer sequentially deposited on substrate 31 32, GaN nucleating layer 33, GaN high temperature fill and lead up layer 34, undoped GaN layer 35, N-type layer 36, multiple quantum well layer 37 and P-type layer 38.Substrate 31 is PSS, and it is micro- that the bottom width of PSS is equal to or more than 2.9 Rice.GaN nucleating layer 33 includes high-temperature low-pressure GaN layer 331 and cryogenic high pressure GaN layer 332, and high-temperature low-pressure GaN layer 331 is located at buffering Between layer 32 and cryogenic high pressure GaN layer 332.
Illustratively, the thickness of high-temperature low-pressure GaN layer 331 is less than the thickness of cryogenic high pressure GaN layer 332, GaN nucleating layer 33 With a thickness of 1~2 micron.
Illustratively, buffer layer 32 includes AlN layer 321 and BGaN layer 322, and AlN layer 321 is located at substrate 31 and BGaN layers Between 322.
Illustratively, AlN layers be low temperature AI N layers, AlN layers with a thickness of 5~20nm;BGaN layers are low temperature BGaN layers, BGaN layers with a thickness of 10~30nm.
Illustratively, GaN high temperature fill and lead up layer with a thickness of 1~2 micron.
Illustratively, the pattern height of PSS is 1.7~2.0 microns, GaN nucleating layer and GaN high temperature fill and lead up layer thickness it Be no more than 2 microns.In this way, the gap between the figure of PSS is covered with enough.
The embodiment of the present invention includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, high-temperature low-pressure GaN by GaN nucleating layer Layer is between buffer layer and cryogenic high pressure GaN layer, and the growth of GaN nucleating layer mainly forms nucleus on the buffer layer, not It is disconnected to grow up to form island, it is beneficial to by the growth pattern of high-temperature low-pressure in figure in the initial growth stages of GaN nucleating layer Change the sapphire c on the figure in Sapphire Substrate and between figure and forms the initial island GaN, and initial GaN on face The three-dimensional on island is mostly identical as the three-dimensional on the island GaN that sapphire c is formed on face;And in the back segment of GaN nucleating layer Growth phase is conducive to the three dimensional growth on the island GaN that sapphire c is formed on face by the growth pattern of cryogenic high pressure, this Sample, by the way of two-step growth GaN nucleating layer, can big bottom width graphical sapphire substrate and sapphire c to face It is preferably nucleated when area is smaller, on the basis of guaranteeing that crystal quality is not deteriorated, increases the external quantum efficiency of device.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of preparation method of GaN base light emitting epitaxial wafer, which is characterized in that the described method includes:
Substrate is provided, the substrate is graphical sapphire substrate, and the bottom width of the graphical sapphire substrate is equal to or more than 2.9 micron;
Buffer layer over the substrate;
GaN nucleating layer is deposited on the buffer layer, the GaN nucleating layer includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN Layer, the high-temperature low-pressure GaN layer is between the buffer layer and the cryogenic high pressure GaN layer;
GaN high temperature is sequentially deposited on the GaN nucleating layer fills and leads up layer, layer of undoped gan, N-type layer, multiple quantum well layer and p-type Layer.
2. the method according to claim 1, wherein described deposit GaN nucleating layer, packet on the buffer layer It includes:
Driving is deposited with the substrate rotation of the buffer layer, and the high-temperature low-pressure GaN is deposited on the buffer layer of rotation Layer and the cryogenic high pressure GaN layer, the growth temperature of the high-temperature low-pressure GaN layer is 1030~1060 DEG C, growth pressure 100 ~300torr, the growth temperature of the cryogenic high pressure GaN layer is 1000~1030 DEG C, growth pressure is 400~600torr, institute State high-temperature low-pressure GaN layer thickness be less than the cryogenic high pressure GaN layer thickness, the GaN nucleating layer it is micro- with a thickness of 1~2 Rice.
3. according to the method described in claim 2, it is characterized in that,
When depositing the high-temperature low-pressure GaN layer, the revolving speed of the substrate is 1000~1200 revs/min,
When depositing the cryogenic high pressure GaN layer, the revolving speed of the substrate is 400~600 revs/min.
4. the method according to claim 1, wherein the buffer layer includes AlN layers and BGaN layers, the AlN Layer be located at the substrate and it is BGaN layers described between, the buffer layer over the substrate, comprising:
Deposit over the substrate it is AlN layers described, described AlN layers with a thickness of 5~20nm, AlN layers of the growth pressure is 100~200torr, AlN layers of the growth temperature are 500~600 DEG C;
Deposited on AlN layers described it is BGaN layers described, described BGaN layers with a thickness of 10~30nm, described BGaN layers of growth pressure Power is 100~200torr, and BGaN layers of the growth temperature is 500~600 DEG C.
5. according to the method described in claim 4, it is characterized in that, described deposit BGaN layers described, packet on AlN layers described It includes:
AlN layers of the substrate will be deposited with to be placed into the growth room of metallo-organic compound chemical gaseous phase deposition equipment;
The first reaction gas is continually fed into the growth room and is passed through the second reaction gas to the growth interventricular septum, with Deposited on AlN layers described BGaN layers described, first reaction gas includes TEB and NH3, second reaction gas includes TMGa or TEGa.
6. the method according to claim 1, wherein the GaN high temperature fill and lead up layer with a thickness of 1~2 micron, institute State GaN high temperature fill and lead up layer growth pressure be 100~300torr, the GaN high temperature fill and lead up layer growth temperature be 1100~ 1150℃。
7. a kind of GaN base light emitting epitaxial wafer, which is characterized in that the epitaxial wafer includes: graphical sapphire substrate, suitable The secondary buffer layer deposited on the graphical sapphire substrate, GaN nucleating layer, GaN high temperature fill and lead up layer, layer of undoped gan, N Type layer, multiple quantum well layer and P-type layer, the bottom width of the graphical sapphire substrate are equal to or more than 2.9 microns, the GaN at Stratum nucleare includes high-temperature low-pressure GaN layer and cryogenic high pressure GaN layer, the high-temperature low-pressure GaN layer be located at the buffer layer with it is described low Between warm high voltage gan layer.
8. epitaxial wafer according to claim 7, which is characterized in that the thickness of the high-temperature low-pressure GaN layer is less than described low The thickness of warm high voltage gan layer, the GaN nucleating layer with a thickness of 1~2 micron.
9. epitaxial wafer according to claim 7, which is characterized in that the buffer layer includes AlN layers and BGaN layers, described AlN layers be located at the substrate and it is BGaN layers described between.
10. epitaxial wafer according to claim 9, which is characterized in that described AlN layers with a thickness of 5~20nm, the BGaN Layer with a thickness of 10~30nm.
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