CN116565097A - Light-emitting diode epitaxial wafer and preparation method thereof - Google Patents
Light-emitting diode epitaxial wafer and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof, wherein the light-emitting diode epitaxial wafer comprises a substrate, and a composite insertion layer, an undoped GaN layer, an n-type GaN layer, a multiple quantum well layer, an electron blocking layer and a p-type GaN layer which are sequentially laminated on the substrate; the composite insert layer comprises SiO 2 Insertion layer, in x Si 1‑x N insertion layer, inN insertion layer, al y In 1‑y An N insertion layer; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9. The light-emitting diode epitaxial wafer provided by the invention can effectively reduce dislocation density of an epitaxial layer, inhibit extension of threading dislocation, improve GaN crystal quality, improve radiation recombination efficiency and improve luminous efficiency of a light-emitting diode.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a light-emitting diode epitaxial wafer and a preparation method thereof.
Background
Light-emitting diodes (LEDs) have the characteristics of high efficiency, energy saving, environmental protection, long service life and the like, and have been widely used in various fields such as traffic indication, architectural decoration, display illumination and the like. Currently, commercial LEDs are mostly based on epitaxially grown group III nitride material, gaN, on a sapphire substrate. However, sapphire has low thermal conductivity and large-size substrates are difficult to prepare, and the development of LEDs towards high performance, high power and low cost is limited.
In order to prevent the reaction of 'back-melting etching' between GaN and Si and solve the problems of defects and cracks caused by lattice mismatch and thermal expansion coefficient mismatch, researchers propose to grow a low-temperature GaN buffer layer between a Si substrate and a GaN epitaxial layer to transition the lattice and thermal expansion effects, so that the density of the defects and cracks is reduced and the quality of a GaN film is improved.
However, since the lattice mismatch and thermal mismatch between Si and GaN are as high as 16.9% and 54%, respectively, a large number of defects and cracks are easily formed in GaN; and the Si substrate reacts with active N to generate SiN in the epitaxial growth process x And the quality of epitaxial materials and the device performance of the GaN-based LED are seriously reduced by the interface layer.
Disclosure of Invention
In order to solve the technical problems, the invention provides a light-emitting diode epitaxial wafer and a preparation method thereof.
The invention adopts the following technical scheme: a light-emitting diode epitaxial wafer comprises a substrate, and a composite insertion layer, an undoped GaN layer, an n-type GaN layer, a multiple quantum well layer, an electron blocking layer and a p-type GaN layer which are sequentially laminated on the substrate;
the composite insert layer comprises SiO 2 Insertion layer, in x Si 1-x N insertion layer, inN insertion layer, al y In 1-y An N insertion layer; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9.
The LED epitaxial wafer of the embodiment of the invention is prepared by depositing SiO 2 The insert layer can prevent back melting etching between Ga and Si, inhibit tensile stress, and obtain a GaN film with a flat surface and no cracks, which lays a foundation for realizing a basic LED device structure; in (In) x Si 1-x The N insertion layer and the InN insertion layer can effectively inhibit the extension of threading dislocation, avoid the deterioration of GaN film crystal quality and the formation of cracks, but In x Si 1-x Too high an In composition of the N insertion layer may result In x Si 1-x The crystal quality of the N insertion layer is reduced, so that the moderate In component value can lead In to x Si 1-x The crystal quality of the N insertion layer is better; al (Al) y In 1-y The lattice constant of the N insertion layer is close to that of GaN by adjusting the proportion of Al and In, so that the lattice mismatch with the GaN layer is reduced, and the crystal quality of the subsequently deposited GaN is improved; in summary, the invention can effectively reduce dislocation density of epitaxial layer, inhibit extension of threading dislocation, improve GaN crystal quality, improve radiation recombination efficiency, and improve luminous efficiency of light emitting diode.
Further, the thickness of the composite insertion layer is 10 nm-500 nm, and the SiO is formed by 2 An insertion layer, the In x Si 1-x N insertion layer, inN insertion layer and Al y In 1-y The thickness ratio of the N insertion layers is 1:1:1:1-1:10:5:10.
Further, the thickness of the undoped GaN layer is 1 um-5 um.
Further, the Si doping concentration of the n-type GaN layer is 1E+19atoms/cm 3 ～5E+19atoms/cm 3 。
Further, the electron blocking layer is an AlInGaN layer, and the thickness of the electron blocking layer is 10 nm-40 nm; the Al component of the electron blocking layer gradually changes from 0.005 to 0.1 along the epitaxial growth direction, and the In component concentration of the electron blocking layer is 0.01-0.2.
Further, the Mg doping concentration of the p-type GaN layer is 1E+19atoms/cm 3 ～1E+21atoms/cm 3 。
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
providing a substrate;
nitriding the substrate at a high temperature;
depositing a composite interposer on the substrate, the composite interposer comprising SiO 2 Insertion layer, in x Si 1-x N insertion layer, inN insertion layer, al y In 1-y An N insertion layer; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9;
depositing an undoped GaN layer on the composite interposer;
depositing an n-type GaN layer on the undoped GaN layer;
depositing a multi-quantum well layer on the n-type GaN layer;
depositing an electron blocking layer on the multiple quantum well layer;
and depositing a p-type GaN layer on the electron blocking layer.
The preparation method of the LED epitaxial wafer of the embodiment of the invention comprises the steps of depositing SiO 2 The insert layer can prevent back melting etching between Ga and Si, inhibit tensile stress, and obtain a GaN film with a flat surface and no cracks, which lays a foundation for realizing a basic LED device structure; in (In) x Si 1-x The N insertion layer and the InN insertion layer can effectively inhibit the extension of threading dislocation, avoid the deterioration of GaN film crystal quality and the formation of cracks, but In x Si 1-x Too high an In composition of the N insertion layer may result In x Si 1-x The crystal quality of the N insertion layer is reduced, so that the moderate In component value can lead In to x Si 1-x The crystal quality of the N insertion layer is better; al (Al) y In 1-y The lattice constant of the N insertion layer is close to that of GaN by adjusting the proportion of Al and In, so that the lattice mismatch with the GaN layer is reduced, and the crystal quality of the subsequently deposited GaN is improved; in summary, the invention can effectively reduce dislocation density of epitaxial layer, inhibit extension of threading dislocation, improve GaN crystal quality, improve radiation recombination efficiency, and improve luminous efficiency of light emitting diode.
Further, the growth atmosphere of the composite insert layer is N 2 With NH 3 And N 2 With NH 3 The mixing volume ratio of (2) is 1:1-1:10.
Further, the deposition temperature of the composite insert layer is 500-1000 ℃.
Further, the deposition pressure of the composite insert layer is 50-500 torr.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a light emitting diode epitaxial wafer according to a first embodiment of the present invention;
FIG. 2 is an enlarged schematic view of portion A of FIG. 1;
fig. 3 is a flowchart of a method for manufacturing a light emitting diode epitaxial wafer according to a first embodiment of the present invention.
Reference numerals illustrate:
100. a substrate; 200. a composite insert layer; 210. SiO (SiO) 2 An interposer layer; 220. in (In) x Si 1-x An N insertion layer; 230. an InN insertion layer; 240. al (Al) y In 1-y An N insertion layer; 300. an undoped GaN layer; 400. an n-type GaN layer; 500. a multiple quantum well layer; 600. an electron blocking layer; 700. a p-type GaN layer.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the invention and should not be construed as limiting the invention.
In the description of the embodiments of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present invention and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
In the embodiments of the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured" and the like are to be construed broadly and include, for example, either permanently connected, removably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention will be understood by those of ordinary skill in the art according to specific circumstances.
Example 1
Referring to fig. 1 to 3, a light emitting diode epitaxial wafer according to a first embodiment of the present invention includes a substrate 100, and a composite insertion layer 200, an undoped GaN layer 300, an n-type GaN layer 400, a multiple quantum well layer 500, an electron blocking layer 600, and a p-type GaN layer 700 sequentially stacked on the substrate 100;
the composite interposer 200 comprises SiO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, al y In 1-y N insertion layer 240; wherein, the value range of x is 0.01 to 0.5, and the value range of y is 0.05 to the whole range0.9。
The LED epitaxial wafer of the embodiment of the invention is prepared by depositing SiO 2 The insert layer 210 can prevent back melting etching between Ga and Si and inhibit tensile stress, so that a GaN film with a flat surface and no cracks is obtained, which lays a foundation for realizing a basic LED device structure; in (In) x Si 1-x The N insertion layer 220 and the InN insertion layer 230 can effectively suppress the extension of threading dislocation, prevent the deterioration of GaN thin film crystal quality and the formation of cracks, but In x Si 1-x Too high an In composition of N insertion layer 220 may result In x Si 1-x The crystal quality of the N insertion layer 220 is degraded, so that the In component takes on moderate values to enable In x Si 1-x The crystal quality of the N insertion layer 220 is better; al (Al) y In 1-y The lattice constant of the N insertion layer 240 is close to that of GaN by adjusting the proportion of Al and In, so that the lattice mismatch with the GaN layer is reduced, and the crystal quality of the subsequently deposited GaN is improved; in summary, the invention can effectively reduce dislocation density of epitaxial layer, inhibit extension of threading dislocation, improve GaN crystal quality, improve radiation recombination efficiency, and improve luminous efficiency of light emitting diode.
The thickness of the composite insert layer 200 is 10 nm-500 nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:1:1:1-1:10:5:10; the proper thickness of the composite insert layer 200 can not only avoid the 'back melting etching' between Ga and Si, but also inhibit threading dislocation, so that the crystal quality is improved, and if the thickness is too thick, the stress between the composite insert layers 200 is increased due to lattice mismatch, and the crystal quality is reduced; in this embodiment, the thickness of the composite insert layer 200 is 100nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:4:2:4, in x Si 1-x The value of x in the N insertion layer 220 is 0.25, al y In 1-y Y in the N insertion layer 240 takes a value of 0.5.
The thickness of the undoped GaN layer 300 is 1um to 5um; with the increase of the GaN thickness, the compressive stress can be released through stacking faults, the line defects are reduced, the crystal quality is improved, the reverse leakage current is reduced, but the increase of the thickness of the undoped GaN layer 300 consumes more Ga source materials, and the epitaxial cost of the LED is greatly increased, so that the thickness of the undoped GaN layer 300 is 1 um-5 um, the production cost is saved, and the GaN material has higher crystal quality; in this embodiment, the thickness of the undoped GaN layer 300 is 3um.
The Si doping concentration of the n-type GaN layer 400 is 1E+19atoms/cm 3 ～5E+19atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Firstly, the n-type GaN layer 400 provides sufficient electrons for LED luminescence, secondly, the resistivity of the n-type GaN layer 400 is higher than that of a transparent electrode on p-GaN, so that the resistivity of the n-type GaN layer 400 can be effectively reduced due to sufficient Si doping, and finally, the luminous efficiency of the stress light-emitting diode can be effectively released due to sufficient thickness of the n-type GaN layer 400; in this embodiment, the Si doping concentration of the n-type GaN layer 400 is 2.5E+19atoms/cm 3 The growth thickness was 3um.
In this embodiment, the multiple quantum well layer 500 is an InGaN quantum well layer and an AlGaN quantum barrier layer alternately stacked, the stacking cycle number is 6-12, wherein the InGaN quantum well layer thickness is 2 nm-5 nm, the AlGaN quantum barrier layer thickness is 5 nm-15 nm, and the al composition is 0.01-0.1.
Specifically, the multiple quantum well layer 500 is an InGaN quantum well layer and an AlGaN quantum barrier layer stacked alternately, the stacking cycle number is 10, wherein the thickness of the InGaN quantum well layer is 3.5nm, the in component is 0.22, the thickness of the AlGaN quantum barrier layer is 9.8nm, the al component is 0.05, the multiple quantum well is an electron and hole recombination region, and the overlapping degree of the electron and hole wave functions can be remarkably increased due to reasonable structural design, so that the luminous efficiency of the LED device is improved.
The electron blocking layer 600 is an AlInGaN layer with a thickness of 10 nm-40 nm; wherein, the Al component of the electron blocking layer 600 gradually changes from 0.005 to 0.1 along the epitaxial growth direction, and the In component concentration of the electron blocking layer 600 is 0.01-0.2; the electron overflow can be effectively limited, the blocking of holes can be reduced, the injection efficiency of the holes to the quantum well can be improved, the auger recombination of carriers can be reduced, and the luminous efficiency of the light-emitting diode can be improved; in this embodiment, the electron blocking layer 600 has a thickness of 15nm and an in composition concentration of 0.01.
The Mg doping concentration of the p-type GaN layer 700 is 1E+19atoms/cm 3 ～1E+21atoms/cm 3 The method comprises the steps of carrying out a first treatment on the surface of the Too high Mg doping concentration can damage crystal quality, while lower doping concentration can affect hole concentration; in this embodiment, the thickness of the p-type GaN layer 700 is 15nm, and the Mg doping concentration is 2E+20atoms/cm 3 。
Correspondingly, the invention also provides a preparation method of the light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer and comprises the following steps:
s1: providing a substrate 100; the substrate 100 may be a sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate.
Specifically, the substrate 100 is a silicon substrate, which has a large size and low price, and can reduce the epitaxial growth cost. The blue stone substrate with high contrast hardness and poor heat and electric conduction properties has great advantages, and the substrate thinning processing technology is simplified, so that the cost is reduced.
S2: the substrate 100 is subjected to high temperature nitridation to clean the substrate surface and to form Si-N bonds on the substrate surface to better deposit GaN on the substrate surface, the specific embodiments of which are well known to those skilled in the art and will not be described in detail herein.
S3: depositing a composite interposer 200 on the substrate 100, the composite interposer 200 comprising SiO 2 Insertion layer 210, in x Si 1- x N insertion layer 220, inN insertion layer 230, al y In 1-y N insertion layer 240; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9;
further, the thickness of the composite insert layer 200 is 10 nm-500 nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:1:1:1-1:10:5:10;
further, the growth atmosphere of the composite interposer 200 is N 2 With NH 3 And N 2 With NH 3 The mixing volume ratio of (2) is 1:1-1:10;
further, the deposition temperature of the composite insert layer 200 is 500-1000 ℃;
further, the deposition pressure of the composite insert layer 200 is 50-500 torr;
specifically, the composite insert layer 200 includes SiO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, al y In 1-y N insertion layer 240; the thickness of the composite insert layer 200 is 100nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:4:2:4; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.25, al y In 1-y The Al component of the N insert 240 is 0.5 and the composite insert 200 is grown in an atmosphere N 2 With NH 3 The mixing volume ratio of (2) is 1:5, and no H exists 2 The method comprises the steps of carrying out a first treatment on the surface of the The growth temperature of the composite insert layer 200 is 825 ℃; the composite interposer 200 is grown at a pressure of 100torr.
In the embodiment, a medium-micro A7 MOCVD (Metal-organic Chemical Vapor Deposition Metal organic vapor deposition, MOCVD for short) device is adopted to obtain high-purity H 2 (Hydrogen), high purity N 2 (Nitrogen) high purity H 2 And high purity N 2 Is used as carrier gas, high-purity NH 3 As N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, trimethylaluminum (TMAL) as aluminum source, silane (SiH) 4 ) As an N-type dopant, magnesium dicyclopentadiene (CP 2 Mg) as P-type dopant.
S4: depositing an undoped GaN layer 300 on the composite interposer 200; alternatively, undoped GaN layer 300 is grown at 1050-1200deg.C, at 100-600 torr and 1-5 um thick.
Specifically, the growth temperature of the undoped GaN layer 300 is 1100 ℃, the growth pressure is 150torr, the growth thickness is 3um, the growth temperature of the undoped GaN layer 300 is higher, the pressure is lower, the prepared GaN crystal has better quality, meanwhile, the thickness is increased along with the increase of the GaN thickness, the compressive stress can be released through stacking faults, the line defects are reduced, the crystal quality is improved, the reverse leakage is reduced, the consumption of Ga source materials by improving the GaN layer thickness is larger, and the epitaxial cost of an LED is greatly improved, so that the conventional LED epitaxial wafer is usually 3um in growth of the undoped GaN layer 300, the production cost is saved, and the GaN material has higher crystal quality.
S5: depositing an n-type GaN layer 400 on the undoped GaN layer 300; optionally, the growth temperature of the n-type GaN layer 400 is 1050-1200 ℃, the growth pressure is 100-600 torr, the thickness is 2-3 um, and the Si doping concentration is 1E+19atoms/cm 3 ～5E+19atoms/cm 3 。
Specifically, the growth temperature of the n-type GaN layer 400 is 1120 ℃, the growth pressure is 100torr, the growth thickness is 3um, and the Si doping concentration is 2.5E+19atoms/cm 3 Firstly, the n-type GaN layer 400 provides sufficient electrons for LED light emission, secondly, the resistivity of the n-type GaN layer 400 is higher than that of a transparent electrode on p-GaN, so that the resistivity of the n-type GaN layer 400 can be effectively reduced due to sufficient Si doping, and finally, the luminous efficiency of the stress light-emitting diode can be effectively released due to sufficient thickness of the n-type GaN layer 400.
S6: depositing a multiple quantum well layer 500 on the n-type GaN layer 400; alternatively, the multiple quantum well layer 500 is an InGaN quantum well layer and an AlGaN quantum barrier layer which are alternately stacked, wherein the stacking period number is 6-12, the growth temperature of the InGaN quantum well layer is 790-810 ℃, the thickness is 2-5 nm, and the growth pressure is 50-300 torr; the AlGaN quantum barrier layer has a growth temperature of 800-900 ℃, a thickness of 5-15 nm, a growth pressure of 50-300 torr and an Al component of 0.01-0.1.
Specifically, the multiple quantum well layer 500 is an InGaN quantum well layer and an AlGaN quantum barrier layer which are alternately stacked, the stacking cycle number is 10, wherein the InGaN quantum well layer has a growth temperature of 795 ℃, a thickness of 3.5nm, a growth pressure of 200torr, and an in composition of 0.22; the AlGaN quantum barrier layer has the growth temperature of 855 ℃, the thickness of 9.8nm, the growth pressure of 200torr, the Al component of 0.05, and the multiple quantum well as an electron and hole composite region, and the reasonable structural design can remarkably increase the overlapping degree of the electron and hole wave functions, thereby improving the luminous efficiency of the LED device.
S7: depositing an electron blocking layer 600 on the multiple quantum well layer 500; optionally, the electron blocking layer 600 is an AlInGaN layer with a thickness of 10 nm-40 nm, a growth temperature of 900-1000 ℃ and a growth pressure of 100-300 torr, wherein the Al component is 0.005-0.1 and the in component concentration is 0.01-0.2.
Specifically, the thickness of the electron blocking layer 600 is 15nm, wherein the concentration of the Al component gradually changes from 0.01 to 0.05 along the growth direction of the epitaxial layer, the concentration of the in component is 0.01, the growth temperature is 965 ℃, and the growth pressure is 200torr, so that not only can the electron overflow be effectively limited, but also the blocking of holes can be reduced, the injection efficiency of the holes to the quantum wells can be improved, the auger recombination of carriers can be reduced, and the luminous efficiency of the light emitting diode can be improved.
S8: depositing a p-type GaN layer 700 on the electron blocking layer 600; optionally, the p-type GaN layer 700 grows at 900-1050 ℃ and 10-50 nm thick, grows at 100-600 torr under 100-600 torr, and has a doping concentration of 1E+19atoms/cm 3 ～1E+21atoms/cm 3 。
Specifically, the p-type GaN layer 700 has a growth temperature of 985 ℃, a thickness of 15nm, a growth pressure of 200torr, and a Mg doping concentration of 2E+20atoms/cm 3 Too high a Mg doping concentration can damage the crystal quality, while a lower doping concentration can affect the hole concentration. Meanwhile, for the LED structure containing the V-shaped pits, the higher growth temperature of the p-type GaN layer 700 is also beneficial to combining the V-shaped pits, so that the LED epitaxial wafer with a smooth surface is obtained.
The preparation method of the LED epitaxial wafer of the embodiment of the invention comprises the steps of depositing SiO 2 The insert layer 210 can prevent back melting etching between Ga and Si and inhibit tensile stress, so that a GaN film with a flat surface and no cracks is obtained, which lays a foundation for realizing a basic LED device structure; in (In) x Si 1-x The N insertion layer 220 and the InN insertion layer 230 can effectively suppress the extension of threading dislocation, prevent the deterioration of GaN thin film crystal quality and the formation of cracks, but In x Si 1-x Too high an In composition of N insertion layer 220 may result In x Si 1-x The crystal quality of the N insertion layer 220 is degraded, so that the In component takes on a moderate value such that In x Si 1-x The crystal quality of the N insertion layer 220 is better; al (Al) y In 1-y N insertion layer 240 is prepared by preparing Al and InCompared with GaN, the lattice constant is close to that of GaN, the lattice mismatch with the GaN layer is reduced, and the crystal quality of the subsequent deposited GaN is improved.
The light emitting diode epitaxial wafers prepared in example 1 and the comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 1 is improved by 4% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 2
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 150nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:3:2:3; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.20, al y In 1-y The Al composition of the N insertion layer 240 is 0.4;
the light-emitting diode epitaxial wafer prepared in example 2 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 2 is improved by 3.5% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 3
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 10nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:1:1:1; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.01, al y In 1-y The Al composition of the N insertion layer 240 is 0.05;
the light emitting diode epitaxial wafers prepared in example 3 and the comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 3 is improved by 1.6% compared with that of the comparative example through test instruments, and other electrical properties are good, and specific results are shown in Table 1.
Example 4
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 150nm, al y In 1-y The Al composition of the N insertion layer 240 is 0.6;
the light-emitting diode epitaxial wafer prepared in example 4 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 4 is improved by 3.2% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 5
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 450nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:10:5:10; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.35, al y In 1-y The Al composition of the N insertion layer 240 is 0.9;
the light-emitting diode epitaxial wafer prepared in example 5 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are respectively extracted, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 5 is improved by 1.5% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in table 1.
Example 6
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 500nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:6:3:6; in (In) x Si 1-x The In composition of N insertion layer 220 is 0.45;
the light-emitting diode epitaxial wafer prepared in example 6 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 6 is improved by 3.5% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 7
This embodiment differs from embodiment 1 in that: the thickness of the composite insert layer 200 in this embodiment is 300nm; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.5, al y In 1-y The Al composition of the N insertion layer 240 is 0.1;
the light-emitting diode epitaxial wafer prepared in example 7 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 7 is improved by 1.8% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 8
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite interposer 200 is 200nm, in x Si 1-x The In composition of the N insertion layer 220 is 0.1;
the light-emitting diode epitaxial wafer prepared in example 8 and the light-emitting diode epitaxial wafer prepared in comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 8 is improved by 3.5% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 9
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 400nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:7:2:7; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.05, al y In 1-y The Al composition of the N insertion layer 240 is 0.8;
the light-emitting diode epitaxial wafers prepared in example 9 and the comparative example are prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 9 is improved by 1.8% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Example 10
This embodiment differs from embodiment 1 in that: in this embodiment, the thickness of the composite insert layer 200 is 50nm, siO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230, and Al y In 1-y The thickness ratio of the N insertion layer 240 is 1:5:4:5; in (In) x Si 1-x The In composition of the N insertion layer 220 is 0.15, al y In 1-y The Al composition of the N insertion layer 240 is 0.7;
the light emitting diode epitaxial wafer prepared in example 10 and comparative example is prepared into 10×24mil chips by using the same chip process conditions, 300 LED chips are extracted respectively, the photoelectric properties of the chips are tested under 120mA/60mA current, the light efficiency of example 10 is improved by 2.5% compared with that of the comparative example through test instruments, other items of electrical properties are good, and specific results are shown in Table 1.
Comparative example
This comparative example differs from example 1 in that a 100nm GaN insertion layer was first deposited on the substrate, instead of the composite insertion layer 200 in this application, the remainder being the same as example 1.
Table 1: comparison table for comparing partial parameters of each embodiment and comparison example and improving corresponding light effect
As can be seen from the above table, the led epitaxial wafer provided by the present invention comprises a substrate 100 subjected to high temperature nitridation treatment, and a composite insertion layer 200, an undoped GaN layer 300, an n-type GaN layer 400, a multiple quantum well layer 500, an electron blocking layer 600 and a p-type GaN layer 700 sequentially stacked on the substrate 100; the composite interposer 200 comprises SiO 2 Insertion layer 210, in x Si 1-x N insertion layer 220, inN insertion layer 230,Al y In 1-y N insertion layer 240; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9. By deposition of SiO 2 The insert layer 210 can prevent back melting etching between Ga and Si and inhibit tensile stress, so that a GaN film with a flat surface and no cracks is obtained, which lays a foundation for realizing a basic LED device structure; in (In) x Si 1-x The N insertion layer 220 and the InN insertion layer 230 can effectively suppress the extension of threading dislocation, prevent the deterioration of GaN thin film crystal quality and the formation of cracks, but In x Si 1-x Too high an In composition of N insertion layer 220 may result In x Si 1-x The crystal quality of the N insertion layer 220 is degraded, so that the In component takes on moderate values to enable In x Si 1-x The crystal quality of the N insertion layer 220 is better; al (Al) y In 1-y The lattice constant of the N insertion layer 240 is close to that of GaN by adjusting the proportion of Al and In, so that the lattice mismatch with the GaN layer is reduced, and the crystal quality of the subsequently deposited GaN is improved; in summary, the invention can effectively reduce dislocation density of epitaxial layer, inhibit extension of threading dislocation, improve GaN crystal quality, improve radiation recombination efficiency, and improve luminous efficiency of light emitting diode.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above additional technical features can be freely combined and superimposed by a person skilled in the art without conflict.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. The light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a composite insertion layer, an undoped GaN layer, an n-type GaN layer, a multiple quantum well layer, an electron blocking layer and a p-type GaN layer which are sequentially laminated on the substrate;
the composite insert layer comprises SiO 2 Insertion layer, in x Si 1-x N insertion layer, inN insertion layer, al y In 1-y An N insertion layer; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9.
2. The light-emitting diode epitaxial wafer according to claim 1, wherein the thickness of the composite insertion layer is 10nm to 500nm, and the SiO is 2 An insertion layer, the In x Si 1-x N insertion layer, inN insertion layer and Al y In 1-y The thickness ratio of the N insertion layers is 1:1:1:1-1:10:5:10.
3. The light emitting diode epitaxial wafer of claim 1, wherein the undoped GaN layer has a thickness of 1um to 5um.
4. The light-emitting diode epitaxial wafer of claim 1, wherein the n-type GaN layer has a Si doping concentration of 1e+19atoms/cm 3 ～5E+19atoms/cm 3 。
5. The light-emitting diode epitaxial wafer of claim 1, wherein the electron blocking layer is an AlInGaN layer having a thickness of 10nm to 40nm; the Al component of the electron blocking layer gradually changes from 0.005 to 0.1 along the epitaxial growth direction, and the In component concentration of the electron blocking layer is 0.01-0.2.
6. The light-emitting diode epitaxial wafer of claim 1, wherein the P-type GaN layer has a Mg doping concentration of 1e+19atoms/cm 3 ～1E+21atoms/cm 3 。
7. A method for preparing a light-emitting diode epitaxial wafer, which is used for preparing the light-emitting diode epitaxial wafer according to claims 1 to 6, and is characterized by comprising the following steps:
providing a substrate;
nitriding the substrate at a high temperature;
depositing a composite interposer on the substrate, the composite interposer comprising SiO 2 Insertion layer, in x Si 1-x N insertion layer, inN insertion layer, al y In 1-y An N insertion layer; wherein, the value range of x is 0.01-0.5, and the value range of y is 0.05-0.9;
depositing an undoped GaN layer on the composite interposer;
depositing an n-type GaN layer on the undoped GaN layer;
depositing a multi-quantum well layer on the n-type GaN layer;
depositing an electron blocking layer on the multiple quantum well layer;
and depositing a p-type GaN layer on the electron blocking layer.
8. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the growth atmosphere of the composite interposer layer is N 2 With NH 3 And N 2 With NH 3 The mixing volume ratio of (2) is 1:1-1:10.
9. The method for preparing a light-emitting diode epitaxial wafer according to claim 7, wherein the deposition temperature of the composite interposer is 500-1000 ℃.
10. The method for manufacturing a light-emitting diode epitaxial wafer according to claim 7, wherein the deposition pressure of the composite interposer is 50-500 torr.
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