CN114093989B - Deep ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof - Google Patents
Deep ultraviolet light-emitting diode epitaxial wafer and manufacturing method thereof Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000005240 physical vapour deposition Methods 0.000 claims abstract description 17
- 230000000903 blocking effect Effects 0.000 claims abstract description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 7
- 150000002902 organometallic compounds Chemical class 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 6
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- 238000001259 photo etching Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 27
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 24
- 229910052757 nitrogen Inorganic materials 0.000 description 8
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
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- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- IBEFSUTVZWZJEL-UHFFFAOYSA-N trimethylindium Chemical compound C[In](C)C IBEFSUTVZWZJEL-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
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- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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Abstract
The present disclosure provides a deep ultraviolet light emitting diode epitaxial wafer and a manufacturing method thereof, which belong to the technical field of semiconductors. The deep ultraviolet light-emitting diode epitaxial wafer comprises a substrate, and a first AlN layer, a second AlN layer, an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate; the radius of the first AlN layer is smaller than that of the substrate, the first AlN layer is deposited by adopting a physical vapor deposition method, and the second AlN layer is grown by adopting a metal organic compound chemical vapor deposition method. The deep ultraviolet light-emitting diode epitaxial wafer can effectively release stress, inhibit the generation of cracks in the AlN growth process, improve the crystal quality and improve the photoelectric performance of the deep ultraviolet light-emitting diode.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, in particular to a deep ultraviolet light emitting diode epitaxial wafer and a manufacturing method thereof.
Background
The light emitting diode (English: light Emitting Diode, abbreviated as LED) is used as a new product with great influence in the photoelectron industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption and the like, and is widely applied to the fields of illumination, display screens, signal lamps, backlights, toys and the like.
The core structure of the LED is an epitaxial wafer, and the manufacture of the epitaxial wafer has a great influence on the photoelectric characteristics of the LED. The epitaxial wafer generally includes a substrate, and an N-type layer, an active layer, and a P-type layer sequentially stacked on the substrate. Electrons provided by the N-type layer and holes provided by the P-type layer perform radiation recombination luminescence in the active layer. The deep ultraviolet light emitting diode is a light emitting diode with the light emitting wavelength of 200-350 nm, and an N-type layer in an epitaxial wafer of the deep ultraviolet light emitting diode is usually an AlGaN layer. The high quality AlGaN layer can improve the luminous efficiency of the deep ultraviolet LED, and in order to improve the quality of the AlGaN layer and reduce the dislocation density, an AlN buffer layer is usually further provided before the N-type layer.
The AlN material grown in a high-temperature environment has better crystal quality, so that an AlN buffer layer is grown at a high temperature. But the AlN material grown at high temperature is easy to crack, so that the epitaxial growth of a subsequent epitaxial wafer can be influenced.
Disclosure of Invention
The embodiment of the disclosure provides a deep ultraviolet light emitting diode epitaxial wafer and a manufacturing method thereof, which can effectively release stress, inhibit crack generation in an AlN growth process, improve crystal quality and promote photoelectric performance of the deep ultraviolet light emitting diode. The technical scheme is as follows:
in a first aspect, a deep ultraviolet light emitting diode epitaxial wafer is provided, the deep ultraviolet light emitting diode epitaxial wafer comprises a substrate, and a first AlN layer, a second AlN layer, an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate;
the radius of the first AlN layer is smaller than that of the substrate, the first AlN layer is deposited by adopting a physical vapor deposition method, and the second AlN layer is grown by adopting a metal organic compound chemical vapor deposition method.
Optionally, the difference between the radius of the first AlN layer and the radius of the substrate is 0.1 to 5mm.
Optionally, the thickness of the first AlN layer is smaller than the thickness of the second AlN layer.
Optionally, the thickness of the first AlN layer is 1 to 100nm.
Optionally, the thickness of the second AlN layer is 2-3 um.
In another aspect, there is provided a method for manufacturing a deep ultraviolet light emitting diode epitaxial wafer, the method comprising:
providing a substrate;
depositing a first AlN layer on the substrate by adopting a physical vapor deposition method;
processing the first AlN layer to enable the radius of the first AlN layer to be smaller than that of the substrate;
growing a second AlN layer on the first AlN layer by adopting a metal organic compound chemical vapor deposition method;
and an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer are sequentially grown on the second AlN layer.
Optionally, the processing the first AlN layer includes:
and processing the first AlN layer by adopting a photoetching technology and an etching technology, and removing part of edge regions of the first AlN layer along the circumferential direction of the first AlN layer to expose the surface of the substrate.
Optionally, the difference between the radius of the first AlN layer and the radius of the substrate is 0.1 to 5mm.
Optionally, the growth temperature of the first AlN layer is less than the growth temperature of the second AlN layer.
Optionally, the growth temperature of the first AlN layer is 500-700 ℃, and the growth temperature of the second AlN layer is 1200-1400 ℃.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that:
by arranging the first AlN layer and the second AlN layer between the substrate and the N-type layer, the first AlN layer and the second AlN layer can play a role in buffering, and dislocation generation is reduced. The first AlN layer is deposited by a physical vapor deposition method, and the formed first AlN layer has smaller and more uniform AlN particles and better C-axis orientation. And growing a second AlN layer on the first AlN layer, which is favorable for forming crystals with better crystal quality, thereby improving the crystal quality. Meanwhile, the radius of the first AlN layer is smaller than that of the substrate, and when the subsequent epitaxial layer is grown, an unoccupied region between the outer side of the first AlN layer and the surface of the substrate can be used as a stress release region to effectively release stress, so that the generation of cracks in the AlN growth process is restrained, the crystal quality is further improved, and the photoelectric performance of the deep ultraviolet light-emitting diode is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for manufacturing a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the present disclosure;
fig. 3 is a flowchart of another method for manufacturing a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the present disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the present disclosure, and as shown in fig. 1, the deep ultraviolet light emitting diode epitaxial wafer includes a substrate 1, and a first AlN layer 2, a second AlN layer 3, an N-type layer 4, an active layer 5, an electron blocking layer 6, a P-type layer 7, and a P-type contact layer 8 sequentially stacked on the substrate 1.
The radius of the first AlN layer 2 is smaller than that of the substrate 1, the first AlN layer 2 is deposited by a physical vapor deposition (Physical Vapor Deposition, PVD) method, and the second AlN layer 3 is grown by a metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) method.
According to the embodiment of the disclosure, the first AlN layer and the second AlN layer are arranged between the substrate and the N-type layer, so that the first AlN layer and the second AlN layer can play a role in buffering, and dislocation generation is reduced. The first AlN layer is deposited by a physical vapor deposition method, and the formed first AlN layer has smaller and more uniform AlN particles and better C-axis orientation. And growing a second AlN layer on the first AlN layer, which is favorable for forming crystals with better crystal quality, thereby improving the crystal quality. Meanwhile, the radius of the first AlN layer is smaller than that of the substrate, and when the subsequent epitaxial layer is grown, an unoccupied region between the outer side of the first AlN layer and the surface of the substrate can be used as a stress release region to effectively release stress, so that the generation of cracks in the AlN growth process is restrained, the crystal quality is further improved, and the photoelectric performance of the deep ultraviolet light-emitting diode is improved.
Alternatively, as shown in fig. 1, the difference Δd between the radius of the first AlN layer 2 and the radius of the substrate 1 is 0.1 to 5mm.
If the difference between the radius of the first AlN layer 2 and the radius of the substrate 1 is too small, a good stress relief effect is not achieved. If the difference between the radius of the first AlN layer 2 and the radius of the substrate 1 is too large, the probability of fogging of the region left between the outside of the first AlN layer 2 and the surface of the substrate 1 increases.
Alternatively, the thickness of the first AlN layer 2 is smaller than the thickness of the second AlN layer 3.
The first AlN layer grows by adopting a PVD method, is thinner, and is favorable for forming a film with better crystallization quality, and is used as a growth substrate of the second AlN layer. The second AlN layer serves as a buffer layer and mainly serves to reduce dislocation, and thus the second AlN layer is provided thicker.
Alternatively, the thickness of the first AlN layer 2 is 1 to 100nm.
If the thickness of the first AlN layer 2 is too thin, a good base function is not performed to improve the crystal quality of the second AlN layer. If the thickness of the first AlN layer 2 is too large, defects are likely to occur, resulting in poor crystal quality.
Alternatively, the thickness of the second AlN layer 3 is 2 to 3um.
If the thickness of the second AlN layer 3 is too thin, the dislocation defect cannot be reduced well. If the thickness of the second AlN layer 3 is too large, defects are more likely to be generated, resulting in poor crystal quality.
In the embodiment of the present disclosure, the first AlN layer 2 is grown in a low-temperature and low-pressure environment, and the second AlN layer 3 is grown in a high-temperature and high-pressure environment.
Alternatively, the substrate is a flat sheet substrate. Such as a sapphire substrate, a silicon wafer, or a silicon carbide substrate.
Optionally, the N-type layer 4 is an AlGaN layer doped with silane, and the thickness of the N-type layer 63 is 500 to 2000nm.
Optionally, the active layer 5 includes 3-15 quantum well layers and quantum barrier layers alternately grown, wherein the quantum well layers are Al x Ga 1-x N/Al y Ga 1-y N(x<y) layer, quantum barrier layer is Al y Ga 1-y And N layers.
Illustratively, the quantum well layer has a thickness of 2-5 nm and the quantum barrier layer has a thickness of 8-12 nm.
Optionally, the electron blocking layer 6 is a P-type AlGaN layer doped with Mg, and the thickness is 5-50 nm.
Optionally, the P-type layer 7 is a P-type AlGaN layer doped with Mg, and the thickness is 10-500 nm.
Optionally, the P-type contact layer 8 is P-type AlGaN doped with Mg, and the thickness is 10-100 nm.
In one specific implementation of the deep ultraviolet light emitting diode epitaxial wafer shown in fig. 1, the difference Δd=3 mm between the radius of the first AlN layer 2 of the epitaxial wafer and the radius of the substrate 1. The thickness of the first AlN layer 2 was 50nm. The thickness of the second AlN layer 3 was 2um.
Illustratively, the substrate 1 is a sapphire flat substrate.
Illustratively, N-type layer 4 is a silane doped AlGaN layer and N-type layer 63 has a thickness of 700nm.
The active layer 5 comprises 5 periodically alternately grown quantum well layers and quantum barrier layers, wherein the quantum well layers are Al x Ga 1-x N/Al y Ga 1-y N(x<y) layer, quantum barrier layer is Al y Ga 1-y And N layers.
Illustratively, the quantum well layer has a thickness of 3nm and the quantum barrier layer has a thickness of 11nm.
The electron blocking layer 6 is illustratively a Mg doped P-type AlGaN layer having a thickness of 10nm.
The P-type layer 7 is illustratively a Mg doped P-type AlGaN layer having a thickness of 25nm.
The P-type contact layer 8 is illustratively Mg-doped P-type AlGaN with a thickness of 50nm.
In another specific implementation of the deep ultraviolet light emitting diode epitaxial wafer shown in fig. 1, the difference Δd=4 mm between the radius of the first AlN layer 2 of the epitaxial wafer and the radius of the substrate 1. The thickness of the first AlN layer 2 was 60nm. The thickness of the second AlN layer 3 was 2.5um.
Illustratively, the substrate 1 is a sapphire flat substrate.
Illustratively, N-type layer 4 is a silane doped AlGaN layer and N-type layer 63 has a thickness of 750nm.
The active layer 5 comprises 8 periodically alternately grown quantum well layers and quantum barrier layers, wherein the quantum well layers are Al x Ga 1-x N/Al y Ga 1-y N(x<y) layer, quantum barrier layer is Al y Ga 1-y And N layers.
Illustratively, the quantum well layer has a thickness of 3nm and the quantum barrier layer has a thickness of 10nm.
The electron blocking layer 6 is illustratively a Mg doped P-type AlGaN layer having a thickness of 20nm.
The P-type layer 7 is illustratively a Mg doped P-type AlGaN layer having a thickness of 50nm.
The P-type contact layer 8 is illustratively Mg-doped P-type AlGaN with a thickness of 50nm.
In yet another specific implementation of the deep ultraviolet light emitting diode epitaxial wafer shown in fig. 1, the difference Δd=2 mm between the radius of the first AlN layer 2 of the epitaxial wafer and the radius of the substrate 1. The thickness of the first AlN layer 2 was 80nm. The thickness of the second AlN layer 3 was 2.5um.
Illustratively, the substrate 1 is a sapphire flat substrate.
Illustratively, N-type layer 4 is a silane doped AlGaN layer and N-type layer 63 has a thickness of 600nm.
The active layer 5 comprises 7 periodically alternately grown quantum well layers and quantum barrier layers, wherein the quantum well layers are Al x Ga 1-x N/Al y Ga 1-y N(x<y) layer, quantum barrier layer is Al y Ga 1-y And N layers.
Illustratively, the quantum well layer has a thickness of 4nm and the quantum barrier layer has a thickness of 8nm.
The electron blocking layer 6 is illustratively a Mg doped P-type AlGaN layer having a thickness of 30nm.
The P-type layer 7 is illustratively a Mg doped P-type AlGaN layer having a thickness of 90nm.
The P-type contact layer 8 is illustratively Mg-doped P-type AlGaN with a thickness of 60nm.
Fig. 2 is a flowchart of a method for manufacturing a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the disclosure, where, as shown in fig. 2, the method includes:
step 201, a substrate is provided.
Alternatively, the substrate may be a flat substrate, such as a sapphire substrate, a silicon wafer, or a silicon carbide substrate.
Step 202, depositing a first AlN layer on a substrate by adopting a PVD method.
And 203, processing the first AlN layer to enable the radius of the first AlN layer to be smaller than that of the substrate.
And 204, growing a second AlN layer on the first AlN layer by adopting an MOCVD method.
And step 205, sequentially growing an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer on the second AlN layer.
According to the embodiment of the disclosure, the first AlN layer and the second AlN layer are arranged between the substrate and the N-type layer, so that the first AlN layer and the second AlN layer can play a role in buffering, and dislocation generation is reduced. The first AlN layer is deposited by a physical vapor deposition method, and the formed first AlN layer has smaller and more uniform AlN particles and better C-axis orientation. And growing a second AlN layer on the first AlN layer, which is favorable for forming crystals with better crystal quality, thereby improving the crystal quality. Meanwhile, the radius of the first AlN layer is smaller than that of the substrate, and when the subsequent epitaxial layer is grown, an unoccupied region between the outer side of the first AlN layer and the surface of the substrate can be used as a stress release region to effectively release stress, so that the generation of cracks in the AlN growth process is restrained, the crystal quality is further improved, and the photoelectric performance of the deep ultraviolet light-emitting diode is improved.
Fig. 3 is a flowchart of another method for manufacturing a deep ultraviolet light emitting diode epitaxial wafer according to an embodiment of the disclosure, where, as shown in fig. 3, the manufacturing method includes:
step 301, a substrate is provided.
Alternatively, the substrate may be a flat substrate, such as a sapphire substrate, a silicon wafer, or a silicon carbide substrate.
The diameter of the substrate is illustratively 50mm.
Step 302, depositing a first AlN layer on a substrate by PVD.
Alternatively, the first AlN layer has a thickness of 1 to 100nm.
If the thickness of the first AlN layer is too thin, a good substrate function cannot be achieved, so that the crystal quality of the second AlN layer is improved. If the thickness of the first AlN layer is too thick, defects are easily generated, resulting in poor crystal quality.
Illustratively, step 302 may include:
and placing the substrate into a PVD device, controlling the temperature of a reaction chamber of the PVD device to be 600 ℃, controlling the pressure to be 7mTorr, controlling the sputtering power to be 4000W, respectively controlling the flow rates of introduced nitrogen and argon to be 150sccm and 80sccm, and depositing a first AlN layer on the substrate for 50 s.
In the embodiment of the disclosure, the first AlN layer is grown in a low-temperature and low-pressure environment, so that the crystal quality of the grown first AlN layer can be ensured.
And 303, processing the first AlN layer to enable the radius of the first AlN layer to be smaller than that of the substrate.
Illustratively, step 303 may include:
and processing the first AlN layer by adopting a photoetching technology and an etching technology, and removing part of the edge area of the first AlN layer along the circumferential direction of the first AlN layer to expose the surface of the substrate.
Alternatively, the difference Δd between the radius of the first AlN layer and the radius of the substrate is 0.1 to 5mm.
If the difference between the radius of the first AlN layer and the radius of the substrate is too small, a good stress relief effect is not achieved. If the difference between the radius of the first AlN layer and the radius of the substrate is too large, the probability of fogging of the vacant region between the outside of the first AlN layer and the surface of the substrate increases.
Alternatively, the etching technique may be one of a wet etching technique or a plasma etching technique, which may be implemented in a variety of ways.
In the embodiment of the present disclosure, the radius of the first AlN layer may be reduced to 49mm.
And 304, growing a second AlN layer on the first AlN layer by adopting an MOCVD method.
Optionally, the thickness of the second AlN layer is 2 to 3um.
If the thickness of the second AlN layer is too thin, the dislocation defect cannot be reduced well. If the second AlN layer is too thick, defects are more likely to be generated, resulting in poor crystal quality.
Illustratively, step 304 may include:
the first AlN sub-layer is put into MOCVD equipment, the temperature of a reaction chamber of the MOCVD equipment is controlled to be 1350 ℃, the pressure is controlled to be 150mbar, and a second AlN sub-layer with the thickness of 2.5um is grown on the first AlN sub-layer.
In the embodiment of the disclosure, the second AlN layer is grown under a high-temperature and high-pressure environment, so that the crystal quality of the grown second AlN layer can be ensured.
And 305, growing an N-type layer on the second AlN layer.
Wherein the N-type layer is an AlGaN layer doped with Si, and the thickness of the N-type layer is 500-2000 nm.
In this embodiment, the manufacturing method of the epitaxial wafer may be implemented using a Veeco K465i or C4 or RB MOCVD apparatus. Adopts high-purity H 2 (Hydrogen) or high purity N 2 (Nitrogen) or high purity H 2 And high purity N 2 High purity NH using the mixed gas of (2) as carrier gas 3 As nitrogen source, trimethylgallium (TMGa) and triethylgallium (TEGa) as gallium source, trimethylindium (TMIn) as indium source, silane (SiH 4) as N-type dopant, i.e., si source, trimethylaluminum (TMAL) as aluminum source, magnesium-cyclopentadienyl (CP 2 Mg) as P-type dopant, i.e., mg source. The control of temperature and pressure refers to the control of temperature and pressure in the reaction chamber in which the epitaxial wafer is grown.
Illustratively, step 305 may include:
the reaction chamber temperature was controlled at 1060℃and the pressure at 100mbar, and a silane doped n-type AlGaN layer was grown with a layer thickness of 700nm.
Step 306, growing an active layer on the N-type layer.
Optionally, the active layer 5 includes 3-15 quantum well layers and quantum barrier layers alternately grown, wherein the quantum well layers are Al x Ga 1-x N/Al y Ga 1-y N(x<y) layer, quantum barrier layer is Al y Ga 1-y And N layers.
Illustratively, the quantum well layer has a thickness of 2-5 nm and the quantum barrier layer has a thickness of 8-12 nm.
Optionally, step 306 may include:
the reaction chamber temperature was controlled at 1040 c and the pressure at 150mbar and an active layer was grown on the N-type layer.
Step 307, growing an electron blocking layer on the active layer.
The electron blocking layer is a P-type AlGaN layer doped with Mg, and the thickness is 5-50 nm.
Illustratively, step 307 may comprise:
the temperature of the reaction chamber was controlled to 980 ℃ and the pressure was controlled to 150mbar, and an electron blocking layer with a thickness of 10nm was grown on the active layer.
Step 308, growing a P-type layer on the electron blocking layer.
Wherein the P-type layer is a Mg-doped P-type AlGaN layer with the thickness of 10-500 nm.
Illustratively, step 308 may include:
the temperature of the reaction chamber is controlled to be 900 ℃ and the pressure is controlled to be 200mbar, and a P-type layer with the thickness of 25nm is grown on the electron blocking layer.
Step 309, growing a P-type contact layer on the P-type layer.
Wherein the P-type contact layer is Mg-doped P-type AlGaN, and the thickness is 10-100 nm.
Illustratively, step 309 may include:
the temperature of the reaction chamber is controlled to 850 ℃, the pressure is 300mbar, and a P-type contact layer with the thickness of 50nm is grown on the P-type layer.
After the epitaxial growth is completed, the temperature is first reduced to 650 to 850 ℃, the epitaxial wafer is annealed in a nitrogen atmosphere for 30 minutes, and then the temperature of the epitaxial wafer is reduced to room temperature.
According to the embodiment of the disclosure, the first AlN layer and the second AlN layer are arranged between the substrate and the N-type layer, so that the first AlN layer and the second AlN layer can play a role in buffering, and dislocation generation is reduced. The first AlN layer is deposited by a physical vapor deposition method, and the formed first AlN layer has smaller and more uniform AlN particles and better C-axis orientation. And growing a second AlN layer on the first AlN layer, which is favorable for forming crystals with better crystal quality, thereby improving the crystal quality. Meanwhile, the radius of the first AlN layer is smaller than that of the substrate, and when the subsequent epitaxial layer is grown, an unoccupied region between the outer side of the first AlN layer and the surface of the substrate can be used as a stress release region to effectively release stress, so that the generation of cracks in the AlN growth process is restrained, the crystal quality is further improved, and the photoelectric performance of the deep ultraviolet light-emitting diode is improved.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," "third," and the like in the description and in the claims, are not used for any order, quantity, or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", "top", "bottom" and the like are used only to indicate relative positional relationships, which may be changed accordingly when the absolute position of the object to be described is changed.
While the present disclosure has been described above by way of example, and not by way of limitation, any person skilled in the art will recognize that many modifications, adaptations, and variations of the present disclosure can be made to the present embodiments without departing from the scope of the present disclosure.
Claims (10)
1. The deep ultraviolet light-emitting diode epitaxial wafer is characterized by comprising a substrate, and a first AlN layer, a second AlN layer, an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate; the active layer comprises a quantum well layer and a quantum barrier layer;
the radius of the first AlN layer is smaller than that of the substrate, the first AlN layer is deposited by adopting a physical vapor deposition method, the second AlN layer is grown by adopting a metal organic compound chemical vapor deposition method, and the radius of the second AlN layer is larger than that of the first AlN layer.
2. The deep ultraviolet light emitting diode epitaxial wafer of claim 1, wherein a difference between a radius of the first AlN layer and a radius of the substrate is 0.1 to 5mm.
3. The deep ultraviolet light emitting diode epitaxial wafer of claim 1, wherein the thickness of the first AlN layer is less than the thickness of the second AlN layer.
4. The deep ultraviolet light emitting diode epitaxial wafer of claim 3, wherein the thickness of the first AlN layer is 1 to 100nm.
5. The deep ultraviolet light emitting diode epitaxial wafer of claim 3, wherein the second AlN layer has a thickness of 2-3 um.
6. The manufacturing method of the deep ultraviolet light-emitting diode epitaxial wafer is characterized by comprising the following steps of:
providing a substrate;
depositing a first AlN layer on the substrate by adopting a physical vapor deposition method;
processing the first AlN layer to enable the radius of the first AlN layer to be smaller than that of the substrate;
growing a second AlN layer on the first AlN layer by adopting a metal organic compound chemical vapor deposition method, wherein the radius of the second AlN layer is larger than that of the first AlN layer;
and an N-type layer, an active layer, an electron blocking layer, a P-type layer and a P-type contact layer are sequentially grown on the second AlN layer, wherein the active layer comprises a quantum well layer and a quantum barrier layer.
7. The method of manufacturing according to claim 6, wherein the processing the first AlN layer includes:
and processing the first AlN layer by adopting a photoetching technology and an etching technology, and removing part of edge regions of the first AlN layer along the circumferential direction of the first AlN layer to expose the surface of the substrate.
8. The method according to claim 6, wherein a difference between a radius of the first AlN layer and a radius of the substrate is 0.1 to 5mm.
9. The method according to claim 6, wherein a growth temperature of the first AlN layer is lower than a growth temperature of the second AlN layer.
10. The method according to claim 9, wherein the first AlN layer has a growth temperature of 500 to 700 ℃ and the second AlN layer has a growth temperature of 1200 to 1400 ℃.
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