CN112786746B - Epitaxial wafer of light-emitting diode and preparation method thereof - Google Patents
Epitaxial wafer of light-emitting diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 230000007704 transition Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 13
- 239000013078 crystal Substances 0.000 abstract description 17
- 238000003475 lamination Methods 0.000 abstract description 13
- 239000000463 material Substances 0.000 abstract description 7
- 230000000903 blocking effect Effects 0.000 abstract description 6
- 230000004888 barrier function Effects 0.000 description 38
- 229910052594 sapphire Inorganic materials 0.000 description 12
- 239000010980 sapphire Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000007547 defect Effects 0.000 description 6
- 230000001737 promoting effect Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
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- 238000005516 engineering process Methods 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- UOSXPFXWANTMIZ-UHFFFAOYSA-N cyclopenta-1,3-diene;magnesium Chemical compound [Mg].C1C=CC=C1.C1C=CC=C1 UOSXPFXWANTMIZ-UHFFFAOYSA-N 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- RGGPNXQUMRMPRA-UHFFFAOYSA-N triethylgallium Chemical compound CC[Ga](CC)CC RGGPNXQUMRMPRA-UHFFFAOYSA-N 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Abstract
The present disclosure provides an epitaxial wafer of a light emitting diode and a preparation method thereof, which belong to the technical field of photoelectron manufacturing. The epitaxial wafer comprises a substrate, and a first high-temperature AlN buffer layer, a superlattice layer, a second high-temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multiple quantum well layer and a p-type layer which are sequentially formed on the substrate, wherein the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are alternately laminated. The SiN layer can play a role in blocking threading dislocation, the alternately laminated AlN layers and SiN layers can bend the dislocation extended from the first high-temperature AlN buffer layer, the probability of annihilation of the dislocation is increased, the AlN crystal quality is better and better in the lamination direction of the layers, the whole crystal quality of the epitaxial wafer is improved, and the superlattice layer can also relieve tensile stress in an AlN material, so that the luminous efficiency of the ultraviolet LED is improved.
Description
Technical Field
The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular, to an epitaxial wafer of a light emitting diode and a preparation method thereof.
Background
The light emitting diode (English: light Emitting Diode, abbreviated as LED) is used as a new product with great influence in the photoelectron industry, has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption and the like, and is widely applied to the fields of illumination, display screens, signal lamps, backlights, toys and the like. The core structure of the LED is an epitaxial wafer, and the manufacture of the epitaxial wafer has a great influence on the photoelectric characteristics of the LED.
The epitaxial wafer typically includes a buffer layer, an n-type layer, a multiple quantum well layer, and a p-type layer. In the epitaxial wafer of the ultraviolet light emitting diode, the buffer layer is usually an AlN layer, more dislocation defects are easily accumulated in the AlN layer, the quality of a crystal structure which grows later in the epitaxial wafer is poor, and the AlN layer also has larger tensile stress and is easy to generate cracks due to overlarge tensile stress.
Disclosure of Invention
The embodiment of the disclosure provides an epitaxial wafer of a light-emitting diode and a preparation method thereof, which can improve the crystal quality of the epitaxial wafer of an ultraviolet light-emitting diode and reduce the tensile stress in an AlN layer. The technical scheme is as follows:
in one aspect, an embodiment of the present disclosure provides an epitaxial wafer of a light emitting diode, the epitaxial wafer including a substrate and a first high temperature AlN buffer layer, a superlattice layer, a second high temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multiple quantum well layer, and a p-type layer sequentially formed on the substrate, wherein the superlattice layer includes a plurality of AlN layers and a plurality of SiN layers that are alternately stacked.
Alternatively, the AlN layers and the SiN layers are alternately laminated with a cycle number of 20 to 40.
Optionally, the thickness of the AlN layer is 1 nm-100 nm, and the thickness of the SiN layer is 1 nm-100 nm.
Optionally, the thickness of the first high-temperature AlN buffer layer is 100 nm-500 nm.
Optionally, the thickness of the second high-temperature AlN buffer layer is 1000 nm-2000 nm.
On the other hand, the embodiment of the disclosure also provides a preparation method of the epitaxial wafer of the light-emitting diode, which comprises the following steps:
providing a substrate;
and sequentially epitaxially growing a first high-temperature AlN buffer layer, a superlattice layer, a second high-temperature AlN buffer layer, an AlGaN transition layer, an n-type AlGaN layer, a multiple quantum well layer and a p-type layer on the substrate, wherein the superlattice layer comprises a plurality of AlN layers and a plurality of SiN layers which are alternately laminated.
Optionally, the growth temperature of the first high-temperature AlN buffer layer is 1200-1300 ℃, and the growth pressure is 30-70 mbar.
Optionally, the growth temperature of the superlattice layer is 1300-1400 ℃, and the growth pressure is 30-70 mbar.
Optionally, the growth temperature of the second high-temperature AlN buffer layer is 1300-1400 ℃, and the growth pressure is 30-70 mbar.
Optionally, the growth pressures of the first high-temperature AlN buffer layer, the superlattice layer and the second high-temperature AlN buffer layer are the same.
The technical scheme provided by the embodiment of the disclosure has the beneficial effects that at least:
through the surface lamination of the substrate sets up first high temperature AlN buffer layer, superlattice layer and second high temperature AlN buffer layer, the superlattice layer includes a plurality of AlN layers and a plurality of SiN layer of alternating lamination, and wherein the SiN layer can play the effect of stopping threading dislocation, and the dislocation bending that extends by first high temperature AlN buffer layer is gone up to alternating lamination AlN layer and SiN layer, increase the probability that dislocation annihilates each other, make in the direction of each layer lamination, the crystal quality of AlN is better and better, be favorable to promoting the holistic crystal quality of epitaxial wafer, the tensile stress in the AlN material can also be alleviated to the superlattice layer, avoid AlN material to produce the crackle owing to tensile stress is too big, further promote the holistic crystal quality of epitaxial wafer, make ultraviolet LED's luminous efficacy obtain promoting.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of another light emitting diode according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 6 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 10 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 11 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure;
fig. 12 is a schematic diagram of a process for preparing an epitaxial wafer of a light emitting diode according to an embodiment of the disclosure.
Detailed Description
For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure. As shown in fig. 1, the epitaxial wafer includes a substrate 10 and a first high temperature AlN buffer layer 20, a superlattice layer 30, a second high temperature AlN buffer layer 40, an AlGaN transition layer 50, an n-AlGaN layer 60, a multiple quantum well layer 70, and a p-type layer 80 sequentially formed on the substrate 10. Wherein the superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked.
Through the surface lamination of the substrate sets up first high temperature AlN buffer layer, superlattice layer and second high temperature AlN buffer layer, the superlattice layer includes a plurality of AlN layers and a plurality of SiN layer of alternating lamination, and wherein the SiN layer can play the effect of stopping threading dislocation, and the dislocation bending that extends by first high temperature AlN buffer layer is gone up to alternating lamination AlN layer and SiN layer, increase the probability that dislocation annihilates each other, make in the direction of each layer lamination, the crystal quality of AlN is better and better, be favorable to promoting the holistic crystal quality of epitaxial wafer, the tensile stress in the AlN material can also be alleviated to the superlattice layer, avoid AlN material to produce the crackle owing to tensile stress is too big, further promote the holistic crystal quality of epitaxial wafer, make ultraviolet LED's luminous efficacy obtain promoting.
Illustratively, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 may be a flat substrate or a patterned substrate.
As an example, in the presently disclosed embodiment, the substrate 10 is a sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low. Specifically, the substrate can be a patterned sapphire substrate or a sapphire flat substrate.
Optionally, the thickness of the first high temperature AlN buffer layer 20 may be 100 nm-500 nm, where the thickness of the grown first high temperature AlN buffer layer 20 is different, and the quality of the finally formed epitaxial layer is also different, if the thickness of the first high temperature AlN buffer layer 20 is too thin, the surface of the first high temperature AlN buffer layer 20 is loose and rough, a good template cannot be provided for the growth of the subsequent structure, and as the thickness of the first high temperature AlN buffer layer 20 increases, the surface of the first high temperature AlN buffer layer 20 becomes gradually denser and flatter, which is beneficial to the growth of the subsequent structure, but if the thickness of the first high temperature AlN buffer layer 20 is too thick, the surface of the first high temperature AlN buffer layer 20 is too dense, which is also unfavorable for the growth of the subsequent structure, and lattice defects in the epitaxial layer cannot be reduced.
As an example, in the embodiment of the present disclosure, the thickness of the first high temperature AlN buffer layer 20 is 250nm.
Alternatively, the superlattice layer 30 may have a thickness of 100nm to 1000nm. The thickness of the superlattice layer 30 is too thin to block the extension of dislocation defects, the effect of improving the luminous efficiency of the ultraviolet LED is not obvious, the thickness of the superlattice layer 30 is too thick, which leads to an increase in resistance, and the absorption of light by the superlattice layer 30 is also increased, resulting in a decrease in luminous efficiency.
As an example, in the presently disclosed embodiment, the superlattice layer 30 has a thickness of 500nm.
Alternatively, the number of cycles in which AlN layers 31 and SiN layers 32 are alternately laminated is 20 to 40.
The dislocations extending from the first high temperature AlN buffer layer 20 are gradually bent by the AlN layer 31 and the SiN layer 32 in a plurality of cycles, annihilated with each other, and the quality of the crystal is gradually improved. The number of cycles for alternately stacking the AlN layers 31 and the SiN layers 32 is too small to obtain a crystal of good quality.
As an example, in the presently disclosed embodiment, the number of periods of the superlattice layer 30 is 30.
Note that fig. 1 shows only a partial structure of the superlattice layer 30, and is not intended to limit the number of cycles in which the AlN layer 31 and the SiN layer 32 are alternately stacked.
Alternatively, the AlN layer 31 has a thickness of 1nm to 100nm and the SiN layer 32 has a thickness of 1nm to 100nm.
As an example, in the presently disclosed embodiment, alN layer 31 has a thickness of 10nm, sin layer 32 has a thickness of 7nm, and sin layer 32 is too thin to reduce dislocation defects. The thickness of AlN layer 31 may be the same or different in different periods, and the thickness of SiN layer 32 may be the same or different. For example, the thickness of the SiN layer 32 gradually decreases.
Alternatively, the second high temperature AlN buffer layer 40 has a thickness of 1000nm to 2000nm.
As an example, in the presently disclosed embodiment, the thickness of the second high temperature AlN buffer layer 40 is 1500nm.
Alternatively, the thickness of the AlGaN transition layer 50 may be 50nm to 5000nm, and in the embodiments of the present disclosure, the thickness of the AlGaN transition layer 50 is 700nm.
Alternatively, the thickness of the n-type AlGaN layer 60 may be 600nm to 800nm, and in the embodiment of the present disclosure, the thickness of the n-type AlGaN layer 60 is 700nm.
Alternatively, the doping concentration of Si in the n-type AlGaN layer 60 is 10 17 cm -3 ～10 18 cm -3 . Too high a doping concentration of Si may reduce the crystal quality, resulting in an increase in defects, and too low a doping concentration of Si may reduce the conductivity of the n-type AlGaN layer 60. The doping concentration of Si is controlled to be 10 17 cm -3 ～10 18 cm -3 Can make the n-type AlGaN layer 60 have better crystal quality, as well asAnd also has sufficient conductivity.
As an example, in the embodiment of the present disclosure, the doping concentration of Si in the n-type AlGaN layer 60 is 5×10 17 cm -3 。
Optionally, the multiple quantum well layer 70 includes 3-8 Al x Ga 1-x N quantum well layer 71 and Al y Ga 1-y N quantum barrier 72, where 0 < x < y < 1. That is, the multiple quantum well layer 70 includes Al of 3 to 8 periods alternately laminated x Ga 1-x N quantum well layer 71 and Al y Ga 1-y N quantum barrier layer 72.
As an example, in the presently disclosed embodiment, the multiple quantum well layer 70 includes 5 periods of Al alternately stacked x Ga 1-x N quantum well layer 71 and Al y Ga 1-y N quantum barrier layer 72.
Alternatively, al x Ga 1-x The thickness of the N quantum well layer 71 may be 2nm to 4nm. Al (Al) y Ga 1-y The thickness of the N quantum barrier layer 72 may be 9 to 14nm.
Illustratively, in embodiments of the present disclosure, al x Ga 1-x The thickness of the N quantum well layer 71 is 3nm. Al (Al) y Ga 1-y The thickness of the N quantum barrier layer 72 is 11nm.
In fig. 1, only a part of the structure of the multiple quantum well layer 70 is shown, and Al is not limited thereto x Ga 1-x N quantum well layer 71 and Al y Ga 1-y The number of cycles in which the N quantum barrier layers 72 are alternately stacked may be such that Al is grown on the N-type AlGaN layer 60 first when the multi-quantum well layer 70 is grown y Ga 1-y N quantum barrier layer 72.
In the embodiment of the present disclosure, the p-type layer 80 includes a p-type barrier layer 81, a p-type AlGaN layer 82, and a p-type GaN layer 83 sequentially stacked on the multiple quantum well layer 70. The p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are all Mg doped.
Illustratively, the p-type barrier layer 81 is a p-type AlGaN barrier layer.
The thickness of the p-type AlGaN barrier layer may be 5nm to 15nm. As an example, in the embodiments of the present disclosure, the thickness of the p-type AlGaN barrier layer is 10nm. If the thickness of the p-type AlGaN barrier layer is too thin, the blocking effect on electrons is reduced, and if the thickness of the p-type AlGaN barrier layer is too thick, the absorption of light by the p-type AlGaN barrier layer is increased, thereby reducing the luminous efficiency of the LED.
In some examples, the thickness of the p-type AlGaN layer 82 is 20nm to 30nm. By way of example, in the presently disclosed embodiment, the p-type AlGaN layer 82 has a thickness of 25nm.
Alternatively, the thickness of the p-type GaN layer 83 may be 20nm to 70nm. As an example, in the presently disclosed embodiment, the thickness of the p-type GaN layer 83 is 50nm.
Fig. 2 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure. The method is used to manufacture the epitaxial wafer shown in fig. 1. As shown in fig. 2, the manufacturing method includes:
s11: a substrate 10 is provided.
S12: a first high temperature AlN buffer layer 20, a superlattice layer 30, a second high temperature AlN buffer layer 40, an AlGaN transition layer 50, an n-type AlGaN layer 60, a multiple quantum well layer 70, and a p-type layer 80 are epitaxially grown in this order on a substrate 10.
Wherein the superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked.
Through the surface lamination of the substrate sets up first high temperature AlN buffer layer, superlattice layer and second high temperature AlN buffer layer, the superlattice layer includes a plurality of AlN layers and a plurality of SiN layer of alternating lamination, and wherein the SiN layer can play the effect of stopping threading dislocation, and the dislocation bending that extends by first high temperature AlN buffer layer is gone up to alternating lamination AlN layer and SiN layer, increase the probability that dislocation annihilates each other, make in the direction of each layer lamination, the crystal quality of AlN is better and better, be favorable to promoting the holistic crystal quality of epitaxial wafer, the tensile stress in the AlN material can also be alleviated to the superlattice layer, avoid AlN material to produce the crackle owing to tensile stress is too big, further promote the holistic crystal quality of epitaxial wafer, make ultraviolet LED's luminous efficacy obtain promoting.
Fig. 3 is a flowchart of another method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present disclosure, which is used to manufacture the epitaxial wafer shown in fig. 1. The manufacturing method provided in fig. 3 is described in detail below with reference to fig. 4 to 12:
s21: a substrate 10 is provided.
Alternatively, the substrate 10 is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate 10 may be a flat substrate or a patterned substrate.
As an example, in the presently disclosed embodiment, the substrate 10 is a sapphire substrate. The sapphire substrate is a common substrate, the technology is mature, and the cost is low. Specifically, the substrate can be a patterned sapphire substrate or a sapphire flat substrate.
In step S21, the sapphire substrate may be pretreated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition; metal organic chemical vapor deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.
Specifically, the baking temperature can be 1000 ℃ to 1200 ℃, and the pressure in the MOCVD reaction chamber during baking can be 100mbar to 200mbar.
S22: a first high temperature AlN buffer layer 20 is epitaxially grown on the substrate 10.
As shown in fig. 4, a first high temperature AlN buffer layer 20 is grown on the substrate 10.
The thickness of the first high temperature AlN buffer layer 20 may be 100 nm-500 nm, the thicknesses of the grown first high temperature AlN buffer layers 20 are different, the quality of the finally formed epitaxial layer may also be different, if the thickness of the first high temperature AlN buffer layer 20 is too thin, the surface of the first high temperature AlN buffer layer 20 may be loose and rough, a good template may not be provided for the growth of the subsequent structure, and as the thickness of the first high temperature AlN buffer layer 20 increases, the surface of the first high temperature AlN buffer layer 20 becomes gradually denser and flatter, which is beneficial to the growth of the subsequent structure, but if the thickness of the first high temperature AlN buffer layer 20 is too thick, the surface of the first high temperature AlN buffer layer 20 may be too dense, which is also unfavorable for the growth of the subsequent structure, and lattice defects in the epitaxial layer may not be reduced.
Alternatively, the growth temperature of the first high temperature AlN buffer layer 20 is 1200-1300 ℃. As an example, in the embodiment of the present disclosure, the growth temperature of the first high temperature AlN buffer layer 20 is 1250 ℃.
Alternatively, the growth pressure of the first high temperature AlN buffer layer 20 is 30mbar to 70mbar. As an example, in the presently disclosed embodiment, the growth pressure of the first high temperature AlN buffer layer 20 is 50mbar.
S23: a superlattice layer 30 is grown on the first high temperature AlN buffer layer 20.
As shown in fig. 5, a superlattice layer 30 is grown on the first high temperature AlN buffer layer 20.
Wherein the superlattice layer 30 includes a plurality of AlN layers 31 and a plurality of SiN layers 32 alternately stacked. Alternatively, the number of cycles in which AlN layers 31 and SiN layers 32 are alternately laminated is 20 to 40. As an example, in the presently disclosed embodiment, the number of periods of the superlattice layer 30 is 30.
Note that fig. 5 shows only a partial structure of the superlattice layer 30, and is not intended to limit the number of cycles in which the AlN layer 31 and the SiN layer 32 are alternately stacked.
In the superlattice layer 30, the growth temperatures of the AlN layer 31 and the SiN layer 32 may be the same or different. As an example, in the embodiment of the present disclosure, the growth temperatures of the AlN layer 31 and the SiN layer 32 are the same, and the AlN layer 31 and the SiN layer 32 are alternately grown with the same growth temperature, which is more convenient to operate and simpler in process.
Alternatively, the superlattice layer 30 may be grown at a temperature of 1300 ℃ to 1400 ℃. By way of example, in the presently disclosed embodiment, the growth temperature of the superlattice layer 30 is 1350 ℃.
In the superlattice layer 30, the growth pressures of the AlN layer 31 and the SiN layer 32 may be the same or different. By way of example, in the embodiments of the present disclosure, the growth pressures of AlN layer 31 and SiN layer 32 are also the same, and AlN layer 31 and SiN layer 32 are alternately grown using the same growth pressure, which is more convenient to operate and simpler in process.
Alternatively, the growth pressure of the superlattice layer 30 is 30mbar to 70mbar. By way of example, in the presently disclosed embodiment, the growth pressure of the superlattice layer 30 is 50mbar.
In the embodiment of the disclosure, the superlattice layer 30 is obtained by periodically and alternately introducing TMAl and silane into the reaction chamber to grow 30 AlN layers 31 and 30 SiN layers 32.
Alternatively, the superlattice layer 30 may have a thickness of 100nm to 1000nm. As an example, in the presently disclosed embodiment, the superlattice layer 30 has a thickness of 500nm.
Alternatively, the AlN layer 31 has a thickness of 1nm to 100nm and the SiN layer 32 has a thickness of 1nm to 100nm. As an example, in the embodiment of the present disclosure, the thickness of AlN layer 31 is 10nm, and the thickness of sin layer 32 is 7nm.
S24: a second high temperature AlN buffer layer 40 is grown on the superlattice layer 30.
As shown in fig. 6, a second high temperature AlN buffer layer 40 is grown on the superlattice layer 30.
The growth temperature of the second high temperature AlN buffer layer 40 is higher than the growth temperature of the first high temperature AlN buffer layer 20 and the growth temperature of the superlattice layer 30.
Optionally, the growth temperature of the second high temperature AlN buffer layer 40 is 1300-1400 ℃.
As an example, in the embodiment of the present disclosure, the growth temperature of the second high temperature AlN buffer layer 40 is 1370 ℃.
Alternatively, the growth pressures of the first high temperature AlN buffer layer 20, the superlattice layer 30, and the second high temperature AlN buffer layer 40 are all the same. The first high-temperature AlN buffer layer 20, the superlattice layer 30, and the second high-temperature AlN buffer layer 40 are grown with the same growth pressure, and the process is simpler.
The second high temperature AlN buffer layer 40 is grown at a pressure of, illustratively, 30mbar to 70mbar. For example, in the presently disclosed embodiment, the second high temperature AlN buffer layer 40 is grown at a pressure of 50mbar.
In the embodiment of the present disclosure, the first high temperature AlN buffer layer 20, the superlattice layer 30, and the second high temperature AlN buffer layer 40 are grown with the same growth temperature, and the process is more convenient.
S25: an AlGaN transition layer 50 is grown on the second high temperature AlN buffer layer 40.
As shown in fig. 7, an AlGaN transition layer 50 is grown on the second high temperature AlN buffer layer 40.
Alternatively, the growth temperature of the AlGaN transition layer 50 is 1280℃to 1320 ℃.
As an example, in the presently disclosed embodiment, the growth temperature of AlGaN transition layer 50 is 1300 ℃.
Alternatively, the AlGaN transition layer 50 may be grown at a pressure of 120mbar to 180mbar. By way of example, in the presently disclosed embodiment, the AlGaN transition layer 50 is grown at a pressure of 150mbar.
Alternatively, the thickness of the AlGaN transition layer 50 may be 50nm to 5000nm, and in the embodiments of the present disclosure, the thickness of the AlGaN transition layer 50 is 700nm.
S26: an n-type AlGaN layer 60 is grown on the AlGaN transition layer 50.
As shown in fig. 8, an n-type AlGaN layer 60 is grown on the AlGaN transition layer 50.
Alternatively, the growth temperature of the n-type AlGaN layer 60 is 1000-1100 ℃. By way of example, in the presently disclosed embodiment, the growth temperature of the n-type AlGaN layer 60 is 1060 ℃.
Alternatively, the growth pressure of the n-type AlGaN layer 60 may be 80mbar to 110mbar. By way of example, in the presently disclosed embodiment, the n-type AlGaN layer 60 is grown at a pressure of 100mbar.
When the n-type AlGaN layer 60 is grown, silane doping is performed, and the Si doping concentration in the n-type AlGaN layer 60 may be 10 17 cm -3 ～10 18 cm -3 . As an example, in the presently disclosed embodiment, the Si doping concentration in the n-type AlGaN layer 60 is 5×10 17 cm -3 。
The thickness of the n-type AlGaN layer 60 may be 600nm to 800nm, and in the embodiment of the present disclosure, the thickness of the n-type AlGaN layer 60 is 700nm.
S27: a multiple quantum well layer 70 is grown on the n-type AlGaN layer 60.
As shown in fig. 9, a multiple quantum well layer 70 is grown on the n-type AlGaN layer 60.
In practice, the multiple quantum well layer 70 may include multiple layers of Al alternately stacked x Ga 1-x N quantum well layer 71 and multilayer Al y Ga 1-y N quantum barrier 72, where 0 < x < y < 1.
Alternatively, al x Ga 1-x N quantum well layer 71 and Al y Ga 1-y The number of periods in which the N quantum barrier layers 72 are alternately stacked may be3 to 8. Illustratively, in embodiments of the present disclosure, al x Ga 1-x N quantum well layer 71 and Al y Ga 1-y The number of cycles in which the N quantum barrier layers 72 are alternately stacked is 5.
In fig. 9, only a part of the structure of the multiple quantum well layer 70 is shown, and Al is not limited thereto x Ga 1-x N quantum well layer 71 and Al y Ga 1-y The number of cycles in which the N quantum barrier layers 72 are alternately stacked may be such that Al is grown on the N-type AlGaN layer 60 first when the multi-quantum well layer 70 is grown y Ga 1-y N quantum barrier layer 72.
Alternatively, al x Ga 1-x The thickness of the N quantum well layer 71 may be 2nm to 4nm. Al (Al) y Ga 1-y The thickness of the N quantum barrier layer 72 may be 9 to 14nm.
Illustratively, in embodiments of the present disclosure, al x Ga 1-x The thickness of the N quantum well layer 71 is 3nm. Al (Al) y Ga 1-y The thickness of the N quantum barrier layer 72 is 11nm.
After the multiple quantum well layer 70 is grown, a p-type layer 80 is grown on the multiple quantum well layer 70, and in the embodiment of the present disclosure, the p-type layer 80 includes a p-type barrier layer 81, a p-type AlGaN layer 82, and a p-type GaN layer 83 sequentially stacked on the multiple quantum well layer 70. The p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are all Mg doped. The growth of the p-type layer 80 includes the following steps S28 to S30.
S28: a p-type barrier layer 81 is grown on the multiple quantum well layer 70.
As shown in fig. 10, a p-type barrier layer 81 is grown on the multiple quantum well layer 70.
Alternatively, the p-type barrier layer 81 may be a p-type AlGaN barrier layer.
Specifically, the growth temperature of the p-type barrier layer 81 may be 960 ℃ to 990 ℃, and in the embodiment of the present disclosure, the growth temperature of the p-type barrier layer 81 is 980 ℃ as an example.
In particular, the growth pressure of the p-type barrier layer 81 may be 100mbar to 200mbar. By way of example, in the presently disclosed embodiment, the p-type barrier layer 81 is grown at a pressure of 150mbar.
Alternatively, the thickness of the p-type barrier layer 81 may be 5nm to 15nm. As an example, in the presently disclosed embodiment, the thickness of the p-type barrier layer 81 is 10nm. If the thickness of the p-type blocking layer 81 is too thin, blocking effect on electrons is reduced, and if the thickness of the p-type blocking layer 81 is too thick, absorption of light by the p-type blocking layer 81 is increased, resulting in a decrease in luminous efficiency of the LED.
S29: a p-type AlGaN layer 82 is grown on the p-type barrier layer 81.
As shown in fig. 11, a p-type AlGaN layer 82 is grown on the p-type barrier layer 81.
Specifically, the growth temperature of the p-type AlGaN layer 82 may be 880 ℃ to 920 ℃, and in the embodiment of the present disclosure, the growth temperature of the p-type AlGaN layer 82 is 900 ℃ by way of example.
Specifically, the growth pressure of the p-type AlGaN layer 82 may be 180mbar to 220mbar. By way of example, in the presently disclosed embodiment, the p-type AlGaN layer 82 is grown at a pressure of 200mbar.
Alternatively, the thickness of the p-type AlGaN layer 82 may be 20nm to 30nm. By way of example, in the presently disclosed embodiment, the p-type AlGaN layer 82 has a thickness of 25nm.
S30: a p-type GaN layer 83 is grown on the p-type AlGaN layer 82.
As shown in fig. 12, a p-type GaN layer 83 is grown on the p-type AlGaN layer 82.
Alternatively, the growth temperature of the p-type GaN layer 83 may be 800-900 ℃. As an example, in the presently disclosed embodiment, the growth temperature of the p-type GaN layer 83 is 850 ℃.
Alternatively, the growth pressure of the p-type GaN layer 83 may be 250mbar to 350mbar. As an example, in the presently disclosed embodiment, the growth pressure of the p-type GaN layer 83 is 300mbar.
Alternatively, the thickness of the p-type GaN layer 83 may be 20nm to 70nm. As an example, in the presently disclosed embodiment, the thickness of the p-type GaN layer 83 is 50nm.
Mg doping is performed using magnesium-dicyclopentadiene with trimethylgallium or triethylgallium as a gallium source when the p-type barrier layer 81, the p-type AlGaN layer 82, and the p-type GaN layer 83 are grown.
S31: and annealing the epitaxial wafer.
Alternatively, annealing may be performed under nitrogen division for 30 minutes to terminate the growth of the epitaxial wafer. And then the heating system and the gas supply system are closed, and the temperature of the reaction cavity is reduced to the room temperature.
And annealing the epitaxial wafer, and further carrying out subsequent processes on the epitaxial wafer to prepare the LED.
In particular implementations, embodiments of the present disclosure may employ high purity H 2 Or/and N 2 As a carrier gas, TEGa or TMGa as Ga source, TMIn as In source, siH 4 TMAL as an aluminum source, cp as an n-type dopant 2 Mg acts as a p-type dopant.
The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.
Claims (8)
1. The epitaxial wafer of the light-emitting diode is characterized by comprising a substrate (10) and a first high-temperature AlN buffer layer (20), a superlattice layer (30), a second high-temperature AlN buffer layer (40), an AlGaN transition layer (50), an n-type AlGaN layer (60), a multiple quantum well layer (70) and a p-type layer (80) which are sequentially formed on the substrate (10), wherein the superlattice layer (30) comprises a plurality of AlN layers (31) and a plurality of SiN layers (32) which are alternately stacked, the number of periods of the alternate stacking of the AlN layers (31) and the SiN layers (32) is 20-40, the thickness of the AlN layers (31) is 1-100 nm, the thickness of the SiN layers (32) is 1-100 nm, and the thickness of the superlattice layer (30) is 100-1000 nm.
2. Epitaxial wafer according to claim 1, characterized in that the thickness of the first high temperature AlN buffer layer (20) is 100nm to 500nm.
3. Epitaxial wafer according to claim 1, characterized in that the thickness of the second high temperature AlN buffer layer (40) is 1000nm to 2000nm.
4. The preparation method of the epitaxial wafer of the light-emitting diode is characterized by comprising the following steps of:
providing a substrate (10);
and sequentially epitaxially growing a first high-temperature AlN buffer layer (20), a superlattice layer (30), a second high-temperature AlN buffer layer (40), an AlGaN transition layer (50), an n-type AlGaN layer (60), a multiple quantum well layer (70) and a p-type layer (80) on the substrate (10), wherein the superlattice layer (30) comprises a plurality of AlN layers (31) and a plurality of SiN layers (32) which are alternately laminated, and the thickness of the superlattice layer (30) is 100-1000 nm.
5. The method according to claim 4, wherein the first high temperature AlN buffer layer (20) is grown at a temperature of 1200-1300 ℃ and a growth pressure of 30-70 mbar.
6. The method of manufacturing according to claim 4 or 5, characterized in that the growth temperature of the superlattice layer (30) is 1300-1400 ℃ and the growth pressure is 30-70 mbar.
7. The method according to claim 4 or 5, characterized in that the second high temperature AlN buffer layer (40) is grown at a temperature of 1300 ℃ to 1400 ℃ and at a pressure of 30mbar to 70mbar.
8. The method according to claim 4 or 5, wherein the growth pressure of the first high temperature AlN buffer layer (20), the superlattice layer (30), and the second high temperature AlN buffer layer (40) is the same.
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