CN115986018A - Epitaxial wafer, epitaxial wafer preparation method and light emitting diode - Google Patents
Epitaxial wafer, epitaxial wafer preparation method and light emitting diode Download PDFInfo
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Abstract
The invention provides an epitaxial wafer, a preparation method of the epitaxial wafer and a light-emitting diode, wherein the epitaxial wafer comprises: the quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer which are sequentially stacked; the first quantum barrier sublayer is an N-type InGaN layer, the second quantum barrier sublayer and the fourth quantum barrier sublayer are non-doped GaN layers, the third quantum barrier sublayer is a P-type AlInGaN layer, and the fifth quantum barrier sublayer is a P-type InGaN layer, the In component of the first quantum barrier sublayer gradually decreases from one end close to the quantum well layer to the other end, and the In component of the fifth quantum barrier sublayer gradually increases from one end close to the quantum well layer to the other end. The invention solves the problem of low luminous efficiency of the epitaxial wafer in the prior art due to the fact that the lattice mismatch of the quantum well layer and the quantum barrier layer is increased.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an epitaxial wafer, a preparation method of the epitaxial wafer and a light emitting diode.
Background
Group III nitride LEDs employ InGaN/GaN Multiple Quantum Wells (MQWS) as the active region, which theoretically can cover a wide spectral region from near-ultraviolet to near-infrared, making them very attractive for solid-state lighting. When InGaN quantum wells are grown on GaN barriers, according to theoretical calculation and experimental measurement, the polarization electric field of the InGaN well layer can reach MV/cm, so that the energy band of the quantum well region is inclined, and electrons and holes can cause serious spatial separation when passing through the quantum well region, so that the so-called Quantum Confinement Stark Effect (QCSE) is generated. Researchers at home and abroad are always actively exploring the internal physical cause of quantum confinement Stark effect, and a great deal of effective research work is done on the aspect, such as designing a novel multi-quantum well structure or optimizing the growth parameters of the quantum well. The thickness of the quantum barrier is one of the most important parameters in an InGaN/GaN multi-quantum well structure, a piezoelectric field in a quantum well can be changed, the transport and distribution state of carriers in an active region can be regulated and controlled, and the crystal quality of the active region is influenced.
The higher In composition In InGaN quantum wells results In an increased lattice mismatch with the GaN barrier, resulting In a large piezoelectric field In the InGaN quantum wells, resulting In the so-called Quantum Confined Stark Effect (QCSE). The QCSE effect reduces the degree of coupling between the electron and hole wave functions in the quantum well, thereby reducing the quantum efficiency within the LED and ultimately reducing the luminous efficiency of the LED.
Disclosure of Invention
Based on this, the invention aims to provide an epitaxial wafer, an epitaxial wafer preparation method and a light emitting diode, and aims to solve the problem that the epitaxial wafer in the prior art has low light emitting efficiency due to the fact that the lattice mismatch between a quantum well layer and a quantum barrier layer is increased.
The embodiment of the invention is realized as follows:
in one aspect, the invention provides an epitaxial wafer, which comprises a multiple quantum well layer, wherein the multiple quantum well layer comprises a quantum well layer and a quantum barrier layer which are alternately stacked, and the quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer which are sequentially stacked on the quantum well layer;
the first quantum barrier layer is an N-type InGaN layer, the second quantum barrier layer is a non-doped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer is a non-doped GaN layer, and the fifth quantum barrier layer is a P-type InGaN layer, the In component of the first quantum barrier layer is gradually reduced from one end close to the other end of the quantum well layer, and the In component of the fifth quantum barrier layer is gradually increased from one end close to the quantum well layer to the other end.
In addition, the epitaxial wafer provided by the invention at least has the following additional technical characteristics:
furthermore, the thickness of the first quantum barrier layer is 0.1 nm-2 nm, the thickness of the second quantum barrier layer is 0.5 nm-5 nm, the thickness of the third quantum barrier layer is 1 nm-20 nm, the thickness of the fourth quantum barrier layer is 0.5 nm-5 nm, and the thickness of the fifth quantum barrier layer is 0.1 nm-2 nm.
Further, the dopant of the first quantum barrier layer is Si, and the doping concentration of Si of the first quantum barrier layer is 5E +16atoms/cm 3 ~5E+17atoms/cm 3 ；
The dopants of the third quantum barrier layer and the fifth quantum barrier layer are both Mg, and the Mg doping concentration of the third quantum barrier layer is 1E +17atoms/cm 3 ~1E+18 atoms/cm 3 The Mg doping concentration of the fifth quantum barrier layer is 5E +16atoms/cm 3 ~5E+17atoms/cm 3 。
Further, the In component of the first quantum barrier layer is 0-0.3, the Al component of the third quantum barrier layer is 0-0.2, the In component is 0-0.1, and the In component of the fifth quantum barrier layer is 0-0.3.
Furthermore, the epitaxial wafer also comprises a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, an electron blocking layer and a P-type GaN layer;
the buffer layer, the non-doped GaN layer, the N-type GaN layer, the multi-quantum well layer, the electronic barrier layer and the P-type GaN layer are sequentially stacked on the substrate.
In another aspect, the present invention provides an epitaxial wafer preparation method for preparing the above-mentioned epitaxial wafer, including:
when the multiple quantum well layer grows, alternately growing the quantum well layer and the quantum barrier layer in sequence according to a preset period to obtain the multiple quantum well layer;
the quantum barrier layer is obtained by growing a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer on the quantum well layer In sequence, the first quantum barrier layer is an N-type InGaN layer, the second quantum barrier layer is a non-doped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer is a non-doped GaN layer and the fifth quantum barrier layer is a P-type InGaN layer, the In component of the first quantum barrier layer is gradually reduced from one end close to the quantum well layer to the other end, and the In component of the fifth quantum barrier layer is gradually increased from one end close to the quantum well layer to the other end.
Further, the above method for preparing an epitaxial wafer further comprises:
providing a substrate;
and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate.
Further, the preparation method of the epitaxial wafer comprises the following steps that the growth temperature of the first quantum barrier layer is 750-850 ℃, the growth temperature of the second quantum barrier layer is 850-950 ℃, the growth temperature of the third quantum barrier layer is 820-920 ℃, the growth temperature of the fourth quantum barrier layer is 800-900 ℃ and the growth temperature of the fifth quantum barrier layer is 750-850 ℃.
Further, the preparation method of the epitaxial wafer is characterized in that the growth pressure of the quantum barrier layer is 50-500 torr.
In another aspect, the invention further provides a light emitting diode, which includes the above epitaxial wafer.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
the quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer. The first quantum barrier layer is an N-type InGaN layer, the second quantum barrier layer is an undoped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer is an undoped GaN layer, and the fifth quantum barrier layer is a P-type InGaN layer. The first quantum barrier layer is gradually reduced along the epitaxial layer deposition direction, the In component of the fifth quantum barrier layer is gradually increased along the epitaxial layer direction, the lattice mismatch between an InGaN quantum well layer and a GaN quantum barrier layer is reduced, the crystal quality of a quantum well and the quantum barrier is improved, the piezoelectric polarization effect of an active layer is reduced, the coupling degree between electrons and hole wave functions In the quantum well is reduced through the QCSE effect, the quantum efficiency In the LED is reduced, the second quantum barrier layer is an undoped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer is an undoped GaN layer, the barrier height of the fourth quantum barrier layer is gradually increased, the overflow of the electrons to the P-type layer is reduced, and the luminous efficiency of the LED is finally improved.
Drawings
Fig. 1 is a schematic structural diagram of an epitaxial wafer according to an embodiment of the invention;
FIG. 2 is a flow chart of a method for fabricating an epitaxial wafer according to an embodiment of the invention;
the following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Several embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The embodiment of the invention provides an epitaxial wafer, a preparation method of the epitaxial wafer and a light emitting diode, aiming at the problem of low luminous efficiency caused by the increase of lattice mismatch of a quantum well layer and a quantum barrier layer in the epitaxial wafer, wherein:
referring to fig. 1, a schematic structural diagram of an epitaxial wafer according to an embodiment of the invention is shown, the epitaxial wafer including:
the GaN-based light emitting diode comprises a substrate 100, and a buffer layer 200, an undoped GaN layer 300, an N-type GaN layer 400, a multi-quantum well layer 500, an electron blocking layer 600 and a P-type GaN layer 700 which are sequentially stacked on the substrate 100.
The multiple quantum well layer 500 comprises quantum well layers 510 and quantum barrier layers 520 which are alternately stacked, the quantum barrier layers 520 comprise a first quantum barrier layer 521, a second quantum barrier layer 522, a third quantum barrier layer 523, a fourth quantum barrier layer 524 and a fifth quantum barrier layer 525 which are sequentially stacked on the quantum well layer 510, specifically, the first quantum barrier layer 521 is an N-type InGaN layer, the second quantum barrier layer 522 is an undoped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer 524 is an undoped GaN layer and the fifth quantum barrier layer 525 is a P-type InGaN layer, the In component of the first quantum barrier layer 521 gradually decreases from one end close to the quantum well layer 510 to the other end, and the In component of the fifth quantum barrier layer 525 gradually increases from one end close to the quantum well layer 510 to the other end.
It is understood that the InGaN well layer is almost completely strained in the a-axis direction by the GaN lamination stress, and thus a strong piezoelectric polarization field is generated. Therefore, the In component of the first quantum barrier layer 521 is gradually decreased from one end close to the quantum well layer 510 to the other end (along the epitaxial layer deposition direction), while the In component of the fifth quantum barrier layer 525 is gradually increased from one end close to the quantum well layer 510 to the other end (along the epitaxial layer direction), so that the lattice mismatch between the InGaN quantum well layer 510 and the GaN quantum barrier layer 520 is reduced, the crystal quality of the quantum well and the quantum barrier is improved, the piezoelectric polarization effect of the quantum well layer 510 of the multiple quantum well layer 500 is reduced, the stark effect (QCSE) is reduced, the degree of coupling between electron and hole wave functions In the quantum well is ensured, the internal quantum efficiency of the LED is ensured, the second quantum barrier layer 522 is an undoped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer 524 is an undoped GaN layer, the barrier height of the second quantum barrier layer is gradually increased, the overflow of electrons to the P layer is reduced, and the light emitting efficiency of the LED is finally improved.
Specifically, the thickness of the first quantum barrier layer 521 is 0.1 nm-2 nm, the thickness of the second quantum barrier layer 522 is 0.5 nm-5 nm, the thickness of the third quantum barrier layer 523 is 1 nm-20 nm, the thickness of the fourth quantum barrier layer 524 is 0.5 nm-5 nm, and the thickness of the fifth quantum barrier layer 525 is 0.1 nm-2 nm; the appropriate thickness of the quantum barrier layer 520 can promote the injection of holes into the light-emitting wells, and the quantum barrier layer 520 corresponding to the light-emitting wells can enhance the interaction of carriers among the light-emitting wells, improve the carrier utilization rate and further improve the external quantum efficiency of the device.
More specifically, the dopant of the first quantum barrier layer 521 is Si, and the doping concentration of Si of the first quantum barrier layer 521 is 5E +16atoms/cm 3 ~5E+17atoms/cm 3 The dopants of the third quantum barrier layer 523 and the fifth quantum barrier layer 525 are both Mg, and the Mg doping concentration of the third quantum barrier layer 523 is 1E +17atoms/cm 3 ~1E+18 atoms/cm 3 The Mg doping concentration of the fifth quantum barrier layer 525 is 5E +16atoms/cm 3 ~5E+17atoms/cm 3 . The electric field of the quantum barrier layer 520 is directed from P to N, and the movement of the hole to the N pole is promoted.
Illustratively, the substrate 100 may be sapphire substrate, siO 2 The electron blocking layer 600 may be one of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate, the buffer layer 200 may be an AlN/GaN layer, and the electron blocking layer 600 may be an AlInGaN layer.
Referring to fig. 2, in another aspect, the method for preparing an epitaxial wafer according to the embodiment of the present invention is used for preparing the above-mentioned epitaxial wafer, and the method for preparing an epitaxial wafer includes steps S10 to S11.
Step S10, a substrate is provided.
Wherein the substrate can be sapphire substrate or SiO 2 One of a sapphire composite substrate, a silicon carbide substrate, a gallium nitride substrate and a zinc oxide substrate.
And S11, growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate in sequence.
When the multiple quantum well layer grows, the quantum well layer and the quantum barrier layer alternately grow in sequence according to a preset period to obtain the multiple quantum well layer;
and sequentially growing a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer on the quantum well layer to obtain the quantum barrier layer.
Specifically, the growth temperature of the first quantum barrier layer is 750-850 ℃, the growth temperature is gradually increased, the temperature rise rate is 10-150 ℃/min, the growth temperature of the second quantum barrier layer is 850-950 ℃, the growth temperature of the third quantum barrier layer is 820-920 ℃, the growth temperature of the fourth quantum barrier layer is 800-900 ℃, the growth temperature of the fifth quantum barrier layer is 750-850 ℃, the growth temperature is gradually decreased, and the temperature decrease rate is 10-150 ℃/min. The temperature is increased, the crystal quality of the quantum barrier layer is improved, the temperature close to the quantum well layer is low, and the crystal quality of the quantum well layer is guaranteed.
In specific implementation, the growth atmosphere of the first quantum barrier layer/quantum barrier layer is N 2 /NH 3 And the ratio is 1The growth atmosphere of the quantum barrier layer/the fourth quantum barrier layer is N 2 /H 2 /NH 3 And the ratio is 1. Wherein the atmosphere near the quantum well layer growth is free of H 2 Avoid the introduction of H 2 Leading InGaN of the quantum well layer to be decomposed, and introducing proper proportion H into growth atmosphere of the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer 2 And the crystal quality of the quantum barrier layer is improved.
Furthermore, the growth pressure of the quantum barrier layer ranges from 50torr to 500torr, wherein the growth pressure of the quantum barrier layer ensures two-dimensional growth of the quantum barrier layer, the crystal quality of the quantum barrier layer is improved, the growth cycle number ranges from 1 to 20, and electrons and holes are localized in the multi-quantum well layer, so that the overlapping of wave functions of the electrons and the holes is improved, and the radiative recombination rate is further improved.
Illustratively, an AlN/GaN buffer layer is deposited on the substrate to a thickness of 10nm to 50 nm.
Specifically, an AlN buffer layer is deposited in an application material PVD (physical vapor deposition), the thickness of the AlN buffer layer is 15nm, the AlN buffer layer is adopted to control crystal defects, the quality of subsequent growing crystals is improved, and stress caused by lattice mismatch and thermal mismatch between a substrate and an epitaxial layer is relieved.
Pretreating the sapphire substrate with the deposited buffer layer, specifically transferring the sapphire substrate plated with the AlN buffer layer into MOCVD, and performing chemical vapor deposition (H) 2 Pretreating for 1-10 min in the atmosphere at 1000-1200 ℃, and then nitriding the sapphire substrate, so that the crystal quality of the AlN buffer layer is improved, and the crystal quality of the post-deposition GaN epitaxial layer can be effectively improved.
And depositing an undoped GaN layer on the buffer layer, wherein the growth temperature of the undoped GaN layer is 1050-1200 ℃, the pressure is 100-600 torr, and the thickness is 1-5 um.
Specifically, the growth temperature of the non-doped GaN layer is 1100 ℃, the growth pressure is 150 torr, the growth thickness is 2 um-3 um, the growth temperature of the non-doped GaN layer is higher, the pressure is lower, the crystal quality of the prepared GaN is better, meanwhile, the thickness is increased along with the thickness of the GaN, the compressive stress can be released through stacking faults, line defects are reduced, the crystal quality is improved, reverse leakage is reduced, but the consumption of the thickness of the GaN layer on Ga source materials is higher, the epitaxial cost of the LED is greatly improved, therefore, the growth thickness of the non-doped GaN layer is preferably 2 um-3 um, the production cost is saved, and the GaN material has higher crystal quality.
Depositing an n-type GaN layer on the undoped GaN layer, wherein the growth temperature of the n-type GaN layer is 1050-1200 ℃, the pressure is 100-600 torr, the thickness is 2-3 um, the doping concentration of Si is 1E19-5E19 atoms/cm 3 。
Specifically, the growth temperature of the n-type GaN layer is 1120 ℃, the growth pressure is 100torr, the growth thickness is 2 um-3 um, the Si doping concentration is 2.5E19 atoms/cm 3 Firstly, the n-type GaN layer provides sufficient electrons for the LED to emit light, secondly, the resistivity of the n-type GaN layer is higher than that of the transparent electrode on the p-GaN, so that sufficient Si doping can effectively reduce the resistivity of the n-type GaN layer, and finally, the sufficient thickness of the n-type GaN layer can effectively release the light emitting efficiency of the stress light emitting diode.
Optionally, the electron blocking layer is an AlInGaN layer, the thickness is 10 nm-40 nm, the growth temperature is 900 ℃ -1000 ℃, the pressure is 100 torr-300 torr, wherein, the Al component is more than 0.005 and less than 0.1, and the in component concentration is more than 0.01 and less than 0.2.
Specifically, the thickness of the electron blocking layer is 15nm of AlInGaN, the concentration of an Al component gradually changes to 0.05 along the growth direction of the epitaxial layer, the concentration of an in component is 0.01, the growth temperature is 965 ℃, the growth pressure is 200torr, electron overflow can be effectively limited, blocking of holes can be reduced, the injection efficiency of the holes to a quantum well is improved, carrier auger recombination is reduced, and the light emitting efficiency of the light emitting diode is improved.
Depositing a P type GaN layer on the electronic barrier layer, optionally, growing the P type GaN layer at 900-1050 ℃, the thickness of the P type GaN layer being 10nm-50nm, the growth pressure being 100torr-600 torr, and the Mg doping concentration being 1E +, 19-1E +, 21atoms/cm 3 。
Specifically, the growth temperature of the P-type GaN layer is 985 ℃, the thickness is 15nm, the growth pressure is 200torr, and the Mg doping concentration is 2E +20atoms/cm 3 Too high a doping concentration of Mg will deteriorate the crystal quality, while lower doping concentrations will affect the hole concentration. At the same time, for the pit containing V-shapeFor the LED structure, the higher growth temperature of the P-type GaN layer is also beneficial to combining the V-shaped pits, and the LED epitaxial wafer with a smooth surface is obtained.
In this embodiment, medium-micro A7 MOCVD (Metal-organic Chemical Vapor Deposition, MOCVD for short) equipment is used to obtain high-purity H 2 (Hydrogen gas), high purity N 2 (Nitrogen), high purity H 2 And high purity N 2 One of the mixed gases of (1) is used as a carrier gas, high-purity NH is added 3 As the N source, trimethylgallium (TMGa) and triethylgallium (TEGa) as the gallium source, trimethylindium (TMIn) as the indium source, trimethylaluminum (TMAl) as the aluminum source, silane (SiH) 4 ) As N-type dopant, magnesium dicocene (CP) 2 Mg) as a P-type dopant.
On the other hand, the light emitting diode provided by the embodiment of the invention comprises the epitaxial wafer.
In order that the invention may be more fully understood, reference will now be made to the accompanying examples. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Example 1
Providing a substrate;
growing an AlN layer on the substrate in the PVD equipment;
growing an undoped GaN layer, an n-type doped GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type doped GaN layer in sequence in MOCVD equipment;
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.E 0 +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 2
Embodiment 2 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.3/1.7/5/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.E 0 +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 3
Embodiment 3 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.7/0.3, the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component of the first quantum barrier layer/the fifth quantum barrier layer is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.0E +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 4
Embodiment 4 of the present invention also provides a method for manufacturing an epitaxial wafer, where the method for manufacturing an epitaxial wafer in this embodiment is different from the method for manufacturing an epitaxial wafer in embodiment 1 in that:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.15, the In component is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping of the first quantum barrier layer is carried outThe concentration is 1.0E +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 5
Embodiment 5 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component is reduced to 0/0 and is increased to 0.1, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.E 0 +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 6
Embodiment 6 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is reduced to 0.2 and is increased to 0.2 from 0/0, the Al component/the In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.0E +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 7
Embodiment 7 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thicknesses of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is reduced to 0.2 and increased to 0.2 from 0/0, the Al component/In component of the third quantum barrier layer is 0.1/0.1, and the Si doping concentration of the first quantum barrier layer is 1.0E +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 8
Embodiment 8 of the present invention also provides an epitaxial wafer manufacturing method, where the difference between the epitaxial wafer manufacturing method in this embodiment and the epitaxial wafer manufacturing method in embodiment 1 is:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 2.5E +00 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/the fifth quantum barrier layer is 6.5E +17/1.5E +17 (atoms/cm) 3 ）。
Example 9
Embodiment 9 of the present invention also provides a method for manufacturing an epitaxial wafer, where the method for manufacturing an epitaxial wafer in this embodiment is different from the method for manufacturing an epitaxial wafer in embodiment 1 in that:
wherein the thickness of the first quantum barrier layer/the second quantum barrier layer/the third quantum barrier layer/the fourth quantum barrier layer/the fifth quantum barrier layer is 0.5/1.5/6/1.5/0.5 (nm), the In component of the first quantum barrier layer/the fifth quantum barrier layer is 0.2, the In component is reduced to 0/0 and is increased to 0.2, the Al component/In component of the third quantum barrier layer is 0.1/0.05, and the Si doping concentration of the first quantum barrier layer is 1.E 0 +17 (atoms/cm) 3 ) Mg doping concentration of the third quantum barrier layer/fifth quantum barrier layer is 5E +17/1E +17 (atoms/cm) 3 ）。
For comparison with the above examples of the present invention, the following comparative examples are also proposed in the examples of the present invention.
Comparative example 1
The first comparative example of the present invention also provides a method for preparing an epitaxial wafer, which is different from the first embodiment in that:
the quantum barrier layer is a conventional GaN layer with the growth thickness of 10 nm.
Please refer to table 1 below, which shows the parameters and performance improvement of the present invention according to the above examples 1 to 9 and comparative example 1.
TABLE 1
It should be noted that, in order to ensure the reliability of the verification result, the above examples 1 to 9 and comparative example 1 of the present invention should have the same epitaxial wafer, except for the above parameters, for example, the preparation process and parameters of each layer of the epitaxial wafer should be kept consistent, and the growth temperature, growth pressure, and H of the quantum barrier layer should be kept consistent 2 Flow rate (L/min), N 2 Flow rate (L/min), NH 3 Flow rate (L/min).
It is obvious from the combination of embodiment 1 and embodiment 2 that a proper quantum well thickness can promote the injection of holes into the light-emitting well, and the quantum barrier corresponding to the light-emitting well can enhance the interaction of carriers between the light-emitting wells, thereby improving the carrier utilization rate and further improving the external quantum efficiency of the device.
It is obvious from the combination of the embodiment 4 and the embodiment 5 that the reasonably arranged In component of the first quantum barrier layer is gradually reduced along the epitaxial layer deposition direction/the In component of the fifth quantum barrier layer is gradually increased along the epitaxial layer direction, so that the lattice mismatch between the InGaN quantum well layer and the GaN quantum barrier layer is reduced, the crystal quality of the quantum well and the quantum barrier is improved, and the piezoelectric polarization effect of the active layer is reduced.
It can be seen from the combination of embodiment 7 and embodiment 8 that the potential barrier height is gradually increased due to the reasonable doping concentration, the overflow of electrons to the P layer is reduced, the electric field of the quantum barrier layer is directed to N from P, the movement of holes to the N pole is promoted, and the light emitting efficiency is further improved.
Referring to table 2, shown are corresponding performance data of another 9 sets of epitaxial wafers prepared by the preparation method in an embodiment of the present invention, in which the growth temperature, growth atmosphere, and the like of the quantum barrier layer are mainly changed.
TABLE 2
It should be noted that, in order to ensure the reliability of the verification result, the above examples 1 to 6 and the comparative example 1 of the present invention should have the same epitaxial wafer, except for the above parameters, for example, the preparation process and parameters of each layer of the epitaxial wafer should be kept consistent, and the In composition and the doping concentration of the quantum barrier layer should also be kept consistent.
In addition, the combination of the test data shows that the growth temperature is gradually reduced firstly, the temperature is increased later, the crystal quality of the quantum barrier layer is improved, the temperature close to the quantum well layer is lower, and the crystal quality of the quantum well is ensured. Reasonable growth atmosphere proportion is set, and the growth atmosphere close to the quantum well layer has no H 2 Avoid the introduction of H 2 Leading to decomposition of quantum well InGaN and improving the crystal quality of the quantum barrier layer. The growth pressure of the quantum barrier layer is low, the two-dimensional growth of the quantum barrier is guaranteed, and the crystal quality of the quantum barrier layer is improved. And finally, the luminous efficiency is improved.
In comparative example 1, a higher In composition In the InGaN quantum well may increase the lattice mismatch with the GaN barrier, resulting In a large piezoelectric field In the InGaN quantum well, thereby generating a so-called Quantum Confined Stark Effect (QCSE). The QCSE effect reduces the degree of coupling between the electron and hole wave functions in the quantum well, thereby reducing the quantum efficiency within the LED and ultimately reducing the luminous efficiency of the LED.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An epitaxial wafer comprises a multi-quantum well layer, wherein the multi-quantum well layer comprises quantum well layers and quantum barrier layers which are alternately stacked, and the quantum barrier layers comprise a first quantum barrier layer, a second quantum barrier layer, a third quantum barrier layer, a fourth quantum barrier layer and a fifth quantum barrier layer which are sequentially stacked on the quantum well layer;
the first quantum barrier layer is an N-type InGaN layer, the second quantum barrier layer is a non-doped GaN layer, the third quantum barrier layer is a P-type AlInGaN layer, the fourth quantum barrier layer is a non-doped GaN layer, and the fifth quantum barrier layer is a P-type InGaN layer, the In component of the first quantum barrier layer is gradually reduced from one end close to the other end of the quantum well layer, and the In component of the fifth quantum barrier layer is gradually increased from one end close to the quantum well layer to the other end.
2. The epitaxial wafer of claim 1, wherein the first quantum barrier layer has a thickness of 0.1nm to 2nm, the second quantum barrier layer has a thickness of 0.5nm to 5nm, the third quantum barrier layer has a thickness of 1nm to 20nm, the fourth quantum barrier layer has a thickness of 0.5nm to 5nm, and the fifth quantum barrier layer has a thickness of 0.1nm to 2nm.
3. The epitaxial wafer of claim 1, wherein the dopant of the first quantum barrier layer is Si, and the Si doping concentration of the first quantum barrier layer is 5e + 1691ms/cm 3 ~5E+17atoms/cm 3 ；
The dopants of the third quantum barrier layer and the fifth quantum barrier layer are both Mg, and the Mg doping concentration of the third quantum barrier layer is 1E +17atoms/cm 3 ~1E+18 atoms/cm 3 The Mg doping concentration of the fifth quantum barrier layer is 5E +16atoms/cm 3 ~5E+17atoms/cm 3 。
4. The epitaxial wafer of claim 1, wherein the In component of the first quantum barrier layer is 0to 0.3, the Al component of the third quantum barrier layer is 0to 0.2, the In component is 0to 0.1, and the In component of the fifth quantum barrier layer is 0to 0.3.
5. The epitaxial wafer according to any one of claims 1 to 4, further comprising a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, an electron blocking layer and a P-type GaN layer;
the buffer layer, the non-doped GaN layer, the N-type GaN layer, the multi-quantum well layer, the electronic barrier layer and the P-type GaN layer are sequentially stacked on the substrate.
6. An epitaxial wafer preparation method for preparing an epitaxial wafer according to any one of claims 1 to 5, comprising:
when the multiple quantum well layer grows, alternately growing the quantum well layer and the quantum barrier layer in sequence according to a preset period to obtain the multiple quantum well layer;
wherein, grow first quantum barrier layer, second quantum barrier layer, third quantum barrier layer, fourth quantum barrier layer and fifth quantum barrier layer In proper order on the quantum well layer In order to obtain the quantum barrier layer, first quantum barrier layer is N type InGaN layer, second quantum barrier layer for not mixing the GaN layer, third quantum barrier layer for P type AlInGaN layer, fourth quantum barrier layer for not mixing the GaN layer and fifth quantum barrier layer for P type InGaN layer, the In component of first quantum barrier layer is by being close to one end of quantum well layer reduces gradually to the other end, the In component of fifth quantum barrier layer is by being close to one end of quantum well layer risees gradually to the other end.
7. The method for preparing an epitaxial wafer according to claim 6, further comprising:
providing a substrate;
and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electronic barrier layer and a P-type GaN layer on the substrate.
8. The method for preparing the epitaxial wafer of claim 6, wherein the growth temperature of the first quantum barrier layer is 750 ℃ to 850 ℃, the growth temperature of the second quantum barrier layer is 850 ℃ to 950 ℃, the growth temperature of the third quantum barrier layer is 820 ℃ to 920 ℃, the growth temperature of the fourth quantum barrier layer is 800 ℃ to 900 ℃ and the growth temperature of the fifth quantum barrier layer is 750 ℃ to 850 ℃.
9. The method of manufacturing an epitaxial wafer according to claim 6, wherein the growth pressure of the quantum barrier layer is 50torr to 500torr.
10. A light-emitting diode comprising an epitaxial wafer according to any one of claims 1 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314496A (en) * | 2023-05-19 | 2023-06-23 | 江西兆驰半导体有限公司 | High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED |
| CN117174793A (en) * | 2023-10-31 | 2023-12-05 | 江西兆驰半导体有限公司 | Blue-green light LED epitaxial wafer, preparation method thereof and LED chip |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10107320A (en) * | 1996-10-02 | 1998-04-24 | Toyoda Gosei Co Ltd | Light-emitting element of iii group nitride semiconductor and manufacture thereof |
| CN106057990A (en) * | 2016-06-28 | 2016-10-26 | 华灿光电(苏州）有限公司 | Method for manufacturing epitaxial wafer of GaN-based light emitting diode |
| CN106057989A (en) * | 2016-06-22 | 2016-10-26 | 华灿光电(苏州）有限公司 | Manufacturing method for epitaxial wafer of GaN-based light-emitting diode |
| CN109950368A (en) * | 2019-02-18 | 2019-06-28 | 华灿光电(苏州）有限公司 | Gallium nitride based LED epitaxial slice and its manufacturing method |
| CN110718612A (en) * | 2019-08-30 | 2020-01-21 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and manufacturing method thereof |
| US20200052155A1 (en) * | 2017-04-18 | 2020-02-13 | Xiamen San'an Optoelectronics Co., Ltd. | Multi-quantum well structure and led device including the same |
| US20210210654A1 (en) * | 2017-07-31 | 2021-07-08 | Xiamen San'an Optoelectronics Co., Ltd. | Semiconductor light emitting device |
| CN114038972A (en) * | 2022-01-10 | 2022-02-11 | 江西兆驰半导体有限公司 | LED epitaxial wafer, epitaxial growth method and LED chip |
| CN114725257A (en) * | 2022-04-08 | 2022-07-08 | 江西兆驰半导体有限公司 | GaN-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode |
| CN115050870A (en) * | 2022-08-12 | 2022-09-13 | 江西兆驰半导体有限公司 | GaN-based light emitting diode epitaxial wafer and preparation method thereof |
-
2023
- 2023-03-20 CN CN202310266386.XA patent/CN115986018B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10107320A (en) * | 1996-10-02 | 1998-04-24 | Toyoda Gosei Co Ltd | Light-emitting element of iii group nitride semiconductor and manufacture thereof |
| CN106057989A (en) * | 2016-06-22 | 2016-10-26 | 华灿光电(苏州）有限公司 | Manufacturing method for epitaxial wafer of GaN-based light-emitting diode |
| CN106057990A (en) * | 2016-06-28 | 2016-10-26 | 华灿光电(苏州）有限公司 | Method for manufacturing epitaxial wafer of GaN-based light emitting diode |
| US20200052155A1 (en) * | 2017-04-18 | 2020-02-13 | Xiamen San'an Optoelectronics Co., Ltd. | Multi-quantum well structure and led device including the same |
| US20210210654A1 (en) * | 2017-07-31 | 2021-07-08 | Xiamen San'an Optoelectronics Co., Ltd. | Semiconductor light emitting device |
| CN109950368A (en) * | 2019-02-18 | 2019-06-28 | 华灿光电(苏州）有限公司 | Gallium nitride based LED epitaxial slice and its manufacturing method |
| CN110718612A (en) * | 2019-08-30 | 2020-01-21 | 华灿光电（浙江）有限公司 | Light emitting diode epitaxial wafer and manufacturing method thereof |
| CN114038972A (en) * | 2022-01-10 | 2022-02-11 | 江西兆驰半导体有限公司 | LED epitaxial wafer, epitaxial growth method and LED chip |
| CN114725257A (en) * | 2022-04-08 | 2022-07-08 | 江西兆驰半导体有限公司 | GaN-based light emitting diode epitaxial wafer, preparation method thereof and light emitting diode |
| CN115050870A (en) * | 2022-08-12 | 2022-09-13 | 江西兆驰半导体有限公司 | GaN-based light emitting diode epitaxial wafer and preparation method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116314496A (en) * | 2023-05-19 | 2023-06-23 | 江西兆驰半导体有限公司 | High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED |
| CN116314496B (en) * | 2023-05-19 | 2023-07-21 | 江西兆驰半导体有限公司 | High-light-efficiency light-emitting diode epitaxial wafer, preparation method thereof and LED |
| CN117174793A (en) * | 2023-10-31 | 2023-12-05 | 江西兆驰半导体有限公司 | Blue-green light LED epitaxial wafer, preparation method thereof and LED chip |
| CN117174793B (en) * | 2023-10-31 | 2024-01-26 | 江西兆驰半导体有限公司 | Blue-green light LED epitaxial wafer, preparation method thereof and LED chip |
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|---|---|
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