CN104938040A - 内置有零件的基板及其制造方法 - Google Patents
内置有零件的基板及其制造方法 Download PDFInfo
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- CN104938040A CN104938040A CN201380070770.7A CN201380070770A CN104938040A CN 104938040 A CN104938040 A CN 104938040A CN 201380070770 A CN201380070770 A CN 201380070770A CN 104938040 A CN104938040 A CN 104938040A
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- 239000000758 substrate Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 81
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000011521 glass Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000012212 insulator Substances 0.000 claims description 71
- 230000004888 barrier function Effects 0.000 claims description 30
- 238000003475 lamination Methods 0.000 claims description 29
- 239000007788 liquid Substances 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000002844 melting Methods 0.000 claims description 12
- 230000008018 melting Effects 0.000 claims description 12
- 230000007261 regionalization Effects 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 238000003825 pressing Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000004744 fabric Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 5
- 238000007747 plating Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 239000007767 bonding agent Substances 0.000 description 5
- 238000007665 sagging Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 208000037656 Respiratory Sounds Diseases 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011120 plywood Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005201 scrubbing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000009941 weaving Methods 0.000 description 1
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
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- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
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- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/82009—Pre-treatment of the connector or the bonding area
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- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- Y10T156/10—Methods of surface bonding and/or assembly therefor
Abstract
内置有零件的基板(20)包括:包含绝缘树脂材料的绝缘层(12);埋设在绝缘层(12)中的电气或电子的零件(4);作为零件(4)所具有的电极的端子(15);形成在绝缘层(12)的表面上的导体图案(18);以及将导体图案(18)和端子(15)电连接的导通通路(21),导通通路(21)从导体图案(18)朝向端子(15)由大径的大径部(21a)和比该大径部(21a)小径的小径部(21b)形成,在大径部(21a)与小径部(21b)之间形成有台阶部(17),大径部(21a)通过将配置在绝缘层(12)内的片状的玻璃丝网(11)贯穿而形成。
Description
技术领域
本发明涉及一种内置有零件的基板(日文:部品内蔵基板)及其制造方法。
背景技术
在专利文献1中记载了一种内置有零件的基板。如专利文献1所记载的,通过将电气或电子的零件装载在要成为导体图案的导电层上,并将该导电层埋设在预浸料(日文:プリプレグ)等的绝缘层中,来形成内置有零件的基板。当埋设零件时,使零件穿过该零件部分被挖空的开孔预浸料(日文:孔あきプリプレグ)和开孔芯材(日文:孔あきコア材)的孔,将没有形成孔的盖式预浸料层叠在上述孔的上部来进行冲压。在进行层叠后,形成到达至零件所具有的电极端子的孔、即通路(日文:ビア),并对该通路的内部进行镀覆,或是不形成通路而通过焊锡来实现端子与导体图案的导通。
该通路的形成一般采用利用CO2激光进行加工的方法。在激光加工中,时,常根据需要设定动力、脉冲宽度及压射数等。
另一方面,当希望在零件的两面(上下面)实现导通的情况下,还在相反侧的面上形成到达零件端子的通路。此外,对该通路实施镀覆处理来实现零件端子与导体图案的导通。
现有技术文献
专利文献
专利文献1:日本专利特许第4874305号公报
发明内容
发明所要解决的技术问题
但是,零件的上侧存在盖式预浸料,该盖式预浸料如上所述从层叠褶皱及平坦性、或是强度的观点考虑,而没有形成供零件穿过的孔。因而,在形成通路时,需要使存在于盖式预浸料内的玻璃丝网贯穿。在进行层叠时,由于在盖式预浸料与零件正面之间设置有空间,因此,盖式预浸料在该部分处下垂,玻璃丝网也相应地靠近零件正面。在用于使上述玻璃丝网贯穿的激光加工中,很难进行玻璃丝网的控制,若玻璃丝网与零件的距离较近,则存在损坏零件本身的可能性。
本发明是考虑到上述现有技术而作,其目的在于提供一种即使在形成有供玻璃丝网贯穿的通路的情况下,也不会在通路的形成加工时使零件受到损伤的内置有零件的基板及其制造方法。
解决技术问题所采用的技术方案
为了实现上述目的,在本发明中,提供一种内置有零件的基板,其特征是,包括:绝缘层,上述绝缘层包含绝缘树脂材料;电气或电子的零件,电气或电子的上述零件埋设在该绝缘层中;端子,上述端子作为上述零件所具有的电极;导体图案,上述导体图案形成在上述绝缘层的表面上;以及导通通路,上述导通通路将上述导体图案和上述端子电连接,上述导通通路从上述导体图案朝向上述端子由大径的大径部和比该大径部小径的小径部形成,在上述大径部与上述小径部之间形成有台阶部,上述大径部通过将配置在上述绝缘层内的片状的玻璃丝网贯穿而形成。
另外,在本发明中,提供一种内置有零件的基板的制造方法,其特征是,包括:装载工序,在上述装载工序中,将金属膜粘贴在具有刚性的支承板上,并将电气或电子的零件装载在上述金属膜上;敷层工序,在上述敷层工序中,使上述零件穿过预先形成有供上述零件贯穿的通孔的开孔绝缘体的上述通孔中,并将内置有片状的玻璃丝网的无孔绝缘体配置在封闭上述通孔的位置处;层叠工序,在上述层叠工序中,通过将上述开孔绝缘体及上述无孔绝缘体相互按压并加热来形成绝缘层,并将上述零件埋设在上述绝缘层内;通路形成工序,在上述通路形成工序中,形成从上述绝缘层的外侧到达上述零件所具有的端子的通路;以及图案形成工序,在上述图案形成工序中,在上述绝缘层的表面形成导体图案,且在上述通路内填充用于将上述导体图案和上述端子电连接的导电体,来形成导通通路,
在上述敷层工序中,由具有流动性的流动体及具有刚性的刚性体来形成上述开孔绝缘体,上述流动体的厚度为上述开孔绝缘体的厚度的30%~90%,在上述通路形成工序中,当形成了供上述玻璃丝网贯穿的大径的大径通路后,在上述大径通路中形成台阶部,并且形成到达上述端子的、比上述大径通路小径的小径通路。
理想的是,在上述通路形成工序中,利用玻璃蚀刻处理将突出到上述通路内的上述玻璃丝网去除。
理想的是,在上述敷层工序中,采用上述无孔绝缘体的熔融开始温度与上述开孔绝缘体的熔融开始温度相同或比上述开孔绝缘体的熔融开始温度高的材料。
理想的是,将上述玻璃丝网的位置控制在上述开孔绝缘体及上述无孔的绝缘体的厚度的40%~90%之间。
理想的是,在上述图案形成工序之后,还进行外侧层叠工序,在上述外侧层叠工序中,从上述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,在上述外侧层叠工序中,将施加到由上述大径通路及上述小径通路构成的上述导通通路的每一个上的压力设为50gf以下。
理想的是,在上述图案形成工序之后,还进行外侧层叠工序,在上述外侧层叠工序中,从上述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,上述大径通路及上述小径通路的厚度为上述多层基板的厚度的15%以下。
理想的是,在上述图案形成工序之后,还进行外侧层叠工序,在上述外侧层叠工序中,从上述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,将上述小径通路所到达的上述端子的厚度设为12μm以上。
发明效果
根据本发明,在导通通路中设置大径部和小径部,大径部供玻璃丝网贯穿。这种大径部和小径部在形成通路时形成作为大径通路及小径通路。因而,能分别在最佳的条件下进行用于贯穿玻璃丝网的开孔加工和用于到达端子的开孔加工。通过在上述大径通路与小径通路之间设置台阶部,能够防止玻璃丝网突出到通路内(特别是小径通路内)。因而,当在形成导通通路时实施镀覆处理的时候,能使镀覆物可靠地附着在通路内壁的整个面上。
另一方面,若将流动体的厚度设为开孔绝缘体的厚度的30%~90%,则在层叠工序中,流动体首先进入到通孔内,因此,能够防止无孔绝缘体下垂到通孔内。因而,能防止在层叠工序中玻璃丝网靠近零件,并能在远离零件的位置处进行将玻璃丝网贯穿的加工。因此,能防止在通路形成加工时零件受到损伤。
另外,通过用玻璃蚀刻处理将突出到通路内的玻璃丝网去除,从而能够进一步使镀覆物向通路内的附着变得可靠。
另外,通过采用使无孔绝缘体的熔融开始温度与开孔绝缘体的熔融开始温度相同或比开孔绝缘体的熔融开始温度高的材料,从而能在层叠工序中可靠地使开孔绝缘体最先在通孔内流动。因此,能够防止无孔绝缘体下垂。
附图说明
图1是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图2是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图3是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图4是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图5是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图6是按顺序对本发明的内置有零件的基板的制造方法进行说明的示意图。
图7是对通路形成工序进行说明的细节图。
图8是对通路形成工序进行说明的细节图。
图9是表示多层基板的例子的示意图。
具体实施方式
首先,对本发明的内置有零件的基板的制造方法进行说明。
如图1及图2所示,进行装载工序。首先,如图1所示,将金属膜2粘贴在具有刚性的支承板1上。金属膜2是随后要成为导电图案的构件。支承板1采用具有在工艺条件中所需程度的刚性的板。例如,由具有刚性的SUS(不锈钢)板或铝板等形成。当支承板1为SUS板时,能够通过使镀铜析出来形成金属膜2,当支承板1为铝板时,能够通过粘贴铜箔来形成金属膜2。接着,如图2所示,通过例如分配器或印刷等方式将由绝缘材料构成的粘接剂3涂覆在金属膜2上。将电气或电子的零件4装载在上述粘接剂3上。另外,也可以采用焊锡在金属膜2上进行零件4的装载。在本例中,在零件4的两个面上形成有作为电极的端子5、15。
接着,如图3所示,进行敷层工序(日文:レイアップ工程)。首先准备开孔绝缘体6。通过将具有流动性的流动体7及具有刚性的刚性体8重叠来形成上述开孔绝缘体6。流动体7是预浸料。刚性体8是所谓的芯材(无包壳材料(日文:アンクラッド(unclad)材)),其由作为芯放入在多层印刷线路板内部的金属板或是形成有图案的层叠板形成。在上述流动体7和刚性体8中形成有供零件4插通的通孔9。使用钻头、刳刨机(日文:ルータ)和模具等形成上述通孔9。在图3中,示出了将一片刚性体8夹在两片流动体7中而层叠形成的开孔绝缘体6。将零件4插通到该开孔绝缘体6的通孔9中。接着,将无孔绝缘体10再层叠在上述开孔绝缘体6上,以封闭上述通孔9。上述无孔绝缘体10也是预浸料。由于是预浸料,因此,在无孔绝缘体10中内置有片状的玻璃丝网11。玻璃丝网11是用玻璃纤维的丝织成的布。另外,在无孔绝缘体10的与零件4相反一侧的面上配置有另一金属膜13。该金属膜13也成为导体图案。另外,流动体7的厚度设定为开孔绝缘体6的厚度的30%~90%。
接着,如图4所示,进行层叠工序。该层叠工序是将开孔绝缘体6及无孔绝缘体10相互按压加热,从而形成绝缘层12,并将零件4埋设在该绝缘层12内的工序。通过加热使由预浸料构成的无孔绝缘体10和流动体7一边流动一边成为一体,进入到通孔9内。此时,由于存在刚性体8,因此在进行了按压时,能够适当地埋设零件4。另外,在上述敷层工序中,若使用无孔绝缘体10的熔融开始温度比开孔绝缘体6(特别是流动体7)的熔融开始温度高的材料,则能够可靠地使流动体7先在通孔9内流动而防止无孔绝缘体10的下垂。随后去除支承板1。此时,将玻璃丝网11的位置控制在开孔绝缘体6及无孔绝缘体10的厚度的40%~90%之间。
在完成层叠工序后,使配置在无孔的绝缘体10内的玻璃丝网11保持与金属膜2和刚性体8平行的状态。即,即使因加热而使无孔的绝缘体10发生熔融,玻璃丝网11也不会下垂到通孔9内。这是由于在上述敷层工序中,将流动体7的厚度设定为开孔绝缘体6的厚度的30%~90%。另外,将流动体7的厚度上限设为90%是考虑到刚性体8的厚度至少为无孔绝缘体10的10%以上。通过这样设定,在层叠工序中,流动体7首先进入到通孔9内。进入到该通孔9内的流动体7对无孔绝缘体10进行支承,防止包含玻璃丝网11的无孔绝缘体10下垂。因此,能在层叠工序中防止玻璃丝网11靠近零件4。藉此,能在接下来的通路形成工序中形成供玻璃丝网11贯通的大径通路14a时,在远离零件4的位置处进行开孔加工。因而,能防止在进行通路形成加工时零件受到损伤。理想的是,玻璃丝网11最好与零件4分开30μm~70μm以上。发明人通过实验确认当将流动体7的厚度设定为小于开孔绝缘体6的厚度的30%时,无孔绝缘体10进而是玻璃丝网11会发生下垂。
接着,如图5所示,进行通路形成工序。该工序是形成从绝缘层12的外侧到达零件4所具有的端子5、15的通路14、16的工序。利用通常的激光加工来形成到达至粘接剂3侧的端子5的通路16。到达与粘接剂3相反一侧的端子15间的通路14是通过如下方式形成的。首先,如图7所示,形成将玻璃丝网11贯穿且未到达至零件4的大径的大径通路14a。该大径通路14a不怎么需要加工深度的精度,因此,也可以利用CO2激光来形成,但是也可以使用UV-YAG或受激准分子(日文:エキシマ(excimer))等高频激光。例如在使用UV-YAG的情况下,在射束模式为高斯模式(日文:ガウシアン)、功率为2.6W,压射数为三次的条件下进行。大径通路14a的深度例如为50μm~100μm。
在形成大径通路14a后,在玻璃丝网11突出到大径通路14a内的情况下,理想的是利用玻璃蚀刻处理来去除该玻璃丝网11。藉此,能在后续工序中对通路14内实施镀覆处理时,使镀覆物向通路14内的附着变得可靠。
接着,如图8所示,形成比大径通路14a小径的小径通路14b。在形成该小径通路14b时,为了不损伤零件4,理想的是使用精度高的高频激光。例如在利用UV-YAG进行的情况下,在射束模式为缩顶模式(日文:トップハット)、功率为0.1W~0.4W、压射数为五次~十次的条件下进行。此外,大径通路14a和小径通路14b的内壁隔着台阶部17形成。通过这样在大径通路14a与小径通路14b之间设置台阶部17,即使例如因形成大径通路14a而使玻璃丝网11位于台阶部17的面上,也能防止玻璃丝网11突出到通路14内(特别是小径通路14b内)。因此,能在后续工序中对通路14内实施镀覆处理时,使镀覆物可靠地附着在通路14的内壁的整个面上。大径通路14a的孔径例如为80μm~150μm,小径通路14b的孔径处于比大径通路14a小的范围内,为50μm~100μm。
这样,在本发明中,当在零件4的与装载侧的面相反一侧的面上实现导通的情况下,利用隔着台阶部17的大径通路14a和小径通路14b来形成上述通路14。因而,能分别在最佳的条件下进行用于将玻璃丝网11贯穿的开孔加工(大径通路14a的开孔加工)和用于到达端子15的开孔加工(小径通路14b的开孔加工)。
接着,如图6所示,进行图案形成工序。该工序是在将导电体19填充到通路14、16内,在绝缘层12的表面形成导体图案18,并利用导电体19将端子5、15与导体图案18电连接的工序。详细而言,根据需要对通路14、16实施除污(日文:デスミア)或半蚀刻处理来进行化学镀铜或电镀铜等镀覆处理,使镀覆物析出在通路14、16内并将导电体19填充到通路14、16内。接着,通过对配置在绝缘层12的两个面的金属膜2、13进行蚀刻处理,来形成导体图案18。
如上所述制成的内置有零件的基板20包括绝缘层12、零件4、导体图案18和导通通路21。绝缘层12包含作为绝缘树脂材料的预浸料(开孔绝缘体6内的流动体和无孔绝缘体10)。零件4是电气或电子的零件,并埋设在绝缘层12中。另外,零件4可以是从动零件,也可以是主动零件。在该零件4上形成有作为电极的端子5、15。在绝缘层12的表面形成有导体图案18来作为电路图案。导通通路21将导体图案18与端子5、15电连接。特别是,连接到零件4的与装载面侧相反一侧的端子15上的导通通路21从导体图案18朝向端子15由大径的大径部21a和比该大径部21a小径的小径部21b形成。大径部21a通过将配置在绝缘层12内的片状的玻璃丝网11贯穿而形成。此外,在大径部21a与小径部21b之间形成有台阶部17。
如图9所示,也可以在进行图案形成工序后,接着进行从外侧将外侧绝缘体22层叠的外侧层叠工序,来形成所谓的多层基板25。在这种情况下,在层叠了外侧绝缘体22后形成通路23,来实现导体图案18与形成在外侧绝缘体22的表面的导体图案24的导通。通过对形成在导体图案18与导体图案24之间的通路23实施电镀处理来形成导通通路26,从而能够实现上述导通。这种导通的实现方式与上述的例子相同。外侧绝缘体22与上述无孔绝缘体10同样地使用预浸料。
在此,理想的是,在外侧层叠工序中,将施加到由大径通路14a和小径通路14b构成的导通通路21的每一个上的压力设为50gf以下。另外,理想的是,大径通路14a及小径通路14b的厚度为多层基板25的厚度的15%以下。另外,理想的是,将小径通路14b所到达的端子15的厚度设为12μm以上(多层基板的厚度400μm)。
通过这样设定,能防止在形成多层基板25时的外侧层叠工序中,在端子15处产生裂纹。发明人确认通过减小施加到由大径通路14a及小径通路14b构成的导通通路21上的压力,便能够防止这种裂纹。因而,可以考虑降低层叠时的压力、或提高通路密度、或增大通路直径、或形成为没有填充导电体19的通路来缓和应力。另外,也可以考虑通过减小通路14的厚度来实现应力的分散。另外,还可以考虑通过增加端子15的电极厚度来使应力分散。
(符号说明)
1 支承板
2 金属膜
3 粘接剂
4 电气或电子的零件
5 端子
6 开孔绝缘体
7 流动体
8 刚性体
9 通孔
10 无孔绝缘体
11 玻璃丝网
12 绝缘层
13 金属膜
14 通路
14a 大径通路
14b 小径通路
15 端子
16 通路
17 台阶部
18 导体图案
19 导电体
20 内置有零件的基板
21 导通通路
21a 大径部
21b 小径部
22 外侧绝缘体
23 通路
24 导体图案
25 多层基板
26 导通通路。
Claims (8)
1.一种内置有零件的基板,其特征在于,包括:
绝缘层,所述绝缘层包含绝缘树脂材料;
电气或电子的零件,电气或电子的所述零件埋设在所述绝缘层中;
端子,所述端子作为所述零件所具有的电极;
导体图案,所述导体图案形成在所述绝缘层的表面上;以及
导通通路,所述导通通路将所述导体图案和所述端子电连接,
所述导通通路从所述导体图案朝向所述端子由大径的大径部和比该大径部小径的小径部形成,
在所述大径部与所述小径部之间形成有台阶部,
所述大径部通过将配置在所述绝缘层内的片状的玻璃丝网贯穿而形成。
2.一种内置有零件的基板的制造方法,其特征在于,包括:
装载工序,在所述装载工序中,将金属膜粘贴在具有刚性的支承板上,并将电气或电子的零件装载在所述金属膜上;
敷层工序,在所述敷层工序中,使所述零件穿过预先形成有供所述零件贯穿的通孔的开孔绝缘体的所述通孔中,并将内置有片状的玻璃丝网的无孔绝缘体配置在封闭所述通孔的位置处;
层叠工序,在所述层叠工序中,通过将所述开孔绝缘体及所述无孔绝缘体相互按压并加热来形成绝缘层,并将所述零件埋设在所述绝缘层内;
通路形成工序,在所述通路形成工序中,形成从所述绝缘层的外侧到达所述零件所具有的端子的通路;以及
图案形成工序,在所述图案形成工序中,在所述绝缘层的表面形成导体图案,且在所述通路内填充用于将所述导体图案和所述端子电连接的导电体,来形成导通通路,
在所述敷层工序中,由具有流动性的流动体及具有刚性的刚性体来形成所述开孔绝缘体,所述流动体的厚度为所述开孔绝缘体的厚度的30%~90%,
在所述通路形成工序中,当形成了供所述玻璃丝网贯穿的大径的大径通路后,在所述大径通路中形成台阶部,并且形成到达所述端子的、比所述大径通路小径的小径通路。
3.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
在所述通路形成工序中,利用玻璃蚀刻处理将突出到所述通路内的所述玻璃丝网去除。
4.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
在所述敷层工序中,采用所述无孔绝缘体的熔融开始温度与所述开孔绝缘体的熔融开始温度相同或是比所述开孔绝缘体的熔融开始温度高的材料。
5.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
将所述玻璃丝网的位置控制在所述开孔绝缘体及所述无孔绝缘体的厚度的40%~90%之间。
6.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
在所述图案形成工序之后,还进行外侧层叠工序,在所述外侧层叠工序中,从所述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,
在所述外侧层叠工序中,将施加到由所述大径通路及所述小径通路构成的所述导通通路的每一个上的压力设为50gf以下。
7.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
在所述图案形成工序之后,还进行外侧层叠工序,在所述外侧层叠工序中,从所述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,
所述大径通路及所述小径通路的厚度为所述多层基板的厚度的15%以下。
8.如权利要求2所述的内置有零件的基板的制造方法,其特征在于,
在所述图案形成工序之后,还进行外侧层叠工序,在所述外侧层叠工序中,从所述导体图案的外侧将由绝缘树脂材料构成的外侧绝缘体按压并层叠,来形成多层基板,
将所述小径通路所到达的所述端子的厚度设为12μm以上。
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JP2016058472A (ja) * | 2014-09-08 | 2016-04-21 | イビデン株式会社 | 電子部品内蔵配線板及びその製造方法 |
CN107295746B (zh) | 2016-03-31 | 2021-06-15 | 奥特斯(中国)有限公司 | 器件载体及其制造方法 |
EP3481162B1 (en) * | 2017-11-06 | 2023-09-06 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with two component carrier portions and a component being embedded in a blind opening of one of the component carrier portions |
WO2021146894A1 (zh) * | 2020-01-21 | 2021-07-29 | 鹏鼎控股(深圳)股份有限公司 | 内埋电子元件的电路板及制作方法 |
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