CN104882488B - 薄膜晶体管、阵列基板及其制作方法、显示装置 - Google Patents

薄膜晶体管、阵列基板及其制作方法、显示装置 Download PDF

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CN104882488B
CN104882488B CN201510332661.9A CN201510332661A CN104882488B CN 104882488 B CN104882488 B CN 104882488B CN 201510332661 A CN201510332661 A CN 201510332661A CN 104882488 B CN104882488 B CN 104882488B
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drain electrode
source
semiconductor layer
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diffusion inhibiting
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CN104882488A (zh
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韩俊号
尹炳坤
马骏
张敏
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Hefei Xinsheng Optoelectronics Technology Co Ltd
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Abstract

本发明的实施例提供一种薄膜晶体管、阵列基板及其制作方法、显示装置，涉及电子技术领域，可降低有源层与源漏极之间形成的欧姆接触电阻。该方法包括：在形成源漏极的步骤与形成非晶硅半导体层的步骤之间，还包括：形成扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向所述半导体层扩散的能力；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层。该方法可应用于薄膜晶体管的制作工艺中。

Description

薄膜晶体管、阵列基板及其制作方法、显示装置
技术领域
本发明涉及电子技术领域，尤其涉及薄膜晶体管、阵列基板及其制作方法、显示装置。
背景技术
在液晶显示领域，TFT(Thin Film Transistor，薄膜晶体管)开态电流的大小(即向栅极施加电压使有源层导通时的电流值)对TFT性能具有重大意义，而TFT开态电流的大小于TFT导通时的阻值即开态电阻Ron成反比。
现有技术中，通常采用背沟道刻蚀底栅结构制作阵列基板，其TFT的开态电阻可以由图1所示的模型描述，即：
Ron＝2*RΩ+2*RV+RC，
其中，Ron是TFT的开态电阻，RΩ是有源层01与源极02或漏极03之间形成的欧姆接触电阻，RV是有源层01形成的纵向电阻，RC是TFT导通后形成的沟道电阻。可以看出，通过降低RΩ、RV或RC可以有效降低开态电阻Ron。
目前，为了获得足够大的开态电流，通常通过增加TFT的沟道宽长比(即W/L)的方式降低沟道电阻RC，进而降低开态电阻Ron。但是，当TFT的沟道宽长比大于一定门限值后，显示器的开口率(即有效的透光区域与全部面积的比例)会随之减小，进而增加显示器能耗。
发明内容
本发明的实施例提供一种薄膜晶体管、阵列基板及其制作方法、显示装置，可降低有源层与源漏极之间形成的欧姆接触电阻。
为达到上述目的，本发明的实施例采用如下技术方案：
一方面，本发明的实施例提供一种薄膜晶体管的制作方法，包括：在衬底基板上形成源漏极、以及半导体层，其中，所述源漏极内包含有具备扩散能力的金属原子；所述半导体层的材料为非晶硅；在形成所述源漏极的步骤与形成所述非晶硅半导体层的步骤之间，所述方法还包括：
形成扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向所述半导体层扩散的能力；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层。
进一步地，所述金属原子为铜原子。
进一步地，所述扩散抑制层的材料包含氮化钽、氮化钛、氮化钼、氮氧化硅或氧化硅中的至少一种。
进一步地，在形成所述扩散抑制层之后，还包括：
对形成有所述源漏极、所述扩散抑制层以及所述半导体层的衬底基板进行退火工艺，以加速从所述扩散抑制层扩散出的金属原子与所述半导体层内的非晶硅反应，生成含有金属硅化物的金属过渡层。
进一步地，所述对形成有所述源漏极、所述扩散抑制层以及所述半导体层的衬底基板进行退火工艺，包括：
在200℃至450℃之间的任意温度下进行所述退火工艺。
进一步地，在衬底基板上形成所述源漏极的步骤、形成所述半导体层的步骤和形成所述扩散抑制层的步骤的顺序依次为：
在所述衬底基板上依次形成源漏极；
形成覆盖所述源漏极的扩散抑制层；
在所述扩散抑制层上，形成所述半导体层。
另一方面，本发明的实施例提供了一种阵列基板的制作方法，包括上述任一项所述的薄膜晶体管的制作方法。
另一方面，本发明的实施例提供了一种薄膜晶体管，包括：
衬底基板；
设置在所述衬底基板上的源漏极，所述源漏极内包含有具备扩散能力的金属原子；
设置在所述源漏极上的扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向后续形成的半导体层扩散的能力；
设置在所述扩散抑制层上的半导体层，所述半导体层的材料为非晶硅；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层。
另一方面，本发明的实施例提供了一种阵列基板，包括上述薄膜晶体管。
另一方面，本发明的实施例提供了一种显示装置，包括上述阵列基板。
本发明的实施例提供一种薄膜晶体管、阵列基板及其制作方法、显示装置，在形成源漏极的步骤与形成半导体层的步骤之间，形成用于降低源漏极内金属原子向半导体层扩散的能力的扩散抑制层，这样一来，使得从扩散抑制层扩散出的金属原子与半导体层内的非晶硅接触并发生反应，在扩散抑制层和半导体层的交界处生成含有金属硅化物的金属过渡层，由于金属硅化物的电阻率较低，因此，可以有效降低TFT中半导体层与源漏极之间形成的欧姆接触电阻，进而可在保证显示器开口率的同时降低TFT的开态电阻，提高TFT的开态电流。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中TFT的开态电阻模型；
图2为本发明的实施例提供一种阵列基板的制作方法的流程示意图一；
图3为本发明的实施例提供一种阵列基板的结构示意图一；
图4为本发明的实施例提供一种阵列基板的结构示意图二；
图5为本发明的实施例提供一种阵列基板的结构示意图三；
图6为本发明的实施例提供一种阵列基板的结构示意图四；
图7为本发明的实施例提供的TFT的开态电阻模型；
图8为本发明的实施例提供一种阵列基板的制作方法的流程示意图二。
具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、接口、技术之类的具体细节，以便透彻理解本发明。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中，省略对众所周知的装置、电路以及方法的详细说明，以免不必要的细节妨碍本发明的描述。
本发明的实施例提供一种薄膜晶体管的制作方法，包括：在衬底基板上形成源漏极、以及半导体层。
其中，所述源漏极内包含有具备扩散能力的金属原子；所述半导体层的材料为非晶硅。
进一步地，在形成所述源漏极的步骤与形成所述半导体层的步骤之间，所述方法还包括：
形成扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向所述半导体层扩散的能力；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层。
这样，在扩散抑制层和半导体层中靠近源漏极的交界处生成含有金属硅化物的金属过渡层，由于金属硅化物的电阻率较低，因此，可以有效降低TFT中半导体层与源漏极之间形成的欧姆接触电阻，进而可在保证显示器开口率的同时降低TFT的开态电阻，提高TFT的开态电流。
需要说明的是，本发明实施例对在衬底基板上形成源漏极的步骤、形成半导体层的步骤和形成扩散抑制层的步骤的顺序不做限制，具体的，本发明实施例给出以下两种可行的实现方案。
方案一，可以在衬底基板上形成栅极和栅绝缘层后，先在栅绝缘层上形成该半导体层，进而在该半导体层上形成该扩散抑制层，最后在该扩散抑制层上形成源漏极。
方案二，可以在衬底基板上形成栅极和栅绝缘层后，先在栅绝缘层上形成源漏极，进而在该源漏极和栅绝缘层上形成该扩散抑制层，最后在该扩散抑制层上形成该半导体层。
示例性的，如图2所示，以下以方案二为例详细阐述该薄膜晶体管的制作方法，所述制作方法具体包括：
101、在衬底基板上分别形成栅极和栅绝缘层。
具体的，如图3所示，在衬底基板10上分别形成栅极11和位于栅极11之上的栅绝缘层12。
102、在该栅绝缘层上形成源漏极，该源漏极内包含有具备扩散能力的金属原子。
具体的，如图4所示，通过一次构图工艺在该栅绝缘层12上形成源极13和漏极14。
其中，金属铜由于具有良好的导热性能以及较低的电阻率，因此被认为是比较理想的连接材料，同时，铜具有显著的扩散效应，即铜原子在大多数介质中具有极高的扩散速率，为了避免源极和漏极中的铜原子过度扩散至后续形成的有源层，形成较大的欧姆接触电阻，可进一步的执行步骤103。
103、在形成有上述结构的衬底基板上分别形成扩散抑制层和半导体层。
其中，该半导体层的材料为非晶硅；该扩散抑制层用于降低源漏极内金属原子向半导体层扩散的能力。
具体的，该扩散抑制层的材料中可以包含氮化钽、氮化钛、氮化钼、氮氧化硅或氧化硅等氮化物中的至少一种。
具体的，如图5所示，在形成有图4结构的衬底基板10上分别形成扩散抑制层15和半导体层16，以源极13和漏极14中包含有铜原子为例，由于铜原子的扩散能力较强，因此，扩散抑制层15仅能阻挡一部分铜原子进行扩散，而从扩散抑制层扩散出的其他金属原子，可以与半导体层16内靠近源极13和漏极14的非晶硅接触并反应，如图6所示，此时可以在散抑制层15和半导体层16的交界面内生成含有金属硅化物(例如Cu3Si等)的金属过渡层17，此时，半导体层16中的一部分为该金属过渡层17，而该半导体层16中的另一部分可以作为TFT中的有源层。
这样，由于金属硅化物与硅晶体附着力好，且电阻率低，因此，金属过渡层17中的金属硅化物可以起到较为理想的降低欧姆接触电阻的作用。
需要说明的是，由于扩散抑制层15对源极13和漏极14内的铜原子的阻挡作用，只能在与源极13和漏极14对应的扩散抑制层15与半导体层16接触的位置生成的金属过渡层17。
如图7所示，为本发明提供的TFT开态电阻的模型示意图，其中，金属过渡层17与半导体层16接触形成欧姆接触电阻RΩ，TFT导通后形成的沟道电阻RC，即TFT的开态电阻Ron＝2*RΩ+RC，相比于图1所示的现有技术中TFT的开态电阻Ron的模型而言，可以有效减少欧姆接触电阻RΩ，同时省略了有源层形成的纵向电阻RV，进而减小TFT的开态电阻，提高TFT的开态电流。
另在，如图8所示，在步骤103之后，还可以执行步骤104，具体的步骤104如下：
104、对步骤103中形成的衬底基板进行退火工艺。
其中，退火工艺指示将金属加热到一定温度，保持足够时间，然后以适宜速度冷却(通常是缓慢冷却，有时是控制冷却)的一种金属热处理工艺。
为了使金属原子，例如铜原子的扩散速度加快，可以在200℃至450℃之间的任意温度下，对如图5所示的基站进行退火工艺，加速从扩散抑制层15扩散出的铜原子与半导体层16内的非晶硅反应，生成含有金属硅化物的金属过渡层17。
至此，本发明的实施例提供一种薄膜晶体管的制作方法，在形成源漏极的步骤与形成半导体层的步骤之间，形成用于降低源漏极内金属原子向半导体层扩散的能力的扩散抑制层，这样一来，使得从扩散抑制层扩散出的金属原子与半导体层内的非晶硅接触并发生反应，在扩散抑制层和半导体层的交界处生成含有金属硅化物的金属过渡层，由于金属硅化物的电阻率较低，因此，可以有效降低TFT中半导体层与源漏极之间形成的欧姆接触电阻，进而可在保证显示器开口率的同时降低TFT的开态电阻，提高TFT的开态电流。
相应的，本发明的实施例还提供一种薄膜晶体管，如图6所示，包括：
衬底基板10；
设置在所述衬底基板10上的源极13和漏极14，所述源极13和漏极14内包含有具备扩散能力的金属原子；
设置在所述源极13和漏极14上的扩散抑制层15，所述扩散抑制层15用于降低源极13和漏极14内金属原子向后续形成的半导体层16扩散的能力；
设置在所述扩散抑制层15上的半导体层16，所述半导体层16的材料为非晶硅；使得从所述扩散抑制层15扩散出的金属原子，与所述半导体层16中靠近源极13和漏极14的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层17。
当然，该薄膜晶体管中还可以进一步包括栅极、栅绝缘层等，本领域技术人员可根据实际情况采用最合理的设置方式，本发明实施例对此不作任何限制。
例如，可以在衬底基板10上先设置半导体层16，进而在半导体层16上设置扩散抑制层15，最后在扩散抑制层15上设置源极13和漏极14，该方案也可以使得从扩散抑制层15扩散出的金属原子，与半导体层16中靠近源极13和漏极14的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层17。
进一步地，本发明实施例还提供一种阵列基板的制作方法，该方法包括步骤101至104中至少一项薄膜晶体管的制作方法。
相应的，本发明实施例还提供一种阵列基板，该阵列基板包括上述的薄膜晶体管。
进一步地，本发明实施例还提供了一种显示装置，该显示装置包括上述的阵列基板。其中，所述显示装置可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本发明的实施例提供一种薄膜晶体管、阵列基板及其制作方法、显示装置，在形成源漏极的步骤与形成半导体层的步骤之间，形成用于降低源漏极内金属原子向半导体层扩散的能力的扩散抑制层，这样一来，使得从扩散抑制层扩散出的金属原子与半导体层内的非晶硅接触并发生反应，在扩散抑制层和半导体层的交界处生成含有金属硅化物的金属过渡层，由于金属硅化物的电阻率较低，因此，可以有效降低TFT中半导体层与源漏极之间形成的欧姆接触电阻，进而可在保证显示器开口率的同时降低TFT的开态电阻，提高TFT的开态电流。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

1.一种薄膜晶体管的制作方法，包括：在衬底基板上形成源漏极、以及半导体层，其特征在于，其中，所述源漏极内包含有具备扩散能力的金属原子；所述半导体层的材料为非晶硅；在形成所述源漏极的步骤与形成所述半导体层的步骤之间，所述方法还包括：
形成扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向所述半导体层扩散的能力；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层；
在衬底基板上形成所述源漏极的步骤、形成所述半导体层的步骤和形成所述扩散抑制层的步骤的顺序依次为：
在所述衬底基板上依次形成源漏极；
形成覆盖所述源漏极的扩散抑制层；
在所述扩散抑制层上，形成所述半导体层。
2.根据权利要求1所述的制作方法，其特征在于，所述金属原子为铜原子。
3.根据权利要求2所述的制作方法，其特征在于，所述扩散抑制层的材料包含氮化钽、氮化钛、氮化钼、氮氧化硅或氧化硅中的至少一种。
4.根据权利要求1至3中任一项所述的制作方法，其特征在于，在形成所述扩散抑制层之后，还包括：
对形成有所述源漏极、所述扩散抑制层以及所述半导体层的衬底基板进行退火工艺，以加速从所述扩散抑制层扩散出的金属原子与所述半导体层内的非晶硅反应，生成含有金属硅化物的金属过渡层。
5.根据权利要求4所述的制作方法，其特征在于，所述对形成有所述源漏极、所述扩散抑制层以及所述半导体层的衬底基板进行退火工艺，包括：
在200℃至450℃之间的任意温度下进行所述退火工艺。
6.一种阵列基板的制作方法，其特征在于，包括：权利要求1-5中任一项所述的薄膜晶体管的制作方法。
7.一种薄膜晶体管，其特征在于，包括：
衬底基板；
设置在所述衬底基板上的源漏极，所述源漏极内包含有具备扩散能力的金属原子；
设置在所述源漏极上的扩散抑制层，所述扩散抑制层用于降低所述源漏极内金属原子向后续形成的半导体层扩散的能力；
设置在所述扩散抑制层上的半导体层，所述半导体层的材料为非晶硅；使得从所述扩散抑制层扩散出的金属原子，与所述半导体层中靠近所述源漏极的部分中的非晶硅反应，生成含有金属硅化物的金属过渡层。
8.一种阵列基板，其特征在于，包括如权利要求7所述的薄膜晶体管。
9.一种显示装置，其特征在于，包括如权利要求8所述的阵列基板。
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