CN104867893B - 具有电容耦合的接合焊盘的功率晶体管管芯 - Google Patents

具有电容耦合的接合焊盘的功率晶体管管芯 Download PDF

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Publication number
CN104867893B
CN104867893B CN201510084864.0A CN201510084864A CN104867893B CN 104867893 B CN104867893 B CN 104867893B CN 201510084864 A CN201510084864 A CN 201510084864A CN 104867893 B CN104867893 B CN 104867893B
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bond pad
metal layer
structuring
power transistor
semiconductor body
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CN104867893A (zh
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A.比尔纳
H.布雷希
S.格尔
R.威尔逊
M.齐格尔德伦
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

具有电容耦合的接合焊盘的功率晶体管管芯。一种功率晶体管管芯包括形成在半导体本体中的晶体管。该晶体管具有栅极端子、输出端子和第三端子。栅极端子控制输出端子和第三端子之间的导电通道。功率晶体管管芯进一步包括布置在半导体本体上并与该半导体本体绝缘的结构化的第一金属层。该结构化的第一金属层连接到晶体管的输出端子。功率晶体管管芯还包括布置在半导体本体上并与该半导体本体绝缘的第一接合焊盘。第一接合焊盘形成功率晶体管管芯的输出端子并电容耦合到结构化的第一金属层以便在晶体管的输出端子和第一接合焊盘之间形成串联电容。还提供了一种包括该功率晶体管管芯的功率半导体封装。

Description

具有电容耦合的接合焊盘的功率晶体管管芯
技术领域
本申请涉及功率晶体管管芯，并且具体涉及用于功率晶体管管芯的输出匹配网络。
背景技术
用于功率晶体管管芯的一些高频阻抗匹配拓补在输出信号路径中需要串联电容，该串联电容优选具有电容的高品质因数（Q）。常规设计将串联电容器部件集成在芯片上，伴随有显著损耗和寄生元件，或者在输出信号路径中在管芯的外部添加分立的串联电容器部件，除了增加成本和降低可靠性之外也伴随有损耗和寄生元件。因此期望更高质量和更节省成本的、既鲁棒又有效的串联电容解决方案。
发明内容
根据功率晶体管管芯的实施例，该管芯包括形成在半导体本体中的晶体管，该晶体管包括栅极端子、输出端子和第三端子。栅极端子控制输出端子和第三端子之间的导电通道。功率晶体管管芯进一步包括布置在半导体本体上并与该半导体本体绝缘的结构化的第一金属层。该结构化的第一金属层连接到晶体管的输出端子。功率晶体管管芯还包括布置在半导体本体上并与该半导体本体绝缘的第一接合焊盘。第一接合焊盘形成功率晶体管管芯的输出端子并电容耦合到结构化的第一金属层以便在晶体管的输出端子和第一接合焊盘之间形成串联电容。
根据功率半导体封装的实施例，该封装包括导电基底、电绝缘元件、附着到电绝缘元件的第一引线和功率晶体管管芯。功率晶体管管芯包括形成在半导体本体中的晶体管，该晶体管包括栅极端子、输出端子和第三端子。栅极端子控制输出端子和第三端子之间的导电通道。功率晶体管管芯进一步包括布置在半导体本体上并与该半导体本体绝缘的结构化的第一金属层。该结构化的第一金属层连接到晶体管的输出端子。功率晶体管管芯还包括布置在半导体本体上并与该半导体本体绝缘的第一接合焊盘。第一接合焊盘形成功率晶体管管芯的输出端子并电容耦合到结构化的第一金属层，以便在晶体管的输出端子和第一接合焊盘之间形成串联电容。该封装的第一引线通过一个或多个第一电导体连接到功率晶体管管芯的第一接合焊盘。
本领域技术人员在阅读了以下详细描述以及查看了附图之后将认识到附加的特征和优点。
附图说明
图中的元件不必要相对于彼此按比例。相似的参考数字指定对应的类似部分。各种所示的实施例的特征可以被组合，除非它们互相排斥。实施例在图中被描绘并且在接着的描述中被详述。
图1示出包括功率晶体管管芯的放大器电路和输出匹配网络的实施例的电路图，该功率晶体管管芯在管芯的输出信号路径中具有集成串联电容，该输出匹配网络包括该串联电容。
图2示出功率晶体管管芯的实施例的自上而下的平面图，该功率晶体管管芯在管芯的输出信号路径中具有集成串联电容。
图3包括图3A和图3B，示出根据实施例的功率晶体管管芯的不同区域的截面图，该功率晶体管管芯在管芯的输出信号路径中具有集成串联电容。
图4包括图4A和图4B，示出根据另一实施例的功率晶体管管芯的不同区域的截面图，该功率晶体管管芯在管芯的输出信号路径中具有集成串联电容。
图5示出包括功率晶体管管芯和输出匹配网络的功率半导体封装的实施例的自上而下的平面图，该功率晶体管管芯在管芯的输出信号路径中具有集成串联电容，该输出匹配网络包括串联电容。
具体实施方式
根据本文描述的实施例，串联电容被集成在功率晶体管管芯的输出信号路径中，而没有添加附加的串联部件并且同时避免了寄生元件。串联电容可以被集成在用于输出信号路径的金属化和用于输出信号路径的接合焊盘之间的管芯的输出信号路径中，该金属化和该接合焊盘中的每一个被包括在功率晶体管管芯中。如本文所用的术语‘接合焊盘’包括半导体管芯中所包括的任何导电结构，外部电导体（例如接合线、带、焊料球、金属夹等）可以附着到所述导电结构用于将外部电连接的点提供给管芯。
图1示出包括功率晶体管（TX）（例如RF晶体管）的放大器电路和输出匹配网络的示意图。晶体管形成在半导体本体（未在图1的示意图示中示出）中，并且具有栅极端子100、输出端子102和第三端子104。栅极端子100控制输出端子102和第三端子104之间的导电通道，这是半导体晶体管领域中众所周知的。在MOSFET（金属氧化物半导体场效应晶体管）或其它类型的FET（例如GaN MESFET（金属半导体场效应晶体管）或JFET（结型场效应晶体管））的情况下，输出端子102是漏极端子并且第三端子104是源极端子。在IGBT（绝缘栅双极晶体管）或BJT（双极结型晶体管）（例如GaAs HBT（异质结双极晶体管））的情况下，输出端子102是集电极端子并且第三端子104是发射极端子。
在每一种情况下，输出匹配网络包括串联连接在晶体管的输出端子102和地之间的分路电感器106和分路电容器108、和将晶体管输出102耦合到电路的输出端子（OUT）（例如在包括放大器电路的封装的边缘处）的电感支路110。电感支路110在图1中被描绘为具有电感元件和电阻元件（IND、RES）两者，并且与晶体管的串联电容112串联连接。电路的DC馈电端子（DC偏置）可以通过用于将DC偏置提供给晶体管的输出端子102的另一电感支路114连接在分路电感器106和分路电容器108之间。输出匹配网络提供功率晶体管的输出端子102和电路的输出端子（OUT）之间的阻抗匹配。为了便于说明，对应的输入匹配网络未在图1中示出，但是可以被包括在电路中，用于提供电路的输入端子（未示出）和晶体管的栅极端子100之间的阻抗匹配。功率晶体管的栅极端子100类似地可以电容耦合到电路的输入端子。也就是，本文公开的用于晶体管的输出端子102的相同类型的串联电容结构也可以用在栅极端子100处以将晶体管的栅极端子100电容耦合到电路的输入。
不管输入和输出匹配网络的特别的实施方式，输出匹配网络的串联电容112与晶体管集成在相同的半导体管芯（芯片）中。半导体管芯在图1中由标为‘半导体管芯’的虚线框表示。
图2示出功率晶体管管芯200的实施例的自上而下的平面图，该功率晶体管管芯在管芯200的输出信号路径中包括集成串联电容。管芯200的集成串联电容可以形成图1中所示的输出匹配网络的串联电容112。根据图2的实施例，功率晶体管管芯200包括形成在半导体本体中的功率晶体管，例如RF晶体管，诸如GaN HEMT（高电子迁移率晶体管）、Si LDMOS（横向双扩散金属氧化物半导体）或VDMOS（垂直双扩散MOS）、双极晶体管等。晶体管具有栅极端子、输出端子和第三端子。如本文先前描述的，根据晶体管的类型，输出端子可以是漏极或集电极端子。还如本文先前描述的，再次根据晶体管的类型，第三端子可以是源极或发射极端子。栅极端子控制输出端子和第三端子之间的导电通道，这是半导体晶体管领域中众所周知的。导电通道形成在半导体本体中。晶体管的半导体本体、端子和导电通道在图2中看不见。
功率晶体管管芯200进一步包括布置在半导体本体上并通过介电材料204与该半导体本体绝缘的结构化的第一金属层202。该结构化的第一金属层202连接到晶体管的输出端子。根据图2的实施例，结构化的第一金属层202具有从主基底208向外延伸的多个指状物206。结构化的第一金属层202的指状延伸206平行延伸并相互间隔开。指状延伸206中的每一个和晶体管的下面的输出端子（漏极/集电极）之间的单独连接点可以例如由延伸穿过将结构化的第一金属层202与下面的半导体本体分离的介电材料204的导电通孔来实现。这些单独连接点在图2中看不见，并且共同提供结构化的第一金属层202和晶体管的输出端子之间的导电路径。晶体管管芯200还包括布置在半导体本体上并与该半导体本体绝缘的栅极接合焊盘210、和连接到栅极焊盘210并具有用于连接到晶体管的下面的栅极端子的指状延伸214的结构化的第二金属层212。结构化的第一金属层202的指状延伸206与结构化的第二金属层212的指状延伸214互相交叉。
功率晶体管管芯200还包括布置在半导体本体上并通过介电材料204与该半导体本体绝缘的输出（Cap）接合焊盘216。输出接合焊盘216形成功率晶体管管芯200的输出端子并电容耦合到结构化的第一金属层202以便在晶体管的输出端子和输出接合焊盘216之间形成串联电容。该集成串联电容可以形成图1中所示的输出匹配网络的串联电容。通过省略结构化的第一金属层202和输出接合焊盘216之间的电导体（例如导电通孔）来实现串联电容。通过在管芯200的该区域中省略这种电导体，晶体管的输出端子通过串联电容而不是导电路径电连接到输出接合焊盘216。结构化的第一金属层202和输出接合焊盘216之间的重叠区域（其中省略了电导体）在图2中用标为‘串联电容’的虚线框示出。
功率晶体管管芯200可以进一步包括布置在半导体本体上并通过介电材料204与该半导体本体绝缘的DC接合焊盘218。DC接合焊盘218与输出接合焊盘216间隔开并且可以具有单一连续结构或者可以如图2中所示那样被分段。在任一情况下，DC接合焊盘218形成功率晶体管管芯200的DC偏置端子并且通过由一个或多个电导体实现的导电路径连接到结构化的第一金属层202，所述电导体例如是延伸穿过将DC接合焊盘218与下面的结构化的第一金属层202分离的介电材料204的导电通孔。例如，电导体可以将DC接合焊盘218垂直连接到结构化的第一金属层202的下面的主基底208。提供DC接合焊盘218和结构化的第一金属层202之间的导电路径的电导体在图2中看不见。
图2还示出在晶体管管芯200的输出接合焊盘216和电路封装的输出引线222之间的电连接220，和在晶体管管芯200的DC接合焊盘218和电路封装的分路电容器226之间的电连接224。这些电连接220、224可以使用线接合、带、金属夹或用于连接到晶体管管芯的接合焊盘的任何其它标准工艺来实施，并对应于图1中所示的输出匹配网络的电感106、110、114。
图3包括图3A和3B，示出根据实施例的在功率晶体管管芯200的不同区域中的图2的功率晶体管管芯200的相应截面图。图3A示出在图2中标为A-A的区域中的功率晶体管管芯200的截面图，以及图3B示出在图2中标为B-B的区域中的功率晶体管管芯200的截面图。
根据图3中所示的实施例，输出接合焊盘216和DC接合焊盘218被布置在晶体管管芯200的下面的半导体本体300上方的相同平面内，并且DC接合焊盘218与不同于输出接合焊盘216的下面的结构化的第一金属层202的一部分重叠。DC接合焊盘218通过在DC接合焊盘218与结构化的第一金属层202之间的重叠区域中的、在DC接合焊盘218和结构化的第一金属层202之间垂直延伸的一个或多个导电通孔302连接到下面的结构化的第一金属层202。根据任何标准的晶体管处理技术，晶体管形成在半导体本体300中。
更详细地说，DC接合焊盘218布置在下面的半导体本体300上并通过介电材料204与该下面的半导体本体300绝缘，如图3A中所示。介电材料204可以包括在半导体处理中使用的一个或多个标准介电层，例如SiN、SiO2、低k电介质、高k电介质等。DC接合焊盘218与输出接合焊盘216在横向上间隔开并如本文先前结合图2所描述的形成功率晶体管管芯200的DC偏置端子。DC接合焊盘218与下面的结构化的第一金属层202的一部分重叠并在该重叠区域中通过由一个或多个导电通孔302形成的导电路径连接到结构化的第一金属层202，所述一个或多个导电通孔302在DC接合焊盘218和下面的结构化的第一金属层202之间垂直延伸穿过中间的介电材料204。
输出接合焊盘216布置在结构化的第一金属层202上方并与不同于DC接合焊盘218的结构化的第一金属层202的一部分重叠，如图3B中所示。在输出接合焊盘216和下面的结构化的第一金属层202之间没有提供导电路径。代替地，输出接合焊盘216通过介电材料204的在输出接合焊盘216和结构化的第一金属层202之间的重叠区域中填充输出接合焊盘216和结构化的第一金属层202之间的垂直间隙（间隙）的部分电容耦合到下面的结构化的第一金属层202。所得到的串联电容（串联电容）在图3B中用电容器符号示意性地表示。串联电容是填充垂直间隙的介电材料204的材料类型和厚度的以及在输出接合焊盘216和结构化的第一金属层202之间重叠的尺寸和量的函数。这些参数可以被选择以按照特别的应用的要求调谐串联电容。
图4包括图4A和4B，示出根据另一实施例的在功率晶体管管芯的不同区域中的图2的功率晶体管管芯200的相应截面图。图4A示出在图2中标为A-A的区域中的功率晶体管管芯200的截面图，以及图4B示出在图2中标为B-B的区域中的功率晶体管管芯200的截面图。
根据图4中所示的实施例，输出接合焊盘216布置在晶体管管芯200的下面的半导体本体300上方与结构化的第一金属层202相同的平面内，并且与结构化的第一金属层202在横向上间隔开。第二金属层400布置在半导体本体300上并通过介电材料204与半导体本体300绝缘，所述介电材料204可以包括在半导体处理中使用的一个或多个标准介电层，例如SiN、SiO2、低k电介质、高k电介质等，如本文先前所描述的。
第二金属层400部分地布置在结构化的第一金属层202下方以及部分地布置在输出接合焊盘216下方，使得结构化的第一金属层202与第二金属层400的第一部分402重叠并且输出接合焊盘216与第二金属层400的第二部分404重叠，如图4B中所示。导电通孔406形成将结构化的第一金属层202连接到下面的第二金属层400的第一部分402的导电路径。
输出接合焊盘216通过介电材料204的在输出接合焊盘216和第二金属层400之间的重叠区域中填充输出接合焊盘216和第二金属层400的第二部分404之间的垂直间隙（间隙）的部分电容耦合到下面的第二金属层400。所得到的串联电容（串联电容）是填充垂直间隙的介电材料204的材料类型和厚度的以及在输出接合焊盘216和第二金属层400之间重叠的尺寸和量的函数，如本文先前结合图3所描述的。
DC接合焊盘218布置在半导体本体300上并通过介电材料204与半导体本体300绝缘，并且与输出接合焊盘216间隔开。DC接合焊盘218形成功率晶体管管芯200的DC偏置端子，如本文先前所描述的。进一步根据图4的实施例，DC接合焊盘218布置在与结构化的第一金属层202和输出接合焊盘216相同的平面内。还根据该实施例，DC接合焊盘218和结构化的第一金属层202具有单一连续结构，如图4A中所示。也就是，在该实施例中DC接合焊盘218是结构化的第一金属层202的构成、组成部分。
图5示出功率半导体封装500的自上而下的平面图，该功率半导体封装500包括导电基底502（例如铜法兰）、电绝缘元件504（例如附着到基底502的陶瓷窗）和附着到基底502的本文先前描述的那种功率晶体管管芯200。也就是，功率晶体管管芯200包括形成在半导体本体中的晶体管，该晶体管包括栅极端子、输出（漏极/集电极）端子和第三端子（源极/发射极），该栅极端子控制输出端子和第三端子之间的导电通道。管芯200进一步包括布置在半导体本体上并与该半导体本体绝缘的结构化的第一金属层，该结构化的第一金属层连接到晶体管的输出端子。
功率晶体管管芯200还包括布置在半导体本体上并与该半导体本体绝缘的输出（O）接合焊盘216。输出接合焊盘216形成功率晶体管管芯200的输出端子并电容耦合到管芯200中所包括的结构化的第一金属层以便在晶体管的输出端子和输出接合焊盘216之间形成串联电容，如本文先前所描述的。输出接合焊盘216背离基底502，并且可以具有单一连续结构或者可以如图5中所示那样被分段。源极接合焊盘（看不见）布置在管芯200的相反侧并且连接到晶体管的第三（源极/发射极）端子以及附着到功率半导体封装500的基底502。栅极（G）接合焊盘210与输出接合焊盘216布置在管芯200的相同侧上，并且与输出接合焊盘216间隔开。栅极接合焊盘210连接到晶体管的栅极端子。
功率半导体封装500进一步包括输入引线506，该输入引线506附着到电绝缘元件504并借助一个或多个输入电导体510通过输入分路电容器（Cin）508电容耦合到晶体管管芯200的栅极焊盘210。输入分路电容器508与功率晶体管管芯200间隔开，并具有背离基底502的第一端子512（输入电导体510附着到该第一端子）和面向基底502并附着到基底502的第二端子（看不见）。
功率半导体封装500还包括输出引线514，该输出引线514附着到电绝缘元件504并借助一个或多个输出电导体516连接到晶体管管芯200的输出接合焊盘216。例如图1中所示的那种输出匹配网络的输出分路（Cout）电容器518与功率晶体管管芯200间隔开，并具有背离基底502的第一端子520和面向基底502并附着到基底502的第二端子（看不见）。根据该实施例，功率晶体管管芯200进一步包括布置在管芯200的半导体本体上并与该半导体本体绝缘以及与管芯200的输出接合焊盘216间隔开的DC接合焊盘218。DC接合焊盘218形成功率晶体管管芯200的DC偏置端子并且通过导电路径连接到管芯200的结构化的第一金属层，如本文先前所描述的。DC接合焊盘218还连接到输出分路电容器518的第二端子520，该第二端子520又通过一个或多个DC偏置电导体524连接到封装500的DC偏置引线522。DC接合焊盘218背离封装500的基底502，并且可以具有单一连续结构或者可以如图5中所示那样被分段，取决于封装500的输出和DC偏置引线514、522的布置。封装500的基底502可以接地或束缚于该配置中的另一电势，使得输入和输出分路电容器508、518的第二端子（看不见）以及晶体管的第三（源极/发射极）端子处于相同的电势。
功率晶体管管芯200可以具有本文先前例如根据图2到4描述的结构中的任何一个、或其它结构，只要晶体管管芯200的输出焊盘216电容耦合到管芯200的结构化的第一金属层以在晶体管的输出端子和管芯200的输出接合焊盘216之间形成内部（集成）串联电容。该（集成）串联电容（图3和4中的串联电容）形成图5中所示的功率半导体封装500的输出匹配网络的分路电容。
例如"第一"、"第二"等的术语用来描述各种元件、区域、区段等，并且不旨在是限制性的。在整个描述中，类似的术语指代类似的元件。
如本文使用的，术语"具有"、"包括"、"包含"、"含有"等是开放式术语，其指示所声明的元件或者特征的存在，但并不排除附加的元件或者特征。冠词"一"、"一个"和"该"旨在包括复数以及单数，除非上下文另有清楚指示。
应当理解的是，除非另外特别指出，否则本文所描述的各个实施例的特征可以相互组合。
虽然本文已经示出和描述了特定实施例，但本领域普通技术人员将认识到，在不脱离本发明的范围的情况下，多种替换和/或等效实施方式可替代所示出和描述的特定实施例。本申请旨在涵盖本文所讨论的特定实施例的任何改编或变型。因此，本发明旨在仅由权利要求及其等同物限定。

Claims (18)

1.一种功率晶体管管芯，包括：
形成在半导体本体中的晶体管，所述晶体管包括栅极端子、第一输出端子和第三端子，所述栅极端子控制所述第一输出端子和所述第三端子之间的导电通道；
布置在所述半导体本体上并通过介电材料与所述半导体本体分离的结构化的第一金属层，所述结构化的第一金属层连接到所述晶体管的所述第一输出端子；和
布置在所述半导体本体上并通过介电材料与所述半导体本体分离的第一接合焊盘，所述第一接合焊盘形成所述功率晶体管管芯的第二输出端子并与所述晶体管流电隔离且仅通过介电材料来电容耦合到所述结构化的第一金属层以便在所述晶体管的所述第一输出端子和所述第一接合焊盘之间形成串联电容。
2.根据权利要求1所述的功率晶体管管芯，其中所述第一接合焊盘布置在所述结构化的第一金属层的一部分上方并且与所述结构化的第一金属层的一部分重叠，并且其中所述第一接合焊盘通过在所述第一接合焊盘和所述结构化的第一金属层之间的重叠区域中填充所述第一接合焊盘和所述结构化的第一金属层之间的间隙的介电材料的部分来电容耦合到所述结构化的第一金属层。
3.根据权利要求2所述的功率晶体管管芯，进一步包括：
布置在所述半导体本体上并与所述半导体本体绝缘以及与所述第一接合焊盘间隔开的第二接合焊盘，所述第二接合焊盘与所述第一接合焊盘流电隔离并形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层。
4.根据权利要求3所述的功率晶体管管芯，其中所述第一接合焊盘和所述第二接合焊盘布置在相同的平面内，其中所述第二接合焊盘与不同于所述第一接合焊盘的所述结构化的第一金属层的一部分重叠，并且其中所述第二接合焊盘通过多个导电通孔连接到所述结构化的第一金属层，所述多个导电通孔在所述第二接合焊盘和所述结构化的第一金属层之间的重叠区域中在所述第二接合焊盘和所述结构化的第一金属层之间延伸。
5.根据权利要求1所述的功率晶体管管芯，其中所述第一接合焊盘布置在与所述结构化的第一金属层相同的平面内并且与所述结构化的第一金属层间隔开，所述功率晶体管管芯进一步包括：
布置在所述半导体本体上并通过介电材料与所述半导体本体分离的第二金属层，所述第二金属层部分地布置在所述结构化的第一金属层下方以及部分地布置在所述第一接合焊盘下方，使得所述结构化的第一金属层与所述第二金属层的第一部分重叠并且所述第一接合焊盘与所述第二金属层的第二部分重叠；和
将所述结构化的第一金属层连接到所述第二金属层的所述第一部分的多个导电通孔，
其中所述第一接合焊盘通过在所述第一接合焊盘和所述第二金属层之间的重叠区域中填充所述第一接合焊盘和所述第二金属层的所述第二部分之间的间隙的介电材料的部分来电容耦合到所述第二金属层。
6.根据权利要求5所述的功率晶体管管芯，进一步包括：
布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及与所述第一接合焊盘流电隔离的第二接合焊盘，所述第二接合焊盘形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层。
7.根据权利要求6所述的功率晶体管管芯，其中所述第二接合焊盘和所述结构化的第一金属层在相同的平面内，以及其中所述第二接合焊盘和所述结构化的第一金属层具有单一连续结构。
8.根据权利要求1所述的功率晶体管管芯，进一步包括：
布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及与所述第一接合焊盘流电隔离的第二接合焊盘，所述第二接合焊盘形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层。
9.根据权利要求1所述的功率晶体管管芯，其中所述晶体管是RF晶体管。
10.一种功率半导体封装，包括：
导电基底；
附着到所述基底的电绝缘元件；
附着到所述基底的功率晶体管管芯，并且所述功率晶体管管芯包括：
形成在半导体本体中的晶体管，所述晶体管包括栅极端子、第一输出端子和第三端子，所述栅极端子控制所述第一输出端子和所述第三端子之间的导电通道；
布置在所述半导体本体上并通过介电材料与所述半导体本体分离的结构化的第一金属层，所述结构化的第一金属层连接到所述晶体管的所述第一输出端子；和
布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及背离所述基底的第一接合焊盘，所述第一接合焊盘形成所述功率晶体管管芯的第二输出端子并与所述晶体管流电隔离且仅通过介电材料来电容耦合到所述结构化的第一金属层以便在所述晶体管的所述第一输出端子和所述第一接合焊盘之间形成串联电容；和
第一引线，所述第一引线附着到所述电绝缘元件并通过一个或多个第一电导体连接到所述功率晶体管管芯的所述第一接合焊盘。
11.根据权利要求10所述的功率半导体封装，其中所述第一接合焊盘布置在所述结构化的第一金属层的一部分上方并且与所述结构化的第一金属层的一部分重叠，并且其中所述第一接合焊盘通过在所述第一接合焊盘和所述结构化的第一金属层之间的重叠区域中填充所述第一接合焊盘和所述结构化的第一金属层之间的间隙的介电材料的部分来电容耦合到所述结构化的第一金属层。
12.根据权利要求11所述的功率半导体封装，进一步包括：
电容器，所述电容器与所述功率晶体管管芯间隔开并具有背离所述基底的第一端子和面向所述基底并连接到所述基底的第二端子，
其中所述功率晶体管管芯进一步包括布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及与所述第一接合焊盘流电隔离的第二接合焊盘，所述第二接合焊盘形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层，
其中所述第二接合焊盘通过一个或多个第二电导体连接到所述电容器的所述第二端子。
13.根据权利要求12所述的功率半导体封装，其中所述第一接合焊盘和所述第二接合焊盘布置在相同的平面内，其中所述第二接合焊盘与不同于所述第一接合焊盘的所述结构化的第一金属层的一部分重叠，并且其中所述第二接合焊盘通过多个导电通孔连接到所述结构化的第一金属层，所述多个导电通孔在所述第二接合焊盘和所述结构化的第一金属层之间的重叠区域中在所述第二接合焊盘和所述结构化的第一金属层之间延伸。
14.根据权利要求10所述的功率半导体封装，其中所述第一接合焊盘布置在与所述结构化的第一金属层相同的平面内并且与所述结构化的第一金属层间隔开，并且其中所述功率晶体管管芯进一步包括：
布置在所述半导体本体上并通过介电材料与所述半导体本体分离的第二金属层，所述第二金属层部分地布置在所述结构化的第一金属层下方以及部分地布置在所述第一接合焊盘下方，使得所述结构化的第一金属层与所述第二金属层的第一部分重叠并且所述第一接合焊盘与所述第二金属层的第二部分重叠；和
将所述结构化的第一金属层连接到所述第二金属层的所述第一部分的多个导电通孔，
其中所述第一接合焊盘通过在所述第一接合焊盘和所述第二金属层之间的重叠区域中填充所述第一接合焊盘和所述第二金属层的所述第二部分之间的间隙的介电材料的部分来电容耦合到所述第二金属层。
15.根据权利要求14所述的功率半导体封装，进一步包括：
电容器，所述电容器与所述功率晶体管管芯间隔开并具有背离所述基底的第一端子和面向所述基底并连接到所述基底的第二端子，
其中所述功率晶体管管芯进一步包括布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及与所述第一接合焊盘流电隔离的第二接合焊盘，所述第二接合焊盘形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层，
其中所述第二接合焊盘通过一个或多个第二电导体连接到所述电容器的所述第二端子。
16.根据权利要求15所述的功率半导体封装，其中所述第二接合焊盘和所述结构化的第一金属层在相同的平面内，以及其中所述第二接合焊盘和所述结构化的第一金属层具有单一连续结构。
17.根据权利要求10所述的功率半导体封装，进一步包括：
电容器，所述电容器与所述功率晶体管管芯间隔开并具有背离所述基底的第一端子和面向所述基底并连接到所述基底的第二端子，
其中所述功率晶体管管芯进一步包括布置在所述半导体本体上并通过介电材料与所述半导体本体分离以及与所述第一接合焊盘流电隔离的第二接合焊盘，所述第二接合焊盘形成所述功率晶体管管芯的DC偏置端子并且通过导电路径连接到所述结构化的第一金属层，
其中所述第二接合焊盘通过一个或多个第二电导体连接到所述电容器的所述第二端子。
18.根据权利要求10所述的功率半导体封装，其中所述晶体管是RF晶体管。
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