CN104851812A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN104851812A
CN104851812A CN201510085191.0A CN201510085191A CN104851812A CN 104851812 A CN104851812 A CN 104851812A CN 201510085191 A CN201510085191 A CN 201510085191A CN 104851812 A CN104851812 A CN 104851812A
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China
Prior art keywords
intermediary layer
chip
layer
heat sink
substrate
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Granted
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CN201510085191.0A
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CN104851812B (zh
Inventor
林文强
王家忠
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Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
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Publication of CN104851812A publication Critical patent/CN104851812A/zh
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Abstract

本发明是关于一种半导体元件的制作方法，其具有下述特征步骤：将芯片-中介层堆栈次组体贴附至散热件，并使芯片插入散热件的凹穴中，且中介层侧向延伸于凹穴外。在贴附中介层堆栈次组体及封胶后，执行中介层背面制程，以完成中介层的制作。散热件可作为散热用，制作完成的中介层则提供芯片的初级扇出路由。此外，于此制作方法中，增层电路电性耦接至中介层，以提供进一步的扇出路由。本发明亦提供一种半导体元件。

Description

半导体元件及其制作方法
技术领域
本发明是关于一种半导体元件及其制作方法，尤指一种将芯片嵌埋于散热件中且电性连接至中介层的半导体元件及其制作方法。
背景技术
为了整合行动、通讯以及运算功能，半导体封装产业面临极大的散热、电性以及可靠度挑战。尽管在文献中已报导许多将半导体芯片嵌埋于电路板或模制化合物中的技术，但所述技术仍然存在许多制造与性能不足的问题。举例来说，美国专利案号No.8,742,589、8,735,222、8,679,963及8,453,323中所揭露的半导体元件，其将半导体芯片嵌埋于层压材或模制化合物中，并使用微盲孔作为嵌埋芯片的电性连接。然而，因为所述技术中嵌埋芯片所产生的热无法通过热绝缘材料(例如层压材或模制化合物)适当地散逸，因此导致元件性能衰减的问题。此外，随着芯片制造技术的进步，芯片的接触垫数目持续地增加，造成接触垫的间隔(间距)减小。因此，使用微盲孔的技术会因为微盲孔彼此非常靠近，而导致相邻微盲孔短路。
上述元件的制作会造成另一严重的缺点是在封胶或层压制程中，会造成嵌埋芯片的位移。如美国专利案号No.8,501,544中描述的芯片位移会造成微盲孔未完全金属化的问题，其将导致电性连接质量变差，因此降低元件的可靠度及生产良率。
为了上述理由及以下所述的其他理由，目前亟需发展一种用于互连嵌埋芯片的新装置与方法，其无须于I/O垫上形成微盲孔，以改善芯片级的可靠度，并且不使用热绝缘材料(例如模制化合物或树脂层压材)封胶芯片，以避免元件可靠度及电性表现因芯片过热而出现问题。
发明内容
本发明的主要目的是提供一种半导体元件，其通过多个凸块，将芯片接置于中介层，以形成芯片-中介层堆栈次组体，由此避免于芯片I/O垫上直接进行激光或光显像制程，进而改善半导体元件的生产良率及可靠度。
本发明的另一目的是提供一种半导体元件，其中中介层对于接置其上的芯片提供扇出路由。因为芯片电性连接至中介层的一侧，以通过该中介层扇出，因此增层电路可连接至中介层具有较大接触垫间距的另一侧，用以解决芯片I/O垫间彼此过于靠近的问题，进而改善半导体元件的生产良率及可靠度。
本发明的再一目的是提供一种半导体元件，其中芯片封置于散热件的凹穴中，以有效地散逸芯片产生的热，用以改善半导体元件的信号完整性及电性表现。
依据上述及其他目的，本发明提出一种半导体元件，其包括芯片、中介层、散热件、封胶层、以及增层电路。中介层通过多个凸块互连至芯片，并提供芯片的初级扇出路由，以避免因为过小I/O垫间距所可能导致的未连接接触垫的问题。具有凹穴的散热件通过导热材料与芯片热性导通，使位于凹穴中的芯片得以散热。增层电路邻接封胶层及中介层，并电性连接至中介层，以提供芯片的第二级扇出路由，并且具有与下一级组体电路板匹配的终端垫图案阵列。
在本发明的另一实施态样中，本发明提供一种半导体元件的制作方法，其包括以下步骤：
提供一芯片；
提供一中介层半成品，其包含具有相对第一表面及第二表面的一基板、于该基板的第一表面上的多个接触垫、以及多个金属化导孔，其中每一金属化导孔形成于该基板中，并且具有电性耦接至所述接触垫的一第一端、以及与该基板的第二表面保持距离的一相对第二端；
通过多个凸块，将该芯片电性耦接至该中介层半成品的所述接触垫，以形成一芯片-中介层堆栈次组体；
提供一散热件，其具有相对的第一表面及第二表面、以及形成于该第二表面的一凹穴；
使用一导热材料，将该芯片-中介层堆栈次组体贴附至该散热件，并使该芯片插入该凹穴中，且该中介层半成品侧向延伸于该凹穴外；
提供一封胶层，以覆盖该散热件的第二表面及该中介层半成品；
移除部分该封胶层及部分该中介层半成品，以显露所述金属化导孔的所述第二端，并使该基板具有与所述金属化导孔的所述第二端实质上共平面的一外露第二表面；
于该基板的该外露第二表面上形成多路由线路，以制作完成一中介层，其中该中介层包括分别位于其相对第一表面及第二表面上的所述接触垫及所述路由线路、以及电性耦接至所述接触垫及所述路由线路的所述金属化导孔；以及
于该封胶层及该中介层的该第二表面及所述路由线路上形成一增层电路，其中该增层电路通过该增层电路的多个导电盲孔电性耦接至该中介层的所述路由线路。
除非特别描述或必须依序发生的步骤，上述步骤的顺序并无限制于以上所列，且可根据所需设计而变化或重新安排。
在本发明的再一实施态样中，本发明提供一种半导体元件，其包括：一芯片、一中介层、一散热件、一封胶层、及一增层电路，其中(i)该中介层具有一第一表面、与该第一表面相对的一第二表面、于该第一表面上的多个接触垫，于该第二表面上的多路由线路、以及电性耦接所述接触垫与所述路由线路的多个金属化导孔；(ii)该芯片通过多个凸块电性耦接至该中介层的所述接触垫，以形成一芯片-中介层堆栈次组体；(iii)该散热件具有一第一表面、相对的一第二表面、以及形成于该第二表面的一凹穴；(iv)该芯片-中介层堆栈次组体通过一导热材料贴附至该散热件，并且该芯片插入该凹穴中，且该中介层为侧向延伸于该凹穴外；(v)该封胶层覆盖该中介层的侧壁及该散热件的第二表面；以及(vi)该增层电路形成于该封胶层及该中介层的该第二表面及所述路由线路上，并且通过该增层电路的多个导电盲孔电性耦接至该中介层的所述路由线路。
本发明的半导体元件制作方法具有许多优点。举例来说，先形成芯片-中介层堆栈次组体后，再贴附至散热件，其可确保芯片的电性连接，因此可避免于微盲孔制程中会遭遇的未连接接触垫问题。使用中介层半成品以互连芯片，则无须于中介层整合于2.5D基板前，先在中介层中制作金属化穿孔，由此得以解决穿孔的金属沉积问题，并改善生产良率。此外，由于该制程在于提供封胶层及散热件以支撑中介层后，才对中介层进行研磨，故此作法可对研磨后的中介层提供足够的机械刚性。再者，以两步骤形成联机于芯片的互连基板是具有益处的，其原因在于，中介层可提供初级扇出路由，而增层电路则可提供上元件与下元件间的进一步扇出路由及水平互连。
本发明的上述及其他特征与优点可通过下述较佳实施例的详细叙述更加清楚明了。
附图说明
参考随附图式，本发明可通过下述较佳实施例的详细叙述更加清楚明了，其中：
图1及图2分别为本发明的一实施态样中，具有盲孔的基板剖视图及顶部立体视图；
图3为本发明的一实施态样中，图1的结构形成金属化导孔后的剖视图；
图4及图5分别为本发明的一实施态样中，图3的结构形成路由线路以完成中介层面板半成品的剖视图及顶部立体视图；
图6为本发明的一实施态样中，将凸块设置于芯片上的剖视图；
图7及图8分别为本发明的一实施态样中，图6的芯片电性耦接至图4及5中介层面板半成品的面板组体剖视图及顶部立体视图；
图9及图10分别为本发明的一实施态样中，图7及图8的面板组体切割后的剖视图及顶部立体视图；
图11及图12分别为本发明的一实施态样中，散热件的剖视图及顶部立体视图；
图13及图14分别为本发明的一实施态样中，将图9及图10的切割后的芯片-中介层堆栈次组体贴附至图11及图12散热件的剖视图及顶部立体视图；
图15为本发明的一实施态样中，图9及图10的切割后的芯片-中介层堆栈次组体贴附至图11及图12散热件的另一态样剖视图；
图16为本发明的一实施态样中，于图15结构中提供另一黏着剂的剖视图；
图17为本发明的一实施态样中，形成封胶层于图13结构上的剖视图；
图18为本发明的一实施态样中，移除部分图17结构的剖视图；
图19及图20分别为本发明的一实施态样中，形成路由线路于图18结构上的剖视图及顶部立体视图；
图21为本发明的一实施态样中，形成介电层于图19结构上的剖视图；
图22为本发明的一实施态样中，于图21的结构形成盲孔的剖视图；
图23为本发明的一实施态样中，形成导线于图22结构上的剖视图；
图24为本发明的一实施态样中，将图23的结构切割后的剖视图；
图25为本发明的一实施态样中，图24的结构切割后的单件剖视图；以及
图26为本发明的一实施态样中，另一半导体元件的剖视图。
【符号说明】
芯片-中介层堆栈次组体 10
中介层面板半成品 11
中介层半成品 11’
中介层 12
芯片 13
凸块 15
底部填充材料 16
封胶层 18
散热件 20
半导体元件 100、200
第一表面 101、201
第一端 102
第二表面 103、103’、203
第二端 104
盲孔 105、313、314
基板 111
金属化导孔 113
接触垫 115
路由线路 117
主动面 131
非主动面 133
I/O垫 135
导热材料 171
黏着剂 173
凹穴 205
增层电路 301
绝缘层 311
导线 315
导电盲孔 317、318
切割线 L
具体实施方式
在下文中，将提供一实施例以详细说明本发明的实施态样。本发明的优点以及功效将通过本发明所揭露的内容而更为显著。在此说明所附之图式是简化过且做为例示用。图式中所示的元件数量、形状及尺寸可依据实际情况而进行修改，且元件的配置可能更为复杂。本发明中也可进行其他方面的实践或应用，且不偏离本发明所定义的精神及范畴的条件下，可进行各种变化以及调整。
图1-图25为本发明一实施态样中，一种半导体元件的制作方法图，其中该半导体元件包括一中介层、一芯片、一散热件、一封胶层、以及一增层电路。
如图25所示，半导体元件100包括中介层12、芯片13、散热件20、封胶层18、以及增层电路301。中介层12及芯片13通过导热材料171而贴附至散热件20，且芯片13置放于散热件20的凹穴205中。封胶层18侧向覆盖且围绕中介层12的侧壁，并且自中介层12侧向延伸至结构的外围边缘。增层电路301由上方覆盖中介层12及封胶层18，并且通过导电盲孔317电性耦接至中介层12的路由线路117。
图1、图3-图4、图6-图7及图9为本发明一实施态样的芯片-中介层堆栈次组体制程剖视图，图2、图5、图8及图10分别为对应图1、图4、图7及图9的顶部立体视图。
图1及图2分别为基板111的剖视图及顶部立体视图，其包括第一表面101、相对的第二表面103、以及形成于第一表面101的盲孔105。基板111可由硅、玻璃、陶瓷、石墨、或树脂制成，并且具有50微米至500微米的厚度。盲孔105具有25微米至250微米的深度。在本实施态样中，基板111为硅制成并且具有200微米的厚度，盲孔105则具有150微米的深度。
图3为形成金属化导孔113后的剖视图。通过沉积金属于盲孔105中，以于基板111中形成金属化导孔113。每一金属化导孔113具有与基板111的第一表面101实质上共平面的第一端102，以及与基板111的第二表面103保持距离的相对第二端104。于硅或石墨基板的态样中，因为硅为半导体材料，而石墨为导电材料，因此在沉积金属前，盲孔105的侧壁需形成例如氧化硅层的绝缘/保护层(图未绘示)。
图4及图5分别为中介层面板半成品11的剖视及顶部立体视图，其基板111的第一表面101上具有接触垫115。基板111的第一表面101可通过各种技术进行金属化，例如电镀、无电电镀、蒸镀、溅镀、或其组合。一旦达到所须的厚度后，施行金属图案化制程以形成电性耦接至金属化导孔113第一端102的接触垫115。同样地，于使用硅或石墨基板时，在形成接触垫前须先形成绝缘/保护层(图未绘示)于基板表面上。
图6为凸块15设置于芯片13上的剖视图。芯片13包括主动面131、与主动面131相对的非主动面133、以及位于主动面131上的I/O垫135。凸块15设置于芯片13的I/O垫135上，并且可为锡凸柱、金凸柱、或铜凸柱。
图7及图8分别为面板组体(panel-scale assembly)的剖视图及顶部立体视图，其将芯片13电性耦接至中介层面板半成品11。通过热压、回焊、或热超音波接合技术，可将芯片13通过凸块15电性耦接至中介层面板半成品11的接触垫115。或者，可先沉积凸块15于中介层面板半成品11的接触垫115上，然后芯片13再通过凸块15电性耦接至中介层面板半成品11。此外，可选择性地进一步提供底部填充材料16，以填充中介层面板半成品11与芯片13间的间隙。
图9及图10分别为面板组体切割成个别单件的剖视图及顶部立体视图。面板组体沿着切割线“L”被单离成个别的芯片-中介层堆栈次组体(chip-on-interposer subassembly)10。因此，每一芯片-中介层堆栈次组体10包含自中介层面板半成品11单离出的中介层半成品11’。
图11及图12分别为散热件20的剖视图及顶部立体视图，其具有第一表面201、相对的第二表面203、以及凹穴205。散热件20的厚度可为0.1毫米至10毫米，并且可由铜、铝、不锈钢、或其他合金所制成。凹穴205于第二表面203处设有一入口，并且每一凹穴205可具有不同尺寸及凹穴深度。凹穴深度的范围可为0.05毫米至1.0毫米。在此实施态样中，散热件20为厚度2毫米的铜板，并且具有0.21毫米深度的凹穴205(以容置0.15毫米芯片及0.05毫米导电凸块)。
图13及图14分别为芯片-中介层堆栈次组体10通过导热材料171贴附至散热件20的剖视图及顶部立体视图。芯片13位于凹穴205中，中介层半成品11’位于凹穴205外，同时基板111的第一表面101贴附至散热件20的第二表面203上。通过涂布导热材料171于凹穴底部上，然后将芯片-中介层堆栈次组体10的芯片13插入凹穴205中，以将芯片13贴附至散热件20。凹穴205中的导热材料171(通常为导热但不导电的黏着剂)受到芯片13挤压，向上流入芯片13与凹穴侧壁的间隙中，并且溢流至散热件20的第二表面203上。因此，导热材料171围绕嵌埋的芯片13，且挤出的部分接触中介层半成品11’的第一表面101及散热件20的第二表面203，并夹置于中介层半成品11’的第一表面101与散热件20的第二表面203间。
图15及图16为芯片-中介层堆栈次组体10贴附至散热件20的另一制程剖视图。
图15为通过涂布于凹穴205底部的导热材料171，将芯片-中介层堆栈次组体10贴附至散热件20的剖视图。导热材料171通常为导热黏着剂，并提供芯片13及散热件20间的机械性接合。
图16为黏着剂173填充至中介层半成品11’与散热件20之间，并进一步延伸进入凹穴205中的剖视图。黏着剂173通常为电性绝缘的底部填充材料，其涂布于中介层半成品11’与散热件20之间，且填入凹穴205的剩余空间中。因此，导热材料171提供芯片13及散热件20间的机械性接合及热性连接，而黏着剂173则提供芯片13与散热件20间、以及中介层半成品11’与散热件20间的机械性接合。
图17为封胶层18形成于芯片-中介层堆栈次组体10及散热件20上的剖视图。封胶层18可通过模制、树脂涂布、或树脂层压形成，并且由上方覆盖芯片-中介层堆栈次组体10及散热件20。
图18为金属化导孔113的第二端104自上方显露的剖视图。移除封胶层18及基板111的顶部区域，以使金属化导孔113的第二端104显露于基板111的外露第二表面103’，其中移除方式通常通过抛光、研磨或激光技术。基板111的外露第二表面103’与金属化导孔113的第二端104及封胶层18的顶部表面实质上共平面。
图19及图20分别为通过金属沉积及图案化制程形成路由线路117的剖视图及顶部立体视图。基板111的第二表面103’可通过各种技术进行金属化，例如电镀、无电电镀、蒸镀、溅镀、或其组合。一旦达到所须的厚度后，施行金属图案化制程以形成路由线路117。路由线路117侧向延伸于基板111的第二表面103’上，并且电性耦接至金属化导孔113的第二端104。金属图案化技术包括湿蚀刻、电化学蚀刻、激光辅助蚀刻及其组合，并使用蚀刻光罩(图未示)，以定义出路由线路117。
进行至此阶段，每一芯片-中介层堆栈次组体10包括一制作完成的中介层12，其具有位于第一表面101上的接触垫115、第二表面103’上的路由线路117、以及电性耦接接触垫115及路由线路117的金属化导孔113。因为中介层12的路由线路117的垫尺寸及间隔较芯片I/O垫135大，因此中介层12可提供芯片13的初级扇出路由，以确保下一级增层电路互连具有较高的生产良率。
图21为绝缘层311形成于封胶层18及中介层12的第二表面103’及路由线路117上的剖视图，其形成方法通常通过层压或涂布。绝缘层311自上方接触且覆盖封胶层18及中介层12的第二表面103’及路由线路117，并侧向延伸于中介层12的第二表面103’及封胶层18上，且通常具有50微米的厚度。绝缘层311可由环氧树脂、玻璃环氧树脂、聚酰亚胺、或其类似物所制成。
图22为形成盲孔313的剖视图。盲孔313延伸穿过绝缘层311并对准路由线路117的选定部分。盲孔313可通过各种技术形成，其包括激光钻孔、电浆蚀刻、及微影技术，且通常具有50微米的直径。可使用脉冲激光提高激光钻孔效能。或者，可使用金属光罩以及激光束。
参照图23，通过金属沉积及图案化制程，于绝缘层311上形成导线315。导线315自中介层12的路由线路117朝向上方向延伸，并填满盲孔313，以形成直接接触中介层12的路由线路117的导电盲孔317，同时侧向延伸于绝缘层311上。因此，导线315可提供X及Y方向的水平信号路由以及穿过盲孔313的垂直路由，以作为中介层12的信号连接。
导线315可通过各种技术形成单层或多层，例如电镀、无电电镀、蒸镀、溅镀、或其组合。举例来说，首先通过将该结构浸入活化剂溶液中，使绝缘层311与无电镀铜产生触媒反应，接着以无电电镀方式被覆一薄铜层做为晶种层，然后以电镀方式将所需厚度的第二铜层形成于晶种层上。或者，于晶种层上沉积电镀铜层前，该晶种层可通过溅镀方式形成如钛/铜的晶种层薄膜。一旦达到所需的厚度，即可使用各种技术图案化被覆层以形成导线315，其包括湿蚀刻、电化学蚀刻、激光辅助蚀刻及其组合，并使用蚀刻光罩(图未示)，以定义出导线315。
图24为图23的结构切割成个别单件的剖视图。图23的结构沿着切割线“L”被单离成个别的半导体元件100。
图25为个别的半导体元件100的剖视图。半导体元件100包括中介层12、芯片13、封胶层18、散热件20、以及增层电路301。在此图中，增层电路301包括绝缘层311及导线315。芯片13通过覆晶制程电性耦接至中介层12，并置放于散热件20的凹穴205中，并通过导热材料171将芯片13贴附并导热至散热件20。中介层12侧向延伸于散热件20的凹穴205外，并且通过中介层12第一表面101与散热件20第二表面203间的导热材料171挤出部分，将中介层12贴附至散热件20。封胶层18侧向覆盖、围绕及共形涂布于中介层12的侧壁，并且与基板111的第二表面103’实质上共平面。通过与中介层12的路由线路117直接接触的导电盲孔317，增层电路301电性耦接至中介层12，因此中介层12与增层电路301间的电性连接无须用到焊接材料。
图26为另一态样的半导体元件200剖视图。半导体元件200与上述的半导体元件100类似，但差异处仅在于，半导体元件200的增层电路301还包含与散热件20的选定部分接触的额外导电盲孔318。导线315自中介层12的路由线路117及散热件20的选定部分朝向上方向延伸，并填满盲孔313、314，以形成导电盲孔317、318，同时侧向延伸于绝缘层311上。据此，增层电路301可通过与中介层12的路由线路117直接接触的导电盲孔317而电性耦接至中介层12的路由线路117，并可通过与散热件20直接接触的额外导电盲孔318而电性耦接至及散热件20。
上述的半导体元件仅为说明范例，本发明尚可透过其他多种实施例实现。此外，上述实施例可基于设计及可靠度的考虑，彼此混合搭配使用或与其他实施例混合搭配使用。芯片可独自使用一凹穴，或与其他芯片共享一凹穴。举例来说，一凹穴可容纳单一芯片，且散热件可包括多个排列成阵列形状的凹穴，以容纳多个芯片。或者，单一凹穴内能放置数个芯片。同样地，芯片可独自使用一中介层，或与其他芯片共享一中介层。举例来说，可将单一芯片电性耦接至一中介层。或者，将数个芯片耦接至同一中介层。举例来说，可将四枚排列成2x2阵列的小型芯片耦接至一中介层，并且该中介层可包括额外的接触垫，以接收额外元件垫，并提供额外元件垫的路由。此外，增层电路亦可包括额外的导线，以连接该中介层的额外的接触垫。
如上述实施态样所示，本发明建构出一种半导体元件，其可展现较佳的散热性能及可靠度，并且包括芯片、中介层、散热件、封胶层、及增层电路。
芯片通过多个凸块电性耦接至中介层，以形成芯片-中介层堆栈次组体。芯片可为已封装或未封装的芯片。举例来说，芯片可为裸晶，或是晶圆级封装芯片等。
散热件可延伸至半导体元件的外围边缘，以提供芯片、中介层、以及增层电路的机械性支撑。在一较佳实施态样中，散热件包括金属板及延伸至金属板中的凹穴。金属板可提供嵌埋芯片的必要散热，且具有0.1毫米至10毫米的厚度。可依据散热考虑来选择金属板的材料，并且金属板的材料可包括铜、铝、不锈钢、或其他合金。据此，芯片所产生的热可通过提供热接触表面的金属板散逸。
散热件的凹穴可在其入口处具有较其底部更大的直径或尺寸，并且具有0.05毫米至1.0毫米的深度。举例来说，凹穴可具有横切的圆锥或方锥形状，其直径或大小自底部向入口递增。或者，凹穴可为具有固定直径的圆柱形状。凹穴亦可在其入口及底部具有圆形、正方形或矩形的周缘。
芯片-中介层堆栈次组体可通过导热材料(例如导热黏着剂)贴附至散热件，其中导热材料先涂布于凹穴底部上，然后当芯片插入散热件的凹穴中时，部分导热材料挤出凹穴外。因此，导热材料可接触并围绕散热件凹穴中的嵌埋芯片。导热材料的挤出部分可接触中介层的第一表面及自凹穴入口侧向延伸的散热件第二表面，并夹置于中介层的第一表面及自凹穴入口侧向延伸的散热件第二表面间。或者，导热材料(例如导热黏着剂)可涂布于凹穴底部，且当芯片插入凹穴中时，导热材料仍位于凹穴中。然后可将第二黏着剂(通常为电性绝缘的底部填充材料)涂布并填入凹穴的剩余空间中，并延伸至中介层的第一表面及自凹穴入口侧向延伸的散热件第二表面间。据此，导热材料提供芯片与散热件间的机械性接合及热性连接，而第二黏着剂则提供中介层与散热件间的机械性接合。
中介层侧向延伸于凹穴外，并可经由将中介层的第一表面贴附至散热件的第二表面的方式，使中介层贴附至散热件。中介层可由硅、玻璃、陶瓷、石墨或树脂材料制成，并且当中介层电性耦接至芯片及贴附至散热件时，中介层为半成品。在一较佳实施态样中，中介层半成品包括厚度50至500微米的基板、深度25至250微米的金属化导孔、以及匹配芯片I/O垫的接触垫。在进行中介层背面研磨制程及形成中介层背面电路后，中介层可包含由第一表面较细微间距扇出至第二表面较粗间距的导线图案。据此，中介层能提供芯片的第一级扇出路由/互连。此外，因为中介层通常由高弹性系数材料制成，且该高弹性系数材料具有与芯片近似的热膨胀系数(例如，每摄氏3至10ppm)，因此，可大幅降低或补偿热膨胀系数不匹配所导致的芯片及其电性互连处的内部应力。为了方便下文描述，中介层的第一表面所面对的方向定义为第一垂直方向，中介层的第二表面所面对的方向定义为第二垂直方向。
在贴附芯片-中介层堆栈次组体后，可通过模制、树脂涂布、或树脂层压，于中介层及散热件上形成封胶层，然后再移除部分封胶层(通常通过抛光、研磨或激光技术)，以使封胶层与中介层基板的外露第二表面实质上共平面。因此，封胶层可自第二垂直方向覆盖并接触散热件的第二表面，并且侧向覆盖、围绕及共形涂布于中介层的侧壁，同时自中介层侧向延伸至元件的外围边缘。
增层电路由第二垂直方向覆盖封胶层及中介层的第二表面及路由线路，并且可提供第二级扇出路由/互连。此外，增层电路可进一步通过额外导电盲孔电性耦接至散热件的金属第二表面，以作为接地连接用。增层电路包括绝缘层、以及一或多个导线。绝缘层形成于封胶层及中介层的第二表面及路由线路上。导线侧向延伸于绝缘层上，并且延伸穿过绝缘层中的盲孔，以形成与中介层的接触垫直接接触的导电盲孔，并且其可选择性地与散热件直接接触。据此，导线可直接接触接触垫，以提供中介层的信号路由，因此中介层与增层电路间的电性连接无须使用焊接材料。假如需要更多的信号路由，增层电路可进一步包括额外的绝缘层、额外的盲孔、以及额外的导线。增层电路的最外侧导线可容置导电接点，例如焊球，以与下一级组体或另一电子元件(如半导体芯片、塑料封装件、或另一半导体元件)电性传输及机械性连接。
「覆盖」一词意指于垂直及/或侧面方向上不完全以及完全覆盖。例如，在凹穴向下的状态下，散热件则于上方覆盖芯片，不论另一元件例如导热材料是否位于散热件及芯片间，同时增层电路于下方覆盖散热件，不论两者是否具有具有元件。
「电性连接」、以及「电性耦接」的词意指直接或间接电性连接。例如，导线直接接触并且电性连接至中介层的路由线路，以及导线与中介层的接触垫保持距离，并且通过路由线路及金属化党导孔电性连接至中介层的接触垫。
「第一垂直方向」及「第二垂直方向」并非取决于元件的定向，凡熟悉此项技艺的人士即可轻易了解其实际所指的方向。例如，中介层的第一表面面朝第一垂直方向，且中介层的第二表面面朝第二垂直方向，此与元件是否倒置无关。因此，该第一及第二垂直方向彼此相反且垂直于侧面方向。再者，在凹穴向下的状态，第一垂直方向为向上方向，第二垂直方向为向下方向；在凹穴向上的状态，第一垂直方向为向下方向，第二垂直方向为向上方向。
本发明的半导体元件具有许多优点。举例来说，通过现有的覆晶接合制程(例如热压或回焊)，将芯片电性耦接至中介层，其可避免多个现有技术使用黏着载体作为暂时接合时所遭遇到的位置准确度问题。中介层提供芯片的第一级扇出路由/互连，而增层电路则提供第二级扇出路由/互连。由于增层电路形成于具有较大垫尺寸及间距的中介层上，与传统的增层电路直接形成在芯片的I/O垫上，并且不具扇出路由的技术相比，前者具有较后者大幅改善的生产良率。散热件可提供嵌埋芯片的散热、电磁屏蔽、及湿气阻障，并且提供芯片、中介层、以及增层电路的机械性支撑。中介层与增层电路间直接电性连接，而未使用焊料，因此有利于展现高I/O值以及高性能。通过此方法制备成的元件为可靠度高、价格低廉、且非常适合大量制造生产。
本案的制作方法具有高度适用性，且是以独特、进步的方式结合运用各种成熟的电性及机械性连接技术。此外，本案的制作方法不需昂贵工具即可实施。因此，相较于传统技术，此制作方法可大幅提升产量、良率、效能与成本效益。
在此所述的实施例为例示之用，其中所述实施例可能会简化或省略本技术领域已熟知的元件或步骤，以免模糊本发明的特点。同样地，为使图式清晰，图式亦可能省略重复或非必要的元件及元件符号。

Claims (4)

1.一种半导体元件的制作方法，其特征在于，包含以下步骤：
提供一芯片；
提供一中介层半成品，其包含具有一第一表面及一相对第二表面的一基板、于该基板的该第一表面上的多个接触垫、以及多个金属化导孔，其中每一所述金属化导孔形成于该基板中，并且具有电性耦接至所述接触垫的一第一端、以及与该基板的该第二表面保持距离的一相对第二端；
通过多个凸块电性耦接该芯片至该中介层半成品的所述接触垫，以形成一芯片-中介层堆栈次组体；
提供一散热件，其具有相对的一第一表面及一第二表面、以及形成于该第二表面的一凹穴；
使用一导热材料贴附该芯片-中介层堆栈次组体至该散热件，并使该芯片插入该凹穴中，且该中介层半成品侧向延伸于该凹穴外；
提供一封胶层，以覆盖该散热件的该第二表面及该中介层半成品；
移除部分该封胶层及部分该中介层半成品，以显露所述金属化导孔的所述第二端，并使该基板具有与所述金属化导孔的所述第二端实质上共平面的一外露第二表面；
于该基板的该外露第二表面上形成多路由线路，以制作完成一中介层，其中该中介层包括分别位于其相对第一表面及第二表面上的所述接触垫及所述路由线路、以及电性耦接至所述接触垫及所述路由线路的所述金属化导孔；以及
于该封胶层及该中介层的该第二表面及所述路由线路上形成一增层电路，其中该增层电路通过该增层电路的多个导电盲孔电性耦接至该中介层的所述路由线路。
2.根据权利要求1所述的方法，其特征在于，电性耦接该芯片至该中介层半成品的所述接触垫的该步骤是以面板规模进行，并且于贴附该芯片-中介层堆栈次组体至该散热件的该步骤前执行一单片化步骤，以分离个别的芯片-中介层堆栈次组体。
3.根据权利要求1所述的方法，其特征在于，该增层电路包含多个额外的导电盲孔，以电性耦接至该散热件。
4.一种半导体元件，其特征在于，通过下述步骤制成：
提供一芯片；
提供一中介层半成品，其包含具有一第一表面及一相对第二表面的一基板、于该基板的该第一表面上的多个接触垫、以及多个金属化导孔，其中每一所述金属化导孔形成于该基板中，并且具有电性耦接至所述接触垫的一第一端、以及与该基板的该第二表面保持距离的一相对第二端；
通过多个凸块电性耦接该芯片至该中介层半成品的所述接触垫，以形成一芯片-中介层堆栈次组体；
提供一散热件，其具有相对的一第一表面及一第二表面、以及形成于该第二表面的一凹穴；
使用一导热材料贴附该芯片-中介层堆栈次组体至该散热件，并使该芯片插入该凹穴中，且该中介层半成品侧向延伸于该凹穴外；
提供一封胶层，以覆盖该散热件的该第二表面及该中介层半成品；
移除部分该封胶层及部分该中介层半成品，以显露所述金属化导孔的所述第二端，并使该基板具有与所述金属化导孔的所述第二端实质上共平面的一外露第二表面；
于该基板的该外露第二表面上形成多路由线路，以制作完成一中介层，其中该中介层包括分别位于其相对第一表面及第二表面上的所述接触垫及所述路由线路、以及电性耦接至所述接触垫及所述路由线路的所述金属化导孔；以及
于该封胶层及该中介层的该第二表面及所述路由线路上形成一增层电路，其中该增层电路通过该增层电路的多个导电盲孔电性耦接至该中介层的所述路由线路。
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