CN104835799B - 导线架结构、四方平面无引脚封装及形成导线架结构方法 - Google Patents

导线架结构、四方平面无引脚封装及形成导线架结构方法 Download PDF

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CN104835799B
CN104835799B CN201510063591.1A CN201510063591A CN104835799B CN 104835799 B CN104835799 B CN 104835799B CN 201510063591 A CN201510063591 A CN 201510063591A CN 104835799 B CN104835799 B CN 104835799B
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frame structure
conducting wire
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CN104835799A (zh
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林殿方
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King Yuan Electronics Co Ltd
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Dawning Leading Technology Inc
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Abstract

用于四方平面无引脚(quad flat no‑lead,QFN)封装的导线架结构包括一基座，多个端点以及一第一金属层。该基座具有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域。该多个端点是环绕该基座设置。该第一金属层具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上。其中该基座及该多个端点是由一冲压工艺所形成，且该第一金属层是在该冲压工艺之前由一镀膜工艺所形成。

Description

导线架结构、四方平面无引脚封装及形成导线架结构方法
技术领域
本发明相关于一种导线架结构，尤指一种用于四方平面无引脚封装的导线架结构。
背景技术
请参考图1，图1是公知形成导线架结构的方法的流程图100。如图1所示，一导线架的各个元件首先在步骤110中形成。在步骤120中，对导线架的部分区域进行半蚀刻，以减少部分区域的厚度。之后，在步骤130中，一金属层被镀膜于导线架上以加强电性连接。
请参考图2，并一并参考图1。图2是公知导线架结构20的剖面图。如图2所示，由于金属层230是在形成导线架200的元件210、220后被镀膜于导线架200上，部分残留金属材料240有可能会存在于导线架200的元件210、220的侧壁上，造成封装材料容易随着残留金属材料240从导线架200的金属层230剥离，使得湿气容易从剥离部分的缝隙入侵至封装中，进而降低电性可靠度。因此，在导线架结构20被封装之后，导线架结构20会因残留金属材料240而无法稳固地和封装材料接合。由此可得知，当公知导线架结构20应用于四方平面无引脚封装时具有较差的封装品质和可靠度。
发明内容
本发明提供一种导线架结构，适用于四方平面无引脚封装，包括一基座，多个端点以及一第一金属层。该基座具有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域。该多个端点是环绕该基座设置。该第一金属层具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上。其中该基座及该多个端点是由一冲压工艺所形成，且该第一金属层是在该冲压工艺之前由一镀膜工艺所形成。另包括：多个连接条，设置于该基座及该多个端点之间；以及其中该第一金属层，另具有一第三部分形成于该多个连接条上。另包括：多个凸块，其高度高于该基座及该多个端点，用以支撑一封装模具。该第一金属层的第一部分是连续地形成于该外围区域上以环绕该中心区域。该第一金属层的第一部分是不连续地形成于该外围区域上以环绕该中心区域。
本发明另提供一种四方平面无引脚封装，包括一导线架结构，一半导体芯片以及一封装单元。该导线架结构包括一基座，多个端点以及一第一金属层。该基座具有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域。该多个端点是环绕该基座设置。该第一金属层具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上。该半导体芯片是通过一贴附层接合于该基座的中心区域，且电连接于该第一金属层的第一部分及该第一金属层的第二部分。该封装单元是用以封装该半导体芯片。其中该基座及该多个端点是由一冲压工艺所形成，且该第一金属层是在该冲压工艺之前由一镀膜工艺所形成。该封装单元的下表面是对齐于该导线架结构的背面。该导线架结构另包括：多个连接条，设置于该基座及该多个端点之间；以及其中该第一金属层，另具有一第三部分形成于该多个连接条上。该导线架结构另包括：多个凸块，其高度高于该基座及该多个端点，用以支撑一封装模具；其中该封装单元的上表面是对齐于该多个凸块的上表面。另包括：一第二金属层，用以覆盖该基座的背面，且覆盖该多个端点的背面及侧壁。本发明另提供一种形成导线架结构的方法，包括提供一金属板；于该金属板的正面形成一图案化金属层；以及于形成该图案化金属层后，冲压该金属板以形成一基座和多个端点；其中该基座形成有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域，且该多个端点是形成于该基座周围；以及其中该图案化金属层具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上。于冲压该金属板之前，对该金属板的背面进行半蚀刻。多个连接条是于冲压该金属板时进一步形成，并设置于该基座及该多个端点之间，且该图案化金属层另具有一第三部分形成于该多个连接条上。本发明的有益效果为：
相较于先前技术，由于本发明导线架结构的图案化金属层是在形成基座和端点的冲压工艺之前所形成，基座和端点的侧壁将不会有残留金属材料存在，所以图案化金属层可以稳固地固定在金属板的正面，且导线架结构和封装材料之间可以具有较强的接合力。因此包括本发明导线架结构的四方平面无引脚封装可以具有较佳的封装品质、电性连接及可靠度。
附图说明
图1是公知形成导线架结构的方法的流程图；
图2是公知导线架结构的剖面图；
图3是本发明导线架结构的第一实施例的形成过程的示意图；
图4是本发明导线架结构的第一实施例的俯视图；
图5是四方平面无引脚(quad flat no-lead,QFN)封装包括本发明导线架结构的第一实施例的示意图；
图6是第5图封装单元的形成过程的示意图；
图7是本发明导线架结构的第二实施例的形成过程的示意图；
图8是本发明导线架结构的第二实施例的俯视图；
图9是本发明形成导线架结构的方法的流程图。
附图标记说明：
100、流程图
110至130、步骤
20、导线架结构
200、导线架
210、导线架元件
220、导线架元件
230、金属层
240、残留金属材料
30、导线架结构
310、基座
312、中心区域
314、外围区域
320、端点
330、金属层
330a、金属层的第一部分
330b、金属层的第二部分
330c、金属层的第三部分
340、凸块
350、连接条
360、外框
400、封装模具
50、四方平面无引脚封装
510、半导体芯片
520、封装单元
530、金属层
70、导线架结构
900、流程图
910至940、步骤
P、金属板
M、图案化遮罩
具体实施方式
请同时参考图3及图4，图3是本发明导线架结构的第一实施例的形成过程的示意图，图4是本发明导线架结构30的第一实施例的俯视图。如图3所示，一图案化遮罩M被置放于一金属板P上，以使图案相反于该图案化遮罩M的一金属层330形成于金属板P的正面。金属层330可以是由一镀膜工艺所形成。之后，对金属板P的背面进行半蚀刻以使金属板P的部分厚度减少。最后，金属板P经过一冲压工艺以形成一基座310以及多个端点320。如图4所示，基座310具有一中心区域312用以承载一半导体芯片，以及一外围区域314围绕中心区域312。多个端点320是环绕基座310设置。金属层330具有一第一部分330a形成于基座310的外围区域314上，以及一第二部分330b形成于多个端点320上。
金属层330的第一部分330a可以用来作为电极以提供一预定电压。在本实施例中金属层330的第一部分330a是连续地形成于外围区域314上以环绕中心区域312。但在本发明其他实施例中，金属层330的第一部分330a亦可以不连续地形成于外围区域314上以环绕中心区域312。
另一方面，基座310和多个端点320是连接于一外框360(外框360之后会被切除)，以将基座310和多个端点320支撑于同一平面上。
依据上述配置，由于金属层是在形成基座310和多个端点320的冲压工艺之前所形成，基座310和多个端点320的侧壁将不会有残留金属材料存在。因此，金属层的第一部分330a和第二部分330b可以稳固地分别固定在基座310和多个端点320的正面，且导线架结构30和封装材料之间可以具有较强的接合力。
请参考图5，图5是四方平面无引脚(quad flat no-lead,QFN)封装50包括本发明导线架结构30的第一实施例的示意图。如图5所示，四方平面无引脚封装50包括导线架结构30，一半导体芯片510以及一封装单元520。半导体芯片510是通过一贴附层接合于基座310的中心区域312，且经由导线电连接于金属层的第一部分330a及金属层的第二部分330b。封装单元520是由封装材料形成，用以封装半导体芯片510。封装单元520的下表面是对齐于导线架结构30的背面。本发明四方平面无引脚封装50可包括另一金属层530，用以覆盖基座310的背面，且覆盖多个端点320的背面及侧壁。金属层530可以覆盖基座310及端点320以避免基座310及端点320被氧化。另外，当四方平面无引脚封装50安装于一电路板上时，金属层530亦可以提供较大的接触面积，以得到较佳的电连接品质和可靠度。
请参考图6，图6是在图5中封装单元520的形成过程的示意图。如图6所示，导线架结构30可另包括多个凸块340，其高度高于基座310及多个端点320。凸块340可用以支撑一封装模具400。当封装模具400置放于凸块340上之后，封装材料可以注入以封装半导体芯片510。当封装材料固化后即形成封装单元520。依据上述配置，封装单元520的上表面是对齐于多个凸块340的上表面，也就是说，封装单元520的高度是由凸块340所决定。
请同时参考图7及图8，图7是本发明导线架结构70的第二实施例的形成过程的示意图，图8是本发明导线架结构70的第二实施例的俯视图。相异于本发明第一实施，当对金属板P进行冲压工艺时，多个连接条350进一步形成于基座310及多个端点320之间。另外，金属层330另具有一第三部分330c形成于多个连接条350上。金属层的第三部分330c可以用来作为电极以提供另一预定电压。
另一方面，基座310、多个端点320及多个连接条350是连接于一外框360(外框360之后会被切除)，以将基座310、多个端点320及多个连接条350支撑于同一平面上。
相似于图5，导线架结构70亦可以采用一封装材料，并被另一金属层覆盖以形成一四方平面无引脚封装。
再者，导线架结构70可另包括多个凸块，其高度高于基座310、多个端点320及多个连接条350，用以支撑一封装模具。
请参考图9，图9为本发明形成导线架结构的方法的流程图900。本发明形成导线架结构的方法的流程如下列步骤：
步骤910：提供一金属板；
步骤920：于该金属板的正面形成一图案化金属层；
步骤930：对该金属板的背面进行半蚀刻；及
步骤940：冲压该金属板以形成一基座和多个端点。
相较于先前技术，由于本发明导线架结构的图案化金属层是在形成基座和端点的冲压工艺之前所形成，基座和端点的侧壁将不会有残留金属材料存在，所以图案化金属层可以稳固地固定在金属板的正面，且导线架结构和封装材料之间可以具有较强的接合力。因此包括本发明导线架结构的四方平面无引脚封装可以具有较佳的封装品质、电性连接及可靠度。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种导线架结构，适用于四方平面无引脚封装，其特征在于，包括：
一基座，具有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域；
多个端点，环绕该基座设置；
一第一金属层，具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上；以及
一第二金属层，用以覆盖该基座的背面，且覆盖该多个端点的背面及侧壁；
其中该基座及该多个端点是由一冲压工艺所形成，且该第一金属层是在该冲压工艺之前由一镀膜工艺所形成。
2.根据权利要求1所述的导线架结构，其特征在于，另包括：
多个连接条，设置于该基座及该多个端点之间；以及
其中该第一金属层，另具有一第三部分形成于该多个连接条上。
3.根据权利要求1所述的导线架结构，其特征在于，另包括：
多个凸块，其高度高于该基座及该多个端点，用以支撑一封装模具。
4.根据权利要求1所述的导线架结构，其特征在于，该第一金属层的第一部分是连续地形成于该外围区域上以环绕该中心区域。
5.根据权利要求1所述的导线架结构，其特征在于，该第一金属层的第一部分是不连续地形成于该外围区域上以环绕该中心区域。
6.一种四方平面无引脚封装，其特征在于，包括：
一导线架结构，一半导体芯片以及一封装单元；
该导线架结构包括：
一基座，具有一中心区域用以承载一半导体芯片，以及一外围区域围绕该中心区域；
多个端点，环绕该基座设置；
一第一金属层，具有一第一部分形成于该基座的外围区域上，以及一第二部分形成于该多个端点上；以及
一第二金属层，用以覆盖该基座的背面，且覆盖该多个端点的背面及侧壁；
其中该半导体芯片接合于该基座的中心区域，且电连接于该第一金属层的第一部分及该第一金属层的第二部分；
其中该封装单元用以封装该半导体芯片；
其中该基座及该多个端点是由一冲压工艺所形成，且该第一金属层是在该冲压工艺之前由一镀膜工艺所形成。
7.根据权利要求6所述的四方平面无引脚封装，其特征在于，该封装单元的下表面是对齐于该导线架结构的背面。
8.根据权利要求6所述的四方平面无引脚封装，其特征在于，该导线架结构另包括：
多个连接条，设置于该基座及该多个端点之间；以及
其中该第一金属层，另具有一第三部分形成于该多个连接条上。
9.根据权利要求6所述的四方平面无引脚封装，其特征在于，该导线架结构另包括：
多个凸块，其高度高于该基座及该多个端点，用以支撑一封装模具；
其中该封装单元的上表面是对齐于该多个凸块的上表面。
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