CN104752507A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN104752507A
CN104752507A CN201410705030.2A CN201410705030A CN104752507A CN 104752507 A CN104752507 A CN 104752507A CN 201410705030 A CN201410705030 A CN 201410705030A CN 104752507 A CN104752507 A CN 104752507A
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CN104752507B (zh
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V·S·巴斯克
刘作光
山下典洪
叶俊呈
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International Business Machines Corp
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Abstract

本发明涉及半导体器件及其制造方法。一种半导体器件包括：衬底，其沿着第一方向延伸以限定衬底长度，并沿着与所述第一方向垂直的第二方向延伸以限定衬底宽度。第一半导体鳍形成于所述衬底的上表面上。所述第一半导体鳍沿着所述第二方向延伸第一距离以限定第一鳍宽度。第一栅极沟道形成于在所述衬底中形成的第一源/漏结与在所述第一半导体鳍中形成的第二源/漏结之间。第一栅极叠层形成于所述第一栅极沟道的侧壁上。第一间隔物被设置在所述第一栅极叠层与所述第一源/漏结之间。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件，更具体地，涉及FinFET半导体器件。
背景技术
常规多栅FinFET半导体器件包括一个或多个半导体鳍(fin)，所述半导体鳍沿着FinFET器件的长度(leff)延伸而限定鳍长度。鳍宽度(wfin)垂直于鳍长度延伸。具有栅极长度(lGATE)的栅极沟道被限定在源极(S)区和漏极(D)区之间。源极区(S)、栅极沟道(lGATE)和漏极区(D)典型地形成为彼此在同一平面内。电流平行于源极(S)区和漏极(D)区之间的leff流动。为了实现更大的驱动电流，常规FinFET器件可包括多个鳍，这些鳍沿着FinFET器件的宽度(weff)彼此平行地形成，如图1所示。因此，随着对驱动更大电流的需求的增加，有必要在衬底上形成另外的鳍。
常规FinFET器件典型地限于鳍高度(hFIN)的整数倍，例如鳍高度的两倍(2x hFIN)。另外的鳍的形成也会增加总的weff。因此，宽度量化是常规多栅FinFET器件的内在限制因素。
发明内容
根据示例性实施例，一种半导体器件包括衬底，其沿着第一方向延伸以限定衬底长度，并沿着与所述第一方向垂直的第二方向延伸以限定衬底宽度。第一半导体鳍形成于所述衬底的上表面上。所述第一半导体鳍沿着所述第二方向延伸第一距离以限定第一鳍宽度。第一栅极沟道形成于在所述衬底中形成的第一源/漏结与在所述第一半导体鳍中形成的第二源/漏结之间。第一栅极叠层形成于所述第一栅极沟道的侧壁上。第一间隔物(spacer)被设置在所述第一栅极叠层与所述第一源/漏结之间。
根据另一示例性实施例，一种制造半导体器件的方法包括形成衬底，该衬底沿着第一方向延伸以限定衬底长度并沿着与所述第一方向垂直的第二方向延伸以限定衬底宽度。所述方法进一步包括在所述衬底的上表面上形成第一半导体鳍。所述第一半导体鳍沿着所述第二方向延伸第一距离以限定第一鳍宽度。所述方法进一步包括在形成于所述衬底中的第一源/漏结与形成于所述第一半导体鳍中的第二源/漏结之间形成第一栅极沟道。所述方法进一步包括在所述第一源/漏结的上表面上形成第一间隔物。所述方法进一步包括在所述第一间隔物上和所述第一栅极沟道的侧壁上形成第一栅极叠层，以便所述第一间隔物被设置在所述第一栅极叠层与所述第一源/漏结之间。
附图说明
在本说明书结尾处的权利要求书中被具体指明并且明确地要求保护被视为本发明的主题。通过结合附图进行的以下详细描述，本发明的上述及其它特征将变得明显。图1-15B示例出制造半导体器件的流程，其中：
图1是常规FinFET半导体器件的等距视图；
图2是根据示例性实施例的起始衬底的截面图；
图3是在起始衬底的上表面沉积硬掩模层的掩蔽沉积工艺之后的图2所示的起始衬底的截面图；
图4是在硬掩模层的上表面上沉积芯(mandrel)层的芯沉积工艺之后的图3所示的衬底的截面图；
图5A是在图案化(pattern)芯层以形成各单独的(individual)芯之后、以及在每个芯的相反侧形成间隔物之后的图4所示的衬底的截面图；
图5B是图5A所示的衬底的等距视图，示例出沿着衬底宽度延伸的间隔物和芯；
图6是在从间隔物之间去除芯的抽芯工艺之后的图5A和5B所示的衬底的截面图；
图7是在蚀刻硬掩模层和下伏的(underlying)衬底以形成各单独的半导体鳍的蚀刻工艺之后的图6所示的衬底的截面图；
图8A是从每个半导体鳍的上表面去除间隔物之后的图7所示的衬底的截面图；
图8B是图8A所示的衬底的等距视图，示出了所述半导体鳍沿着衬底宽度延伸不同的长度以限定彼此不同的鳍宽度；
图9是在沉积阻隔掩模(block mask)的阻隔掩模沉积工艺之后的图8A和8B所示的衬底的截面图，该阻隔掩模覆盖衬底和半导体鳍的暴露部；
图10是在使单个半导体鳍和一部分衬底暴露的选择性图案化工艺之后的图9所示的衬底的截面图；
图11是正在经历将掺杂离子注入一部分暴露的衬底和一部分暴露的半导体鳍的离子注入工艺的图10所示的衬底的截面图；
图12是示例出在离子注入工艺之后在暴露的衬底和暴露的半导体鳍中形成源/漏结的图11所示的衬底的截面图；
图13A是在选择性图案化和离子注入工艺以形成在衬底的剩余部分和剩余的半导体鳍上具有变化的深度的源/漏结之后的图12所示的衬底的截面图；
图13B是图13A所示的衬底的等距视图，示出了沿着衬底宽度和鳍宽度延伸的源/漏结；
图14是在衬底的上表面以及半导体鳍的上表面和侧壁上沉积保形(conformal)间隔物层之后的图13A-13B所示的衬底的等距视图；
图15是蚀刻保形间隔物层以在半导体鳍的栅极沟道和衬底的源/漏结上形成间隔物之后的图14所示的衬底的等距视图；
图16A示例出在沉积多晶硅阻隔层之后的图15的衬底，该多晶硅阻隔层覆盖半导体鳍和衬底的暴露部分；
图16B是图16A所示的衬底的等距视图，示例出沿着衬底宽度延伸的多晶硅阻隔层；
图17A是在图案化多晶硅阻隔层以在栅极沟道的相应侧壁上和相应间隔物的上表面上形成各单独的栅极叠层的图案化工艺之后的图16A和16B所示的衬底的等距视图；以及
图17B是图17A所示的衬底的等距视图，示例出沿着鳍宽度延伸并且位于相应栅极叠层与源/漏结之间的间隔物。
具体实施方式
参考图2，半导体结构100包括体(bulk)半导体衬底102，该衬底沿着X轴延伸以限定高度，并且沿着与X轴垂直的Y轴延伸以限定长度。体半导体衬底102可由诸如硅(Si)的半导体材料形成。
转向图3，在体半导体衬底102的上表面上形成硬掩模层103。硬掩模层103可使用化学气相沉积(CVD)形成，并且可由氮化物掩模材料形成，如本领域的普通技术人员可理解的。
参考图4，在硬掩模层103的上表面上形成芯层104。芯层104可通过氧化硅(SiO2)的CVD形成。进一步地，芯层104可由成分不同于硬掩模层103的材料形成以实现蚀刻选择性。芯层104的材料包括但不限于光致抗蚀剂、多晶硅、氧化硅、氮化硅和硅锗。
现在参考图5，对芯层104进行图案化以形成多个单独的芯106。芯层104的一个或多个部分可使用包括但不限于光刻的各种工艺而被图案化，从而形成一个或多个沟槽108。相应地，每个单独的芯106通过沟槽108而彼此分隔。芯层104也可被图案化以调整单独的芯106中的一个或多个的沿着Z轴延伸的宽度，如图5B所示。每个芯106的图案化宽度可限定要在半导体器件100上形成的相应鳍的宽度，如下面将更详细地讨论的。在每个单独的芯106的侧面处形成间隔物107。间隔物可使用光刻工艺和侧壁图像转印(SIT)工艺形成，如本领域的普通技术人员可理解的。
现在转向图6，执行去除单独的芯106的抽芯工艺。抽芯工艺在各单独的间隔物107之间产生另外的沟槽108。
参考图7，各单独的间隔物107可被用于在体半导体衬底102中蚀刻出鳍沟槽110。鳍沟槽110可使用本领域的普通技术人员理解的SIT工艺形成。蚀刻出的鳍沟槽110限定一个或多个半导体鳍112′-112″″。由于鳍112′-112″″被图案化到体半导体衬底102中，因此，鳍112′-112″″和体半导体衬底102由同一材料(例如Si)形成。
转向图8A，各单独的间隔物107可被去除，从而暴露在相应的鳍112′-112″″的上表面上形成的各单独的硬掩模帽103′-103″″。硬掩模帽103可具有例如大约3纳米(nm)到5nm的厚度。可执行各种工序以去除间隔物107，其中包括但不限于蚀刻化学工艺。鳍112′-112″″沿着Z轴延伸以限定鳍宽度(wFIN)，如图8B所示。鳍112′-112″″中的一个或多个的wFIN可根据相应的间隔物107的宽度而被限定。因此，一个鳍112′-112″″的wFIN可相对于其余的鳍112′-112″″而被调整。参考图8B，例如，第一鳍112′的wFIN可小于第二鳍112″″的wFIN。因此，半导体器件100可被形成为具有灵活可调的鳍宽度设计的多栅FinFET。
除了调整鳍112′-112″″中的一个或多个的wFIN之外，也可通过形成具有变化的深度的源(S)结和漏(D)结来调整半导体器件100的栅极长度。在图9-17B中示例出并且在下面更详细地讨论形成具有变化的栅极长度和S/D结深度的多栅FinFET的工艺流程。
现在参考图9，对图8A-8B所示的半导体器件100进行掩模沉积处理，此处理沉积阻隔掩模114，所述阻隔掩模114覆盖沟槽110和鳍112′-112″″。阻隔掩模114被配置为阻隔掺杂离子，防止掺杂离子穿透阻隔掩模并到达下伏的体半导体衬底102和鳍112′-112″″的半导体材料。根据至少一个示例性实施例，阻隔掩模114可由本领域的普通技术人员理解的各种可选择进行光刻图案化的材料形成。
转向图10，阻隔掩模114的一部分被图案化以暴露第一鳍112′和第一半导体衬底部102′。可使用各种公知的光刻工艺来图案化阻隔掩模114。因此，仅暴露单个鳍112′和选定的半导体衬底部102′，而其余的鳍112″-112″″和其余的体半导体衬底102仍被阻隔掩模114覆盖。
现在参考图11，对半导体器件100应用离子注入工艺以形成源/漏(S/D)结。这些离子可穿透硬掩模帽103并且可根据自对准的0度离子注入工艺而被注入。然而，应该理解，这些离子可以倾斜地被注入以更精确地形成最终的S/D结。也可调整离子源的能量水平以使离子在暴露的第一鳍112′和第一半导体衬底部102′中的注入深度变化。为离子注入工艺选择的离子可根据体半导体衬底102和鳍112′-112″″的掺杂类型而被选择。例如，如果体半导体衬底102和鳍112′-112″″被掺有P型材料(例如，磷)，则这些离子可以是N型离子(例如，硼)以形成N型S/D结(即，NFET)。然而，如果体半导体衬底102和鳍112′-112″″被掺有N型材料(例如，硼)，则这些离子可以是P型离子(例如，磷)以形成P型S/D结(即，PFET)。
如图12所示，离子注入工艺形成对应于第一鳍112′的源结116′和漏结118′。本领域的普通技术人员将理解，源结116′和漏结118′的位置可互换。如图12进一步所示，源结116′和漏结118′具有第一深度水平，该第一深度水平根据被选择用于执行对应的离子注入工艺的能量水平而形成。与常规FinFET器件(其形成将相对于彼此在同一平面内的源(S)结和漏(D)结，参见图1)不同，本发明的至少一个示例性实施例提供相对于彼此垂直偏移的源结116和漏结118。
现在转向图13A和13B，示例出在多个离子注入工艺以形成对应于每个鳍112′-112″″的源结116′-116″″和漏结118′-118″″之后的半导体器件100。本领域的普通技术人员将理解，对应于每个鳍112′-112″″的S/D结可通过执行上面详细描述的多个阻隔掩模沉积和阻隔掩模图案化工序(未示出)来形成。每个阻隔掩模沉积和图案化工序选择性地暴露单个鳍和对应的半导体衬底部102′，所述暴露的单个鳍和对应的半导体衬底部102′根据上面详细描述的离子注入工艺被注入离子。如图13A-13B进一步所示，每个离子注入工艺的能量水平可变化，从而形成具有彼此不同的深度水平的S/D结。例如，第一鳍112′的源结116′和漏结118′具有比第三鳍112″′的源结116″′和漏结118″′的深度水平浅的第一深度水平。
也可利用掺杂的S/D结中的一个或多个作为隔离结，该隔离结将相邻的鳍彼此电隔离和/或将相邻的鳍与体半导体衬底102的其余部分电隔离以限定栅极沟道。仍参考图13A-13B，例如，在体半导体衬底102中形成隔离区120。
仍参考图13A-13B，每个S/D结限定相应的栅极沟道122′-122″″。常规多栅FinFET形成这样的栅极沟道：该栅极沟道的栅极长度平行延伸(即，沿着X轴水平地延伸)并且与S/D结在同一平面内(参见图1)。与常规多栅FinFET不同，本发明的至少一个实施例提供这样的栅极沟道122′-122″″：所述栅极沟道的沟道长度沿着Y轴垂直地延伸。因此，与常规多栅FinFET器件(其形成在源(S)结与漏(D)结之间平行且在同一平面内的栅极沟道，参见图1)不同，本发明的至少一个实施例形成这样的栅极沟道122′-122″″：所述栅极沟道122′-122″″相对于源结116′-116″″和漏结118′-118″″中的至少一者不在同一平面内，且垂直地延伸。
如图13A-13B进一步所示，每个栅极沟道122′-122″″的长度(lGATE)由相应的源结116′-116″″和漏结118′-118″″的深度水平限定。也就是说，本发明的至少一个实施例提供具有可调lGATE的多栅FinFET。因此，栅极沟道长度与鳍高度无关，从而可通过反馈偏压(back biasing)实现所需的电压阈值(Vt)偏移。尽管图13A-13B所示的半导体器件100示出由共同的掺杂材料形成的栅极沟道122，但是将理解，栅极沟道中的一个或多个可被隔离以形成由不同的掺杂材料形成的栅极沟道。例如，第一栅极沟道可被隔离并且形成为N型半导体材料以提供PFET器件，而相邻的栅极沟道可形成为P型半导体材料以提供NFET器件。可使用本领域的普通技术人员理解的例如离子注入形成各种类型的半导体材料。
现在参考图14，在半导体衬底102的上表面以及半导体鳍112′-112″″的上表面和侧壁上沉积保形间隔物层123。保形间隔物层123可由各种材料形成，其中包括但不限于氮化硅(SiN)、含硼的碳化硅(SiBCN)和含氧的碳化硅(SiOCN)。
现在参考图15，保形间隔物层123被蚀刻以在半导体衬底102的源结116′-116″″和漏结118′-118″″上形成间隔物125。一部分间隔物125也形成在半导体鳍112′-112″″的相应栅极沟道122′-122″″上。尽管图15示例出仅在相应栅极沟道122′-122″″的侧壁上形成且沿着相应鳍112′-112″″的宽度延伸的间隔物125，但是将理解，保形间隔物层123可被蚀刻以使得间隔物125在相应栅极沟道122′-122″″的所有侧面上形成。
现在参考图16A-16B，在半导体结构100的上表面上沉积多晶硅阻隔层124。多晶硅阻隔层124可覆盖栅极沟道122′-122″″、源结116′-116″″、漏结118′-118″″、隔离区120、以及鳍112′-112″″。此外，多晶硅阻隔层124的一部分通过相应间隔物125而与源/漏结分隔。多晶硅阻隔层124可由本领域的普通技术人员理解的各种被配置为形成一个或多个栅极叠层的多晶硅材料形成。将理解，可执行中间工艺以在沉积多晶硅阻隔层124之前，在每个栅极沟道122′-122″″的侧壁上形成高k电介质层和金属栅极层。将理解，至少一个实施例可包括在沉积多晶硅阻隔层124之前，在每个栅极沟道122′-122″″的侧壁上形成高k电介质层和金属栅极层。
转向图17A-17B，对多晶硅阻隔层124进行图案化以形成各单独的栅极叠层126′-126″″。每个栅极叠层126′-126″″对应于相应的鳍112′-112″′。本领域的普通技术人员将理解，可使用各种栅极叠层图案化工艺形成各单独的栅极叠层126′-126″″。将理解，高k电介质层和金属栅极层可被设置在每个栅极沟道122′-122″″与相应的栅极叠层126′-126″″之间。
如图17A-17B进一步所示，每个间隔物125被设置在相应的栅极叠层126′-126″″与在衬底102中形成的相应结116′-116″″之间。间隔物125的厚度(即，沿着Y轴方向延伸的距离)的范围可以为例如从大约3纳米(nm)到大约5nm。在此方面，有效电介质区域在栅极叠层126′-126″″与形成于衬底102中的相应结116′-116″″之间增加。因此，栅极沟道122′-122″″与形成于半导体衬底102中的相应结116′-116″″之间的电容耦合可减小。
如图17A-17B所示，半导体器件100可形成为这样的多栅FinFET：其所包括的至少一个鳍112′-112″″具有的鳍宽度(wFIN)不同于一个或多个其余的鳍112′-112″″的wFIN。因此，与向半导体器件添加另外的半导体鳍结构相反，半导体器件100所提供的驱动电流可通过调整一个或多个鳍112′-112″″的wFIN而被更精确地控制。尽管图17A和17B示例出在相应栅极沟道122′-122″″的侧壁上形成且沿着相应鳍112′-112″″的宽度延伸的栅极叠层126′-126″″，但是将理解，多晶硅阻隔层124可被蚀刻为使得栅极叠层126′-126″″在相应栅极沟道122′-122″″的所有侧面上形成。
如图17A-17B进一步所示的那样，半导体器件100可形成为这样的多栅FinFET：该多栅FinFET包括至少一个栅极沟道122′-122″″，所述至少一个栅极沟道122′-122″″的栅极长度(lGATE)不同于一个或多个其余的栅极沟道122′-122″″的栅极长度。因此，与常规多栅FinFET(其中电流沿着平面方向且平行于源(S)和漏(D)之间的栅极沟道流动)不同，在半导体器件100所形成的多栅FinFET中流动的电流(i)沿着非平面方向流动。例如，该电流可源自第一源结116′，并且垂直地流动通过第一栅极沟道122′，以便该电流被第一漏结118′收集。因此，与常规多栅FinFET器件(其使电流沿着与鳍112′-112″″的宽度垂直的衬底长度在平面方向上流动，参见图1)不同，半导体器件100使电流沿着非平面方向垂直地流动。
本文中所用的术语，仅仅是为了描述特定的实施例，而不意图限定本发明。本文中所用的单数形式的“一”和“该”，旨在也包括复数形式，除非上下文中明确地另行指出。还要知道，“包含”一词在本说明书中使用时，说明存在所指出的特征、整体、步骤、操作、单元和/或组件，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元组件，以及/或者它们的组合。
下面的权利要求中的所有装置或步骤加功能要素的对应结构、材料、动作和等价物旨在包括用于与具体地要求保护的其他要求保护的要素组合地执行功能的任何结构、材料或动作。本发明的说明书是为了示例和说明的目的而给出的，而不旨在以所公开的形式穷举或限制本发明。只要不脱离本发明的范围和精神，多种修改和变化对于本领域的普通技术人员而言是显而易见的。为了最好地解释本发明的原理和实际应用，且为了使本领域的其他普通技术人员能够理解本发明的具有适于所预期的特定用途的各种修改的各种实施例，选择和描述了实施例。
本文中示出的流程图只是一个实例。本文中描述的该图或步骤(或操作)可以存在许多变型而不偏离本发明的精神。例如，可以按不同的顺序执行所述步骤，或者可以添加、删除或修改步骤。所有这些变型都被视为要求保护的发明的一部分。
尽管已经描述了本发明的优选实施例，但是将理解，本领域的技术人员现在和将来都可做出落在下面的权利要求的范围内的各种改进和增强。这些权利要求应该被视为保持对首先描述的本发明的适当保护。

Claims (15)

1.一种半导体器件，包括：
衬底，其沿着第一方向延伸以限定衬底长度，并沿着与所述第一方向垂直的第二方向延伸以限定衬底宽度；
第一半导体鳍，其形成于所述衬底的上表面上，所述第一半导体鳍沿着所述第二方向延伸第一距离以限定第一鳍宽度；
第一栅极沟道，其形成于在所述衬底中形成的第一源/漏结与在所述第一半导体鳍中形成的第二源/漏结之间；
第一栅极叠层，其形成于所述第一栅极沟道的侧壁上；以及
第一间隔物，其被设置在所述第一栅极叠层与所述第一源/漏结之间。
2.根据权利要求1所述的半导体器件，进一步包括：
第二半导体鳍，其形成于所述衬底的所述上表面上，所述第二半导体鳍沿着所述第二方向延伸不同于所述第一距离的第二距离以控制所述半导体器件的驱动电流流动；
第二栅极沟道，其形成于在所述衬底中形成的第三源/漏结与在所述第二半导体鳍中形成的第四源/漏结之间，
第二栅极叠层，其形成于所述第二栅极沟道的侧壁上；以及
第二间隔物，其被设置在所述第二栅极叠层与所述第三源/漏结之间，所述第一间隔物被配置为减小所述第一栅极沟道与所述第一源/漏结之间的电容耦合，所述第二间隔物被配置为减小所述第二栅极沟道与所述第三源/漏结之间的电容耦合。
3.根据权利要求2所述的半导体器件，其中，所述第一鳍宽度小于所述第二鳍宽度。
4.根据权利要求2所述的半导体器件，其中，所述第一鳍宽度大于所述第二鳍宽度。
5.根据权利要求2所述的半导体器件，其中，所述第一和第二栅极沟道中的至少一者与至少一个相应的源/漏结不在同一平面内。
6.根据权利要求5所述的半导体器件，其中，所述第一栅极沟道具有第一栅极长度，并且所述第二栅极沟道具有不同于所述第一栅极长度的第二栅极长度。
7.根据权利要求6所述的半导体器件，其中，所述第二源/漏结以第一深度被注入所述第一半导体鳍的上表面中以限定所述第一栅极长度，并且所述第四源/漏结以不同于所述第一深度的第二深度被注入所述第二半导体鳍的上表面中以限定所述第二栅极长度。
8.一种制造半导体器件的方法，所述方法包括：
形成衬底，该衬底沿着第一方向延伸以限定衬底长度并沿着与所述第一方向垂直的第二方向延伸以限定衬底宽度；
在所述衬底的上表面上形成第一半导体鳍，所述第一半导体鳍沿着所述第二方向延伸第一距离以限定第一鳍宽度；
在形成于所述衬底中的第一源/漏结与形成于所述第一半导体鳍中的第二源/漏结之间形成第一栅极沟道；
在所述第一源/漏结的上表面上形成第一间隔物；以及
在所述第一间隔物上和所述第一栅极沟道的侧壁上形成第一栅极叠层，以便所述第一间隔物被设置在所述第一栅极叠层与所述第一源/漏结之间。
9.根据权利要求8所述的方法，进一步包括：
在所述衬底的所述上表面上形成第二半导体鳍，所述第二半导体鳍沿着所述第二方向延伸不同于所述第一距离的第二距离；
在形成于所述衬底中的第三源/漏结与形成于所述第二半导体鳍中的第四源/漏结之间形成第二栅极沟道，
在所述第三源/漏结的上表面上形成第二间隔物；以及
在所述第二间隔物上和所述第二栅极沟道的侧壁上形成第二栅极叠层，以便所述第二间隔物被设置在所述第二栅极叠层与所述第三源/漏结之间，所述第一间隔物被配置为减小所述第一栅极沟道与所述第一源/漏结之间的电容耦合，所述第二间隔物被配置为减小所述第二栅极沟道与所述第三源/漏结之间的电容耦合。
10.根据权利要求9所述的方法，进一步包括通过相对于所述第二半导体鳍的所述第二鳍宽度改变所述第一半导体鳍的所述第一鳍宽度来控制流过所述半导体器件的驱动电流。
11.根据权利要求10所述的方法，进一步包括将所述第一鳍宽度形成为小于所述第二鳍宽度。
12.根据权利要求10所述的方法，进一步包括将所述第一鳍宽度形成为大于所述第二鳍宽度。
13.根据权利要求10所述的方法，其中，所述第一和第二栅极沟道中的至少一者与至少一个相应的源/漏结不在同一平面内。
14.根据权利要求13所述的方法，进一步包括将所述第一栅极沟道形成为具有第一栅极长度，并且将所述第二栅极沟道形成为具有不同于所述第一栅极长度的第二栅极长度。
15.根据权利要求14所述的方法，进一步包括以第一深度将所述第二源/漏结注入所述第一半导体鳍的上表面中以限定所述第一栅极长度，并且以不同于所述第一深度的第二深度将所述第四源/漏结注入所述第二半导体鳍的上表面中以限定所述第二栅极长度。
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