CN105990149A - 一种制作半导体元件的方法 - Google Patents

一种制作半导体元件的方法 Download PDF

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CN105990149A
CN105990149A CN201510093659.0A CN201510093659A CN105990149A CN 105990149 A CN105990149 A CN 105990149A CN 201510093659 A CN201510093659 A CN 201510093659A CN 105990149 A CN105990149 A CN 105990149A
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林建廷
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United Microelectronics Corp
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Abstract

本发明公开一种制作半导体元件的方法。首先提供一基底，该基底上具有一第一区域、一第二区域以及一第三区域，然后形成多个鳍状结构于该第一区域、该第二区域及该第三区域上。接着进行一第一鳍状结构切割(fin-cut)制作工艺，以在第一区域形成一第一鳍状结构、在第二区域形成一第二鳍状结构以及于第三区域形成一第三鳍状结构，其中第一鳍状结构的高度不同于第二鳍状结构及该第三鳍状结构的高度。之后再进行一第二鳍状结构切割制作工艺以降低第三鳍状结构的高度。

Description

一种制作半导体元件的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种利用两次鳍状结构切割(fin-cut)制作工艺以形成不同鳍状结构高度的方法。
背景技术
随着半导体元件尺寸的缩小，维持小尺寸半导体元件的效能是目前业界的主要目标。然而，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。非平面(non-planar)式场效晶体管元件,例如鳍状场效晶体管(fin field effecttransistor,FinFET)元件，具有立体结构可增加与栅极之间接触面积，进而提升栅极对于通道区域的控制，俨然已取代平面式场效晶体管成为目前的主流发展趋势。
现有鳍状场效晶体管的制作工艺是先将鳍状结构形成于基底上,再将栅极形成于鳍状结构上。鳍状结构一般为蚀刻基底所形成的条状鳍片，但在尺寸微缩的要求下，各鳍片宽度渐窄，而鳍片之间的间距也渐缩小。因此，其制作工艺也面临许多限制与挑战，例如现有掩模及光刻蚀刻技术受限于微小尺寸的限制，无法准确定义鳍状结构的位置而造成鳍片倒塌，或是无法准确控制蚀刻时间而导致过度蚀刻等问题，连带影响鳍状结构的作用效能。
发明内容
本发明优选实施例是揭露一种制作半导体元件的方法。首先提供一基底，该基底上具有一第一区域、一第二区域以及一第三区域，然后形成多个鳍状结构于该第一区域、该第二区域及该第三区域上，进行一第一鳍状结构切割(fin-cut)制作工艺，以在第一区域形成一第一鳍状结构、在第二区域形成一第二鳍状结构以及于第三区域形成一第三鳍状结构，其中第一鳍状结构的高度不同于第二鳍状结构及该第三鳍状结构的高度。之后再进行一第二鳍状结构切割制作工艺以降低第三鳍状结构的高度。
本发明另一实施例公开一种半导体元件，其包含一基底，该基底上具有一第一区域、一第二区域以及一第三区域；以及一第一鳍状结构设于第一区域，一第二鳍状结构设于第二区域以及一第三鳍状结构设于第三区域，其中第一鳍状结构、第二鳍状结构及第三鳍状结构具有不同高度。
附图说明
图1至图5为本发明优选实施例制作一半导体元件的方法示意图。
主要元件符号说明
12 基底 14 第一区域
16 第二区域 18 第三区域
20 衬垫氧化层 22 衬垫氮化层
24 氧化层 26 鳍状结构
30 浅沟隔离 32 图案化掩模
34 图案化掩模
具体实施方式
请参照图1至图5，图1至图5为本发明优选实施例制作一半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底，且基底12上定义有一第一区域14、一第二区域16以及一第三区域18。在本实施例中，第一区域14优选为一用来制作实际所需元件的区域，因此在此区域所形成的鳍状结构上于后续制作工艺中会依据制作工艺需求形成例如栅极结构等元件，第二区域16与第三区18域则定义为虚置区域，因此后续于这两个区域中所形成的鳍状结构仅为虚置鳍状结构。
然后依序形成一硬掩模于基底12上，硬掩模可为单一材料层或多层结构，例如可包含一衬垫氧化层20、一衬垫氮化层22以及一氧化层24，接着先形成一图案化掩模(图未示)于氧化层24上，再进行一蚀刻制作工艺去除部分氧化层24、部分衬垫氮化层22、部分衬垫氧化层20以及部分基底12，将图案化掩模的图案转移至基底12中以于第一区域14、第二区域16及第三区域18形成多个鳍状结构26。在本实施例中，第一区域14的鳍状结构26以两根为例，第二区域16的鳍状结构26以一根为例，第三区域18的鳍状结构26以三根为例，但鳍状结构26于各区域的数量并不局限于此，而可视制作工艺需求任意调整。
除此之外，鳍状结构26又可通过侧壁图案转移(sidewall image transfer,SIT)技术制得，其程序大致包括：提供一布局图案至电脑系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至氧化层、衬垫氮化层、衬垫氧化层以及基底内而获得所需的鳍状结构。需注意的是，此时鳍状结构优选为圈状图案的鳍状结构而非条状图案的鳍状结构。
接着进行一第一鳍状结构切割制作工艺(first fin-cut process)，例如先形成一由图案化光致抗蚀剂所构成的图案化掩模32于第一区域14上并覆盖部分鳍状结构26，然后进行一蚀刻制作工艺去除第一区域14的部分鳍状结构26、第二区域16的部分鳍状结构26及第三区域26的部分鳍状结构26，使第一区域14内的圈状图案的鳍状结构26被切割成多条彼此独立且具条状图案的鳍状结构26，并蚀刻第二区域16内所有的鳍状结构26及第三区域18内所有的鳍状结构26，使第二区域16的鳍状结构26及第三区域18的鳍状结构26高度低于第一区域14的鳍状结构26高度，其中第二区域16的鳍状结构26高度又约略等于第三区域18的鳍状结构26高度。
如图2所示，接着去除图案化掩模32并进行第二鳍状结构切割制作工艺，例如先形成另一图案化掩模34于第一区域14及第二区域16上，接着再进行一蚀刻制作工艺去除第三区域18的部分鳍状结构26，使第三区域18的鳍状结构26高度低于第一区域14与第二区域16的鳍状结构26高度。
需注意的是，依据本发明的一实施例，如图3所示，本发明进行前述第二鳍状结构切割制作工艺时又可依据制作工艺需求调整第三区域18中鳍状结构26与基底12的高度，例如可利用蚀刻降低第三区域18的鳍状结构26高度后继续往下蚀刻去除部分基底12，使第三区域18的基底12表面低于第一区域14及第二区域16的基底12表面，甚至第三区域18的基底12及鳍状结构26两者均低于第一区域14及第二区域16的基底12表面，此实施例也属本发明所涵盖的范围。
此外，相较于前述实施例将第二区域16设于紧邻第一区域14，如图4所示，本发明另一实施例又可将第三区域18设于紧邻第一区域14而第二区域16设于第三区域18旁，如此依据前述依序进行两次鳍状结构切割制作工艺后紧邻第一区域14的第三区域18的鳍状结构26高度将同时低于第一区域14与第二区域16的鳍状结构26高度。
之后如图5所示，可进行一浅沟隔离制作工艺，例如先形成一由氧化硅所构成的绝缘层(图未示)于基底12上并覆盖第一区域14、第二区域16及第三区域18的鳍状结构26，然后进行一CMP及/或蚀刻制作工艺，去除部分绝缘层以形成一浅沟隔离30，且浅沟隔离30的上表面优选低于第一区域14的鳍状结构26顶部但完全覆盖第二区域16与第三区域18的鳍状结构26，亦即只有第一区域14的鳍状结构26突出于浅沟隔离30。随后可依据制作工艺需求进行一般鳍状晶体管元件或nanowire的制作，例如可于第一区域14的鳍状结构26上形成栅极结构以及于栅极结构两侧的基底12中形成源极/漏极区域等。至此即完成本发明优选实施例的半导体元件的制作。此外，在进行浅沟隔离制作工艺之前，也可先于第一区域14、第二区域16及第三区域18的鳍状结构26表面形成一由例如氧化硅所构成的衬垫层(图未示)。另外，去除硬掩模(包含衬垫氧化层20、衬垫氮化层22及氧化层24)的时间点可实施于第一鳍状结构切割制作工艺、第二鳍状结构切割制作工艺与浅沟隔离制作工艺等步骤之前、之间或之后。
请再参照图5，图5另揭露一种半导体元件结构。如图5所示，本发明的半导体元件主要包含一基底12、一第一区域14、一第二区域16以及一第三区域18定义于基底12上以及多个鳍状结构26设于第一区域14、第二区域16及第三区域18，其中第一区域14、第二区域16与第三区域18的鳍状结构26均具有不同高度。
更具体而言，第二区域16与第三区域18的鳍状结构26高度均低于第一区域14的鳍状结构26，而第三区域18的鳍状结构26高度又低于第二区域16的鳍状结构26高度。另外基底12上又设有一浅沟隔离30，其中浅沟隔离30的上表面优选低于第一区域14的鳍状结构26顶表面但完全覆盖第二区域16与第三区域18的鳍状结构26。
综上所述，本发明主要于基底上形成鳍状结构后依序进行两次鳍状结构切割(fin-cut)制作工艺，使基底上不同区域的鳍状结构可具有不同高度。更具体而言，第一次鳍状结构切割制作工艺优选将基底上的鳍状结构分隔为两种高度，而第二次鳍状结构切割制作工艺则再次将部分鳍状结构的高度降低，使基底上的鳍状结构可具有至少三种不同高度。依此制作工艺手段本发明可于鳍状结构制作过程中避免基底上产生过多残余物或对非虚置的鳍状结构造成损害。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (10)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底上具有第一区域、第二区域以及第三区域；
形成多个鳍状结构于该第一区域、该第二区域及该第三区域上；
进行一第一鳍状结构切割(fin-cut)制作工艺，以在该第一区域形成一第一鳍状结构、在该第二区域形成一第二鳍状结构以及于该第三区域形成一第三鳍状结构，其中该第一鳍状结构的高度不同于该第二鳍状结构及该第三鳍状结构的高度；以及
进行一第二鳍状结构切割制作工艺以降低该第三鳍状结构的高度。
2.如权利要求1所述的方法，其中该第一鳍状结构切割制作工艺包含：
形成一图案化掩模于该第一区域上；以及
进行一蚀刻制作工艺去除部分该第二鳍状结构及部分该第三鳍状结构以使该第二鳍状结构及该第三鳍状结构的高度低于该第一鳍状结构的高度。
3.如权利要求2所述的方法，其中该第二鳍状结构的高度等于该第三鳍状结构的高度。
4.如权利要求1所述的方法，其中该第二鳍状结构切割制作工艺包含：
形成一图案化掩模于该第一区域及该第二区域上；以及
进行一蚀刻制作工艺去除部分该第三鳍状结构以使该三鳍状结构的高度低于该第一鳍状结构及该第二鳍状结构的高度。
5.如权利要求1所述的方法，还包含形成一浅沟隔离于该基底上并覆盖该第二鳍状结构及该第三鳍状结构。
6.如权利要求5所述的方法，其中该浅沟隔离的上表面低于该第一鳍状结构的上表面。
7.一种半导体元件，包含：
基底，该基底上具有第一区域、第二区域以及第三区域；以及
一第一鳍状结构设于该第一区域，一第二鳍状结构设于该第二区域以及一第三鳍状结构设于该第三区域，其中该第一鳍状结构、该第二鳍状结构及该第三鳍状结构具有不同高度。
8.如权利要求7所述的半导体元件，其中该第二鳍状结构及该第三鳍状结构的高度低于该第一鳍状结构的高度。
9.如权利要求7所述的半导体元件，还包含形成一浅沟隔离于该基底上并覆盖该第二鳍状结构及该第三鳍状结构。
10.如权利要求9所述的半导体元件，其中该浅沟隔离的上表面低于该第一鳍状结构的上表面。
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