CN104716185B - 具有经优化源极侧阻挡能力的高电压横向dmos晶体管 - Google Patents

具有经优化源极侧阻挡能力的高电压横向dmos晶体管 Download PDF

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CN104716185B
CN104716185B CN201410788510.XA CN201410788510A CN104716185B CN 104716185 B CN104716185 B CN 104716185B CN 201410788510 A CN201410788510 A CN 201410788510A CN 104716185 B CN104716185 B CN 104716185B
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chain
region
diffusion
channel
isolation
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CN104716185A (zh
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菲利普·利兰·豪尔
萨米尔·彭德哈卡
马里·丹尼森
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请案涉及具有经优化源极侧阻挡能力的高电压横向DMOS晶体管。一种集成电路及方法具有延伸漏极MOS晶体管，所述延伸漏极MOS晶体管具有掩埋漂移区、漏极扩散链、沟道扩散链及将源极电隔离的隔离链，其中所述隔离扩散链是通过穿过经分段区域进行植入以将掺杂稀释到小于所述漏极扩散链中的掺杂的三分之二而形成。

Description

具有经优化源极侧阻挡能力的高电压横向DMOS晶体管
技术领域
本发明涉及集成电路的领域。更特定来说，本发明涉及集成电路中的MOS晶体管。
背景技术
集成电路可含有具有掩埋漂移区的平面延伸漏极金属氧化物半导体(MOS)晶体管，举例来说，以提供高于所述MOS晶体管中的栅极电介质层的介电强度的操作电压。可期望形成掩埋漂移区与漏极触点之间的低电阻漏极部分连接、掩埋漂移区与MOS晶体管的沟道之间的经轻掺杂沟道部分链及掩埋漂移区与集成电路的衬底的顶部表面之间的经轻掺杂隔离链，所述经轻掺杂隔离链将MOS晶体管的源极及主体与衬底电隔离。可进一步期望最小化在形成集成电路的制作序列中的光刻及离子植入操作的数目。
发明内容
下文呈现简化发明内容以便提供对本发明的一或多个方面的基本理解。本发明内容并非本发明的广泛概述，且既不打算识别本发明的关键或紧要元件，也不打算记述其范围。而是，本发明内容的主要目的为以简化形式呈现本发明的一些概念作为稍后所呈现的更详细说明的前言。
一种集成电路可包含平面延伸漏极MOS晶体管，所述平面延伸漏极MOS晶体管具有在所述MOS晶体管的漏极触点与沟道之间的掩埋漂移区。掩埋漂移区与漏极触点之间的漏极部分链与掩埋漂移区与沟道之间的沟道部分链及掩埋漂移层与集成电路的衬底的顶部表面之间的隔离链同时形成。所述隔离链将延伸漏极MOS晶体管的源极扩散区及主体区与所述衬底电隔离。所述漏极部分链、沟道部分链及隔离链是通过离子植入掺杂剂、后续接着进行退火操作而形成，所述退火操作使经植入掺杂剂扩散以与所述掩埋漂移区进行电连接。所述隔离链中的平均掺杂密度小于所述漏极部分链中的平均掺杂密度的三分之二。通过以下操作来形成所述隔离链：将经离子植入区域分段以使得在退火操作之后经植入分段的扩散掺杂剂分布在所述隔离链中比在漏极部分链中更稀释。
附图说明
图1A到图1D是根据一实例形成的集成电路的透视图，其描绘连续制作阶段。
图2A及图2B是含有根据第一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘连续制作阶段。
图3A及图3B是含有根据第二实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘连续制作阶段。
图4是含有根据一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其是在形成链离子植入掩模之后描绘的。
图5是含有根据一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其是在形成链离子植入掩模之后描绘的。
具体实施方式
以下共同待决的专利申请案为相关的且特此以引用的方式并入：与本申请案同时申请的美国专利申请案14/xxx，xxx(德州仪器(Texas Instruments)档案号TI-67676)。
参考附图描述本发明，其中贯穿各图使用相似参考编号来指定类似或等效元件。所述图未按比例绘制且其仅被提供以图解说明本发明。下文参考用于图解说明的实例性应用来描述本发明的数个方面。应理解，陈述了众多特定细节、关系及方法以提供对本发明的理解。然而，所属领域的技术人员将容易地认识到，可在不使用所述特定细节中的一或多者或者使用其它方法的情况下实践本发明。在其它实例中，未详细展示众所周知的结构或操作以避免使本发明模糊。本发明不受动作或事件的所图解说明次序限制，这是因为一些动作可以不同次序发生及/或与其它动作或事件同时发生。此外，未必需要所有所图解说明动作或事件来实施根据本发明的方法。
一种集成电路可包含平面延伸漏极MOS晶体管，所述平面延伸漏极MOS晶体管具有在集成电路的衬底中在所述MOS晶体管的漏极触点与沟道之间的掩埋漂移区。通过离子植入及退火而使所述掩埋漂移区与所述漏极触点之间的漏极部分链和所述掩埋漂移区与所述沟道之间的沟道部分链及所述掩埋漂移区与所述衬底的顶部表面之间的隔离链同时形成，所述退火使每一链中的经植入掺杂剂扩散以与所述掩埋漂移区进行电连接。所述隔离链经配置以将所述MOS晶体管的源极扩散区及主体区与衬底电隔离。将隔离链中的离子植入区域分段以使得在退火过程期间掺杂剂横向稀释以与未分段植入区域相比减小平均掺杂密度。在退火操作之后，隔离链中的邻近经植入分段的掺杂剂分布重叠。隔离链中的平均掺杂密度小于漏极部分链中的平均掺杂密度的三分之二。可调整对隔离链的经离子植入区域的分段以提供MOS晶体管的所要击穿电压及串联电阻。
在第一实例中，所述隔离链围绕所述源极扩散区及主体区横向延伸且连接到所述沟道部分链以便将源极扩散区及主体区电隔离。在第二实例中，所述沟道部分链被配置成环绕所述漏极部分链的闭环，且所述隔离链被配置成环绕所述沟道部分链的闭环，以使得所述源极扩散区及主体区位于所述沟道部分链及所述隔离链之间。
出于本说明的目的，术语“实质上相等”在应用于集成电路的特征时应理解为意指在用于形成集成电路的制作公差相等。
图1A到图1D是根据一实例形成的集成电路的透视图，其描绘连续制作阶段。参考图1A，在p型衬底1002中及上形成集成电路1000，p型衬底1002可为单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶体定向的区的混合定向技术(HOT)晶片或适于制作集成电路1000的其它材料。在衬底1002中形成平面延伸漏极n沟道MOS晶体管的n型掩埋漂移区1004。可通过以下操作来形成掩埋漂移区1004：将n型掺杂剂(举例来说，磷)离子植入到衬底1002的现有顶部表面中，后续接着在经植入n型掺杂剂上方生长p型外延半导体材料。在本实例的一个版本中，掩埋漂移区1004的顶部表面在衬底1002中的深度可介于2微米与4微米之间。衬底1002的在掩埋漂移区1004上面的区可在集成电路1000的操作期间提供RESURF区。
在衬底1002的现有顶部表面上方形成链离子植入掩模1006。链离子植入掩模1006可包含光致抗蚀剂及/或电介质层(例如二氧化硅)。链离子植入掩模1006具有在掩埋漂移区1004的漏极部分1010上方的漏极开口区域1008。链离子植入掩模1006具有在掩埋漂移区1004的沟道部分1014上方的多个经分段沟道开口区域1012。链离子植入掩模1006进一步具有在掩埋漂移区1004的隔离部分1018上方的多个经分段隔离开口区域1016。隔离部分1018延伸超过MOS晶体管的随后形成的源极扩散区。在本实例的一个版本中，每一经分段隔离开口区域1016可具有介于1.5微米与3.0微米之间的横向尺寸且以介于4微米与7微米之间的距离间隔开。在本实例的一个版本中，经分段隔离开口区域1016及经分段沟道开口区域1012可具有实质上相等的横向尺寸及间隔。在另一版本中，经分段隔离开口区域1016及经分段沟道开口区域1012可具有不同的横向尺寸及间隔，如图1A中所描绘。在本实例的一个版本中，经分段隔离开口区域1016及经分段沟道开口区域1012可具有如图1A中所描绘的线性配置。在另一版本中，经分段隔离开口区域1016及经分段沟道开口区域1012可具有弯曲配置。
参考图1B，对集成电路1000执行链离子植入操作，所述链离子植入操作同时穿过链离子植入掩模1006的漏极开口区域1008、经分段沟道开口区域1012及经分段隔离开口区域1016将n型掺杂剂(例如磷及可能地砷)离子植入到衬底1002中。在本实例的一个版本中，链离子植入操作可具有介于8×1012cm-2与1.5×1013cm-2之间的剂量。链离子植入操作同时形成在漏极开口区域1008下方的漏极链植入区1020、在经分段沟道开口区域1012下方的沟道链植入区1022及在经分段隔离开口区域1016下方的隔离链植入区1024。在本实例的一个版本中，隔离链植入区1024不彼此触及或重叠。可将所述链离子植入操作作为两个或两个以上子植入以不同能量来执行，举例来说，以提供经植入掺杂剂的较均匀垂直分布。
参考图1C，对集成电路1000执行退火操作，所述退火操作使图1B的漏极链植入区1020中的掺杂剂扩散以形成漏极扩散链1026，漏极扩散链1026在漏极部分1010处延伸到掩埋漂移区1004并与其进行电连接。所述退火操作还使图1B的沟道链植入区1022中的掺杂剂扩散以形成沟道扩散链1028，沟道扩散链1028在沟道部分1014处延伸到掩埋漂移区1004并与其进行电连接。此外，所述退火操作使图1B的隔离链植入区1024中的掺杂剂扩散以形成隔离扩散链1030，隔离扩散链1030在隔离部分1018处延伸到掩埋漂移区1004并与其进行电连接。在本实例的一个版本中，来自邻近隔离链植入区1024的扩散区重叠以形成邻接隔离扩散链1030，如图1C中所描绘。在替代版本中，在来自邻近隔离链植入区1024的扩散区之间可存在间隙，使得在MOS晶体管的操作期间，围绕隔离扩散链1030的扩散区的耗尽区重叠以将MOS晶体管的源极扩散区与衬底1002电隔离。隔离扩散链1030中的平均掺杂密度小于漏极扩散链1026中的平均掺杂密度的三分之二。在本实例的一个版本中，隔离扩散链1030中的平均掺杂密度可介于漏极扩散链1026中的平均掺杂密度的20％与50％之间。在又一版本中，隔离扩散链1030中的平均掺杂密度可介于漏极扩散链1026中的平均掺杂密度的25％与33％之间。在本实例的一个版本中，漏极扩散链1026中的平均掺杂密度可介于2.5×1016cm-3与3.5×1016cm-3之间，且隔离扩散链1030中的平均掺杂密度可介于5×1015cm-3与1×1016cm-3之间。
参考图1D，在衬底1002上于沟道扩散链1028与隔离扩散链1030之间形成MOS晶体管的栅极电介质层1032。在栅极电介质层1032上形成MOS晶体管的栅极1034。在衬底1002中于漏极扩散链1026的顶部处形成漏极扩散区1036。在衬底1002中邻近于栅极1034与沟道扩散链1028相对地且在沟道扩散链1028与隔离扩散链1030之间形成源极扩散区1038。在衬底1002中于沟道扩散链1028与隔离扩散链1030之间形成背栅极触点扩撒区1040。在集成电路1000的操作期间，沟道扩散链1028提供从掩埋漂移区1004到栅极电介质层1032下方的沟道的电连接。隔离扩散链1030与掩埋漂移区1004组合地将源极扩散区1038与在MOS晶体管外侧的衬底1002电隔离。可调整图1B的经分段隔离开口区域1016的横向尺寸及间隔以提供MOS晶体管的所要击穿电压。
将认识到，可通过适当反转掺杂极性形成参考图1A到图1D所描述的MOS晶体管的p沟道版本。将认识到，可在集成电路1000中形成具有掩埋漂移区的第二平面延伸漏极MOS晶体管，以使得第二MOS晶体管的隔离扩散链与第一MOS晶体管的隔离扩散链1030同时形成，其中经分段沟道端开口区域的配置不同，以便在无额外过程操作的情况下提供不同于第一MOS晶体管的击穿。
图2A及图2B是含有根据第一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘连续制作阶段。参考图2A，在集成电路2000所形成于的衬底2004上方形成链离子植入掩模2002。已在衬底2004中形成掩埋漂移区2006。链离子植入掩模2002具有在掩埋漂移区2006的漏极部分上方的线性漏极端开口区域2008。链离子植入掩模2002还具有在掩埋漂移区2006的沟道部分上方的经分段沟道开口区域2010的线性阵列及在掩埋漂移区2006的隔离部分上方的多个经分段隔离开口区域2012。经分段隔离开口区域2012横向延伸到经分段沟道开口区域2010以便横向包封源极区域2014。对集成电路2000执行链离子植入操作，所述链离子植入操作同时穿过漏极开口区域2008、经分段沟道开口区域2010及经分段隔离开口区域2012将掺杂剂离子植入到衬底2004中以形成在漏极开口区域2008下方的漏极链植入区(未展示)、在经分段沟道开口区域2010下方的沟道链植入区(未展示)及在经分段隔离开口区域2012下方的隔离链植入区(未展示)，如参考图1B所描述。
参考图2B，对集成电路2000执行退火操作，所述退火操作使漏极链植入区中的掺杂剂扩散以形成漏极扩散链2016，漏极扩散链2016延伸到掩埋漂移区2006并与其进行电连接，如参考图1C所描述。所述退火操作还使沟道链植入区中的掺杂剂扩散以形成沟道扩散链2018，沟道扩散链2018延伸到掩埋漂移区2006并与其进行电连接，如参考图1C所描述。此外，所述退火操作使隔离链植入区中的掺杂剂扩散以形成隔离扩散链2020，隔离扩散链2020延伸到掩埋漂移区2006并与其形成电连接，如参考图1C所描述。随后，在源极区域2014中形成栅极2022、源极扩散区2024及任选背栅极扩散触点区2026。
在本实例中，隔离扩散链2020围绕源极区域2014横向延伸且接触沟道扩散链2018以便将源极扩散区2024与在MOS晶体管外侧的衬底2004电隔离。将认识到，其它隔离元件(例如填充有二氧化硅的深沟槽隔离元件)也可与隔离扩散链2020组合地使用以电隔离源极扩散区2024。
图3A及图3B是含有根据第二实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘连续制作阶段。参考图3A，在集成电路3000所形成于的衬底3004上方形成链离子植入掩模3002。已在衬底3004中形成掩埋漂移区3006。链离子植入掩模3002具有在掩埋漂移区3006的漏极部分上方的漏极开口区域3008。链离子植入掩模3002还具有在掩埋漂移区3006的沟道部分上方围绕漏极开口区域3008的经分段沟道开口区域3010的阵列及在掩埋漂移区3006的隔离部分上方的经分段隔离开口区域3012的闭环阵列。经分段沟道开口区域3010的阵列可具有如图3A中所描绘的闭环配置。经分段隔离开口区域3012横向环绕经分段沟道开口区域3010以便横向包封经分段沟道开口区域3010与经分段隔离开口区域3012之间的源极区域3014。对集成电路3000执行链离子植入操作，所述链离子植入操作同时穿过漏极开口区域3008、经分段沟道开口区域3010及经分段隔离开口区域3012将掺杂剂离子植入到衬底3004中以形成在漏极开口区域3008下方的漏极链植入区(未展示)、在经分段沟道开口区域3010下方的沟道链植入区(未展示)及在经分段隔离开口区域3012下方的隔离链植入区(未展示)，如参考图1B所描述。
参考图3B，对集成电路3000执行退火操作，所述退火操作使漏极链植入区中的掺杂剂扩散以形成漏极扩散链3016，漏极扩散链3016延伸到掩埋漂移区3006并与其进行电连接，如参考图1C所描述。所述退火操作还使沟道链植入区中的掺杂剂扩散以形成沟道扩散链3018，沟道扩散链3018延伸到掩埋漂移区3006并与其进行电连接，如参考图1C所描述。此外，所述退火操作使隔离链植入区中的掺杂剂扩散以形成隔离扩散链3020，隔离扩散链3020延伸到掩埋漂移区3006并与其形成电连接，如参考图1C所描述。随后，在源极区域3014中形成栅极3022、源极扩散区3024及任选背栅极扩散触点区3026。
在本实例中，沟道扩散链3018、栅极3022、源极扩散区3024、任选背栅极扩散触点区3026(如果存在)及隔离扩散链3020被配置为同心跑道形闭环，以使得隔离扩散链3020将源极扩散区3024与在MOS晶体管外侧的衬底3004电隔离。将认识到，可使用其它闭环形状，例如圆形、矩形或指状形状。
图4是含有根据一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其是在形成链离子植入掩模之后描绘的。在集成电路4000所形成于的衬底4004上方形成链离子植入掩模4002。链离子植入掩模4002具有经分段隔离开口区域4006。经分段隔离开口区域4006是以交错配置安置，举例来说，以获得随后在隔离开口区域4006下面形成的隔离扩散链的所要掺杂密度及总宽度。将认识到，可在具有非线性隔离扩散链(例如圆形或跑道形隔离扩散链)的MOS晶体管中形成经分段隔离开口区域的交错配置。
图5是含有根据一实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其是在形成链离子植入掩模之后描绘的。在集成电路5000所形成于的衬底5004上方形成链离子植入掩模5002。链离子植入掩模5002具有拥有第一长度及第一宽度的多个第一经分段隔离开口区域5006以及拥有第二长度及第二宽度的多个第二经分段隔离开口区域5008。第一经分段隔离开口区域5006与第二经分段隔离开口区域5008组合地可提供(举例来说)随后在第一经分段隔离开口区域5006及第二经分段隔离开口区域5008下面形成的隔离扩散链中的掺杂密度的有利缓变。将认识到，可在具有非线性隔离扩散链(例如圆形或跑道形隔离扩散链)的MOS晶体管中形成经分段隔离开口区域的交错配置。
尽管上文已描述本发明的各种实例，但应理解，所述实例仅通过实例而非限制的方式呈现。在不背离本发明的精神或范围的情况下，可根据本文中的揭示内容对所揭示实施例做出众多改变。因此，本发明的广度及范围不应受上文所描述的实例中的任一者限制。而是，本发明的范围应根据所附权利要求书及其等效物来界定。

Claims (18)

1.一种形成集成电路的方法，其包括：
接收具有第一导电性类型的衬底的半导体晶片、在所述衬底中的第二导电性类型的掩埋漂移区，以及在所述掩埋漂移区上的所述第一导电性类型的外延层，其中所述第二导电性类型与所述第一导电性类型相反；
将链离子植入掩模施加于所述外延层上，所述链离子植入掩模界定在所述掩埋漂移区的漏极部分上方的漏极开口区域，在所述掩埋漂移区的沟道部分上方且与所述漏极开口区域间隔开的沟道开口区域；
穿过所述漏极开口区域和所述沟道开口区域将掺杂剂植入到所述外延层上，以在所述半导体晶片的顶部表面处形成漏极链植入区和与所述漏极链植入区间隔开的沟道链植入区；以及
使所述漏极链植入区中的所述掺杂剂扩散以形成漏极扩散链，所述漏极扩散链延伸到所述掩埋漂移区的所述漏极部分；以及
使所述沟道链植入区中的所述掺杂剂扩散以形成沟道扩散链，所述沟道扩散链延伸到所述掩埋漂移区的所述沟道部分，所述沟道扩散链与所述漏极扩散链间隔开，其中所述顶部表面包括邻接栅极电介质层的区段。
2.根据权利要求1所述的方法，其中所述沟道扩散链和所述漏极扩散链由在所述外延层中的RESURF区分隔开。
3.根据权利要求2所述的方法，其中所述RESURF区延伸到所述掩埋漂移区且邻接所述掩埋漂移区。
4.根据权利要求1所述的方法，其中所述沟道链植入区和所述漏极链植入区由在所述外延层中的RESURF区分隔开。
5.根据权利要求4所述的方法，其中所述RESURF区延伸到所述掩埋漂移区且邻接所述掩埋漂移区。
6.根据权利要求1所述的方法，其中：
所述链离子植入掩模界定在所述掩埋漂移区的隔离部分上方的隔离开口区域；且
植入所述掺杂剂包括穿过所述隔离开口区域将所述掺杂剂植入到所述外延层上，以形成横向围绕具有所述沟道链植入区的源极区域的隔离链植入区。
7.根据权利要求6所述的方法，其中：
所述沟道链植入区横向围绕所述漏极链植入区；且
所述隔离链植入区横向围绕所述沟道链植入区和所述漏极链植入区。
8.根据权利要求1所述的方法，其中：
所述漏极开口区域包括线性开口区域；
所述沟道开口区域包括开口区域的线性阵列。
9.根据权利要求1所述的方法，其中：
所述漏极开口区域包括线性开口区域；
所述沟道开口区域包括横向围绕所述线性开口区域的开口区域的非线性阵列。
10.一种形成延伸漏极晶体管的方法，其包括：
接收具有第一导电性类型的顶部表面以及在所述顶部表面下方的第二导电性类型的掩埋漂移区的半导体晶片，其中所述第二导电性类型与所述第一导电性类型相反；以及
形成从所述顶部表面延伸到所述掩埋漂移区的漏极链，且所述漏极链具有所述第二导电性类型的掺杂剂；以及
形成从所述顶部表面延伸到所述掩埋漂移区的沟道链，且所述沟道链具有所述第二导电性类型的所述掺杂剂，所述沟道链通过沿着所述顶部表面的RESURF区与所述漏极链分隔开，
其中所述顶部表面包括邻接栅极电介质层的区段。
11.根据权利要求10所述的方法，其中所述RESURF区从所述顶部表面延伸至邻接所述掩埋漂移区。
12.根据权利要求10所述的方法，进一步包括：
形成从所述顶部表面延伸到所述掩埋漂移区的隔离链，且所述隔离链具有所述第二导电性类型的所述掺杂剂，所述隔离链横向围绕具有所述沟道链的源极区域。
13.根据权利要求12所述的方法，其中：
所述沟道链横向围绕所述漏极链；且
所述隔离链横向围绕所述沟道链和所述漏极链。
14.根据权利要求10所述的方法，其中：
所述漏极链包括线性扩散区；且
所述沟道链包括扩散区的线性阵列。
15.根据权利要求10所述的方法，其中：
所述漏极链包括线性扩散区；
所述沟道链包括横向围绕所述线性扩散区的扩散区域的非线性阵列。
16.一种形成集成电路的方法，其包括：
在半导体晶片的顶部表面下方形成掩埋漂移区，
在所述顶部表面上施加链离子植入掩模，所述链离子植入掩模界定：
在所述掩埋漂移区的漏极部分上方的漏极开口区域；
在所述掩埋漂移区的沟道部分上方且与沿着所述顶部表面的所述漏极开口区域分隔开的沟道开口区域；以及
在所述掩埋漂移区的隔离部分的上方的隔离开口区域；以及
穿过所述漏极开口区域、所述沟道开口区域及所述隔离开口区域将掺杂剂植入到所述顶部表面上以形成漏极链植入区、与所述漏极链植入区间隔开的沟道链植入区，以及横向围绕所述掩埋漂移区上方的源极区域的隔离链植入区；
使所述漏极链植入区中的所述掺杂剂扩散以形成漏极扩散链，所述漏极扩散链与所述掩埋漂移区的所述漏极部分连接；
使所述沟道链植入区中的所述掺杂剂扩散以形成沟道扩散链，所述沟道扩散链与所述掩埋漂移区的所述沟道部分连接，所述沟道扩散链由所述顶部表面的RESURF区与所述漏极扩散链分隔开；以及
使所述隔离链植入区中的所述掺杂剂扩散以形成隔离扩散链，所述隔离扩散链与所述掩埋漂移区的所述隔离部分连接，
其中所述顶部表面包括邻接栅极电介质层的区段。
17.根据权利要求16所述的方法，其中：
所述漏极开口区域包括线性开口区域；
所述沟道开口区域包括经分段开口区域的线性阵列。
18.根据权利要求16所述的方法，其中：
所述漏极开口区域包括线性开口区域；
所述沟道链包括横向围绕所述线性开口区域的开口区域的非线性阵列。
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