CN104716184B - 具有经改进漂移层触点的高电压横向延伸漏极mos晶体管 - Google Patents

具有经改进漂移层触点的高电压横向延伸漏极mos晶体管 Download PDF

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CN104716184B
CN104716184B CN201410787421.3A CN201410787421A CN104716184B CN 104716184 B CN104716184 B CN 104716184B CN 201410787421 A CN201410787421 A CN 201410787421A CN 104716184 B CN104716184 B CN 104716184B
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channel terminal
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drift region
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CN104716184A (zh
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菲利普·利兰·豪尔
萨米尔·彭德哈卡
马里·丹尼森
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Abstract

本申请案涉及一种具有经改进漂移层触点的高电压横向延伸漏极MOS晶体管。一种集成电路及方法具有延伸漏极MOS晶体管，所述延伸漏极MOS晶体管具有掩埋漂移区、在所述掩埋漂移区与漏极触点之间的漏极端扩散链及在所述掩埋漂移区与沟道之间的同时形成的沟道端扩散链，其中所述沟道端扩散链是通过穿过经分段区域进行植入以将掺杂稀释到小于所述漏极端扩散链中的掺杂的三分之二而形成。

Description

具有经改进漂移层触点的高电压横向延伸漏极MOS晶体管
技术领域
本发明涉及集成电路的领域。更特定来说，本发明涉及集成电路中的MOS晶体管。
背景技术
集成电路可含有具有掩埋漂移区的平面延伸漏极金属氧化物半导体(MOS)晶体管，举例来说，以提供高于所述MOS晶体管中的栅极电介质层的介电强度的操作电压。可期望形成掩埋漂移区与漏极触点之间的低电阻漏极端连接，同时可期望形成掩埋漂移区与MOS晶体管的沟道之间的经轻掺杂沟道端链。可进一步期望最小化在形成集成电路的制作序列中的光刻及离子植入操作的数目。
发明内容
下文呈现简化发明内容以便提供对本发明的一或多个方面的基本理解。本发明内容并非本发明的广泛概述，且既不打算识别本发明的关键或紧要元件，也不打算记述其范围。而是，本发明内容的主要目的为以简化形式呈现本发明的一些概念作为稍后所呈现的更详细说明的前言。
一种集成电路可包含平面延伸漏极MOS晶体管，所述平面延伸漏极MOS晶体管具有在所述MOS晶体管的漏极触点与沟道之间的掩埋漂移区。所述掩埋漂移区与漏极触点之间的漏极端链和所述掩埋漂移区与沟道之间的沟道端链同时形成。所述漏极端链及所述沟道端链是通过离子植入掺杂剂、后续接着进行退火操作而形成，所述退火操作使经植入掺杂剂扩散以与所述掩埋漂移区进行电连接。所述沟道端链中的平均掺杂密度小于所述漏极端链中的平均掺杂密度的三分之二。通过以下操作来形成所述沟道端链：将经离子植入区域分段以使得在退火操作之后经植入分段的扩散掺杂剂分布在所述沟道端链中比在漏极端链中更稀释。
附图说明
图1A到图1D是根据第一实例形成的集成电路的透视图，其是以连续制作阶段描绘的。
图2是含有根据第二实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。
图3是含有根据第三实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。
图4是含有根据第四实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。
图5是含有根据第五实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。
图6是含有根据第六实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。
具体实施方式
以下共同待决的专利申请案为相关的且特此以引用的方式并入：与本申请案同时申请的美国专利申请案14/xxx，xxx(德州仪器(Texas Instruments)档案号TI-69256)。
参考附图描述本发明，其中贯穿所述各图使用相似参考编号来指定类似或等效元件。所述图未按比例绘制且其仅经提供以图解说明本发明。下文参考用于图解说明的实例性应用来描述本发明的数个方面。应理解，众多特定细节、关系及方法经陈述以提供对本发明的理解。然而，所属领域的技术人员将容易地认识到，可在不使用所述特定细节中的一或多者或者使用其它方法的情况下实践本发明。在其它实例中，未详细展示众所周知的结构或操作以避免使本发明模糊。本发明不受动作或事件的所图解说明排序限制，这是因为一些动作可以不同次序发生及/或与其它动作或事件同时发生。此外，未必需要所有所图解说明动作或事件来实施根据本发明的方法。
一种集成电路可包含平面延伸漏极MOS晶体管，所述平面延伸漏极MOS晶体管具有在所述MOS晶体管的漏极触点与沟道之间的掩埋漂移区。通过离子植入及退火而使所述掩埋漂移区与所述漏极触点之间的漏极端链与所述掩埋漂移区与所述沟道之间的沟道端链同时形成，所述退火使每一链中的经植入掺杂剂扩散以与所述掩埋漂移区进行电连接。将所述沟道端链中的离子植入区域分段以使得在退火期间掺杂剂横向稀释以与未分段植入区域相比减小平均掺杂密度。在退火操作之后，沟道端链中的邻近经植入分段的掺杂剂分布可重叠。沟道端链中的平均掺杂密度小于漏极端链中的平均掺杂密度的三分之二。对沟道端链的经离子植入区域的分段可经调整以提供所述MOS晶体管的所要击穿电压及串联电阻。可在同一集成电路中形成具有掩埋漂移区的第二平面延伸漏极MOS晶体管，其中对所述第二晶体管的与第一MOS晶体管的沟道端链同时形成的沟道端链的经离子植入区域进行的不同分段可在无额外过程操作的情况下提供具有不同所要击穿电压及串联电阻的MOS晶体管。
图1A到图1D是根据第一实例形成的集成电路的透视图，其是以连续制作阶段描绘的。参考图1A，在p型衬底1002中及上形成集成电路1000，p型衬底1002可为单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶体定向的区的混合定向技术(HOT)晶片或适于制作集成电路1000的其它材料。在衬底1002中形成平面延伸漏极n沟道MOS晶体管的n型掩埋漂移区1004。可通过以下操作来形成掩埋漂移区1004：将n型掺杂剂(举例来说，磷)离子植入到衬底1002的现有顶部表面中，后续接着在经植入n型掺杂剂上方生长p型外延半导体材料。在本实例的一个版本中，掩埋漂移区1004的顶部表面在衬底1002中的深度可介于2微米与4微米之间。衬底1002的在掩埋漂移区1004上面的区可在集成电路1000的操作期间提供RESURF区。
在衬底1002的现有顶部表面上方形成链离子植入掩模1006。链离子植入掩模1006可包含光致抗蚀剂及/或电介质层(例如二氧化硅)。链离子植入掩模1006具有在掩埋漂移区1004的漏极端上方的漏极端开口区域1008。链离子植入掩模1006还具有在掩埋漂移区1004的沟道端上方的多个经分段沟道端开口区域1010。在本实例的一个版本中，每一经分段沟道端开口区域1010可具有介于1.5微米与3.0微米之间的横向尺寸且以4微米与7微米之间的距离间隔开。
参考图1B，对集成电路1000执行链离子植入操作，所述链离子植入操作同时穿过链离子植入掩模1006的漏极端开口区域1008及经分段沟道端开口区域1010将n型掺杂剂(例如磷及可能地砷)离子植入到衬底1002中。在本实例的一个版本中，链离子植入操作可具有介于8×1012cm-2与1.5×1013cm-2之间的剂量。链离子植入操作形成在漏极端开口区域1008下方的漏极端链植入区1012及在经分段沟道端开口区域1010下方的沟道端链植入区1014。在本实例的一个版本中，沟道端链植入区1014不彼此触碰或重叠。
参考图1C，对集成电路1000执行退火操作，所述退火操作使图1B的漏极端链植入区1012中的掺杂剂扩散以形成漏极端扩散链1016，漏极端扩散链1016延伸到掩埋漂移区1004并与其进行电连接。所述退火操作还使图1B的沟道端链植入区1014中的掺杂剂扩散以形成沟道端扩散链1018，沟道端扩散链1018延伸到掩埋漂移区1004并与其进行电连接。在本实例的一个版本中，来自邻近沟道端链植入区1014的扩散区重叠以形成邻接沟道端扩散链1018，如图1C中所描绘。在替代版本中，在来自邻近沟道端链植入区1014的扩散区之间可存在间隙。沟道端扩散链1018中的平均掺杂密度小于漏极端扩散链1016中的平均掺杂密度的三分之二。在本实例的一个版本中，沟道端扩散链1018中的平均掺杂密度可介于漏极端扩散链1016中的平均掺杂密度的25％与33％之间。在一个实例中，漏极端扩散链1016中的平均掺杂密度可介于2.5×1016cm-3与3.5×1016cm-3之间，且沟道端扩散链1018中的平均掺杂密度可介于5×1015cm-3与1×1016cm-3之间。
参考图1D，在衬底1002上邻近于沟道端扩散链1018与掩埋漂移区1004相对地形成MOS晶体管的栅极电介质层1020。在栅极电介质层1020上形成MOS晶体管的栅极1022。可在漏极端扩散链1016中于衬底1002的顶部表面处形成任选经重掺杂漏极扩散区1024。在衬底1002上形成漏极触点1026以通过漏极扩散区1024(如果形成)与漏极端扩散链1016电连接。在集成电路1000的操作期间，沟道端扩散链1018提供从掩埋漂移区1004到栅极电介质层1020下方的沟道的电连接。可调整图1B的经分段沟道端开口区域1010的横向尺寸及间隔以提供MOS晶体管的所要击穿电压及串联电阻。
将认识到，可通过适当反转掺杂极性形成参考图1A到图1D所描述的MOS晶体管的p沟道版本。将认识到，可在集成电路1000中形成具有掩埋漂移区的第二平面延伸漏极MOS晶体管，以使得第二MOS晶体管的沟道端链与第一MOS晶体管的沟道端链1018同时形成，其中经分段沟道端开口区域的配置不同，以便在无额外过程操作的情况下提供不同于第一MOS晶体管的击穿及电阻值。
图2是含有根据第二实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。在集成电路2000所形成于的衬底2004上方形成链离子植入掩模2002。链离子植入掩模2002具有居中位于经分段沟道端开口区域2008的两个线性阵列之间的线性漏极端开口区域2006。在如上文参考图1B及1C所描述的使用链离子植入掩模2002的离子植入及退火之后，在衬底中于经分段沟道端开口区域2008下面形成沟道端扩散链，且在衬底中于线性漏极端开口区域2006下面形成漏极端扩散链。
图3是含有根据第三实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。在集成电路3000所形成于的衬底3004上方形成链离子植入掩模3002。链离子植入掩模3002具有居中位于经分段沟道端开口区域3008的圆形阵列中的圆形漏极端开口区域3006。在如上文参考图1B及1C所描述的使用链离子植入掩模3002的离子植入及退火之后，在衬底中于经分段沟道端开口区域3008的圆形阵列下面形成圆形沟道端扩散链，所述圆形沟道端扩散链环绕形成于圆形漏极端开口区域3006下面的衬底中的漏极端扩散链。
图4是含有根据第四实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。在集成电路4000所形成于的衬底4004上方形成链离子植入掩模4002。链离子植入掩模4002具有居中位于经分段沟道端开口区域4008的跑道形阵列中的具有圆形端的线性漏极端开口区域4006。沟道端开口区域4008经配置以提供随后在沟道端开口区域4008下面形成的沟道端链中的电场的所要均匀性。形成如图4中所描绘的MOS晶体管与具有相当电流容量及击穿电压的其它配置相比可消耗集成电路的4000的较少面积。在如上文参考图1B及1C所描述的使用链离子植入掩模4002的离子植入及退火之后，在衬底中于经分段沟道端开口区域4008的跑道阵列下面形成跑道形沟道端扩散链，所述跑道形沟道端扩散链环绕形成于线性漏极端开口区域4006下面的衬底中的漏极端扩散链。
图5是含有根据第五实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。在集成电路5000所形成于的衬底5004上方形成链离子植入掩模5002。链离子植入掩模5002具有漏极端开口区域5006及经分段沟道端开口区域5008。经分段沟道端开口区域5008是以交错配置安置，举例来说，以获得随后在沟道端开口区域5008下面形成的沟道端链的所要掺杂密度及总宽度。将认识到，可在具有非线性沟道端链(例如圆形或跑道形沟道端链)的MOS晶体管中形成经分段沟道端开口区域的交错配置。
图6是含有根据第六实例形成的平面延伸漏极MOS晶体管的集成电路的俯视图，其描绘在形成链离子植入掩模之后的状态。在集成电路6000所形成于的衬底6004上方形成链离子植入掩模6002。链离子植入掩模6002具有漏极端开口区域6006及经分段沟道端开口区域6008。经分段沟道端开口区域6008包含至少两个不同大小的开口区域，举例来说，以获得邻近于MOS晶体管的沟道的所要掺杂分布及随后在沟道端开口区域6008下面形成的沟道端链的所要电阻。将认识到，可在具有非线性沟道端链(例如圆形或跑道形沟道端链)的MOS晶体管中形成具有不同大小的开口的经分段沟道端开口区域的配置。
尽管上文已描述本发明的各种实例，但应理解，所述实例仅通过实例而非限制的方式呈现。在不背离本发明的精神或范围的情况下，可根据本文中的揭示内容对所揭示实施例做出众多改变。因此，本发明的广度及范围不应受上文所描述的实例中的任一者限制。而是，本发明的范围应根据所附权利要求书及其等效物来界定。

Claims (20)

1.一种集成电路，其包括：
衬底，所述衬底具有第一导电性类型；
平面延伸漏极金属氧化物半导体MOS晶体管，所述MOS晶体管包含：
掩埋漂移区，其在所述衬底中以使得所述掩埋漂移区的顶部在所述衬底的顶部表面下面，所述掩埋漂移区具有与所述衬底相反的导电性类型，所述掩埋漂移区具有靠近所述MOS晶体管的漏极触点的漏极端，且所述掩埋漂移区具有靠近所述MOS晶体管的沟道区域的沟道端；
漏极端扩散链，其在所述衬底中，所述漏极端扩散链具有所述掩埋漂移区的所述导电性类型，所述漏极端扩散链在所述掩埋漂移区的所述漏极端处与所述掩埋漂移区电连接且与漏极触点电连接；以及
沟道端扩散链，其在所述衬底中，所述沟道端扩散链具有所述掩埋漂移区的所述导电性类型，所述沟道端扩散链在所述掩埋漂移区的所述沟道端处与所述掩埋漂移区电连接，所述沟道端扩散链是通过穿过多个经分段沟道端开口区域的离子植入而形成，以使得所述沟道端扩散链中的平均掺杂密度小于所述漏极端扩散链中的平均掺杂密度的三分之二。
2.根据权利要求1所述的集成电路，其中所述经分段沟道端开口区域是配置成线性阵列。
3.根据权利要求1所述的集成电路，其中所述经分段沟道端开口区域是配置成圆形阵列，且所述沟道端扩散链居中地位于所述圆形阵列中。
4.根据权利要求1所述的集成电路，其中所述经分段沟道端开口区域是配置成跑道形阵列，且所述沟道端扩散链居中地位于所述跑道形阵列中。
5.根据权利要求1所述的集成电路，其中所述经分段沟道端开口区域是以交错配置而布置。
6.根据权利要求1所述的集成电路，其中：
所述衬底的所述导电性类型为p型；
所述掩埋漂移区的所述导电性类型为n型；
所述漏极端扩散链的所述导电性类型为n型；且
所述沟道端扩散链的所述导电性类型为n型。
7.根据权利要求1所述的集成电路，其中所述掩埋漂移区的顶部表面在所述衬底中的深度介于2微米与4微米之间。
8.根据权利要求1所述的集成电路，其中所述沟道端扩散链中的所述平均掺杂密度介于所述漏极端扩散链中的所述平均掺杂密度的25％与33％之间。
9.根据权利要求1所述的集成电路，其中：
所述漏极端扩散链中的所述平均掺杂密度介于2.5×1016cm-3与3.5×1016cm-3之间；且
所述沟道端扩散链中的所述平均掺杂密度介于5×1015cm-3与1×1016cm-3之间。
10.根据权利要求1所述的集成电路，其中所述经分段沟道端开口区域具有介于1.5微米与3.0微米之间的横向尺寸且以介于4微米与7微米之间的距离间隔开。
11.一种形成集成电路的方法，其包括：
提供衬底，所述衬底具有第一导电性类型
通过包括以下步骤的方法形成平面延伸漏极MOS晶体管：
在所述衬底中形成掩埋漂移区以使得所述掩埋漂移区的顶部表面在所述衬底的顶部表面下面，以使得所述掩埋漂移区具有与所述衬底相反的导电性类型，以使得所述掩埋漂移区具有漏极端及沟道端；
在所述衬底的所述顶部表面上方形成链离子植入掩模，以使得所述链离子植入掩模具有在所述掩埋漂移区的漏极端上方的漏极端开口区域且具有在所述掩埋漂移区的所述沟道端上方的多个经分段沟道端开口区域；
同时穿过所述漏极端开口区域及所述经分段沟道端开口区域将掺杂剂离子植入到所述衬底中以形成在所述漏极端开口区域下方的漏极端链植入区且形成在所述多个经分段沟道端开口区域下方的多个沟道端链植入区；
执行退火操作，所述退火操作：
使所述漏极端链植入区中的所述掺杂剂扩散以形成漏极端扩散链，所述漏极端扩散链延伸到所述掩埋漂移区并与其电连接；以及
使所述沟道端链植入区中的所述掺杂剂扩散以形成沟道端扩散链，所述沟道端扩散链延伸到所述掩埋漂移区并与其电连接，以使得所述沟道端扩散链中的平均掺杂密度小于所述漏极端扩散链中的平均掺杂密度的三分之二；
在所述衬底上邻近于所述沟道端扩散链与所述掩埋漂移区相对地形成栅极电介质层；
在所述栅极电介质层上形成栅极；以及
在所述衬底上形成漏极触点以便与所述漏极端扩散链电连接。
12.根据权利要求11所述的方法，其中所述经分段沟道端开口区域是配置成线性阵列。
13.根据权利要求11所述的方法，其中所述经分段沟道端开口区域是配置成圆形阵列，且所述漏极端扩散链居中位于所述圆形阵列中。
14.根据权利要求11所述的方法，其中所述经分段沟道端开口区域是配置成跑道形阵列，且所述漏极端扩散链居中位于所述跑道形阵列中。
15.根据权利要求11所述的方法，其中所述经分段沟道端开口区域是以交错配置而布置。
16.根据权利要求11所述的方法，其中：
所述衬底的所述导电性类型为p型；
所述掩埋漂移区的所述导电性类型为n型；
所述漏极端扩散链的导电性类型为n型；且
所述沟道端扩散链的导电性类型为n型。
17.根据权利要求11所述的方法，其中所述掩埋漂移区的顶部表面在所述衬底中的深度介于2微米与4微米之间。
18.根据权利要求11所述的方法，其中所述沟道端扩散链中的所述平均掺杂密度介于所述漏极端扩散链中的所述平均掺杂密度的25％与33％之间。
19.根据权利要求11所述的方法，其中：
所述漏极端扩散链中的所述平均掺杂密度介于2.5×1016cm-3与3.5×1016cm-3之间；且
所述沟道端扩散链中的所述平均掺杂密度介于5×1015cm-3与1×1016cm-3之间。
20.根据权利要求11所述的方法，其中所述经分段沟道端开口区域具有介于1.5微米与3.0微米之间的横向尺寸且以介于4微米与7微米之间的距离间隔开。
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CN1632931A (zh) * 2004-12-23 2005-06-29 上海华虹（集团）有限公司 提高表面降场型ldmos器件耐压的工艺
CN201741700U (zh) * 2010-06-11 2011-02-09 东南大学 带浮置埋层的碳化硅高压p型金属氧化物半导体管

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