CN104659079B - 隔离型nldmos器件及其制造方法 - Google Patents

隔离型nldmos器件及其制造方法 Download PDF

Info

Publication number
CN104659079B
CN104659079B CN201510033372.9A CN201510033372A CN104659079B CN 104659079 B CN104659079 B CN 104659079B CN 201510033372 A CN201510033372 A CN 201510033372A CN 104659079 B CN104659079 B CN 104659079B
Authority
CN
China
Prior art keywords
type
well
traps
region
heavily doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510033372.9A
Other languages
English (en)
Other versions
CN104659079A (zh
Inventor
段文婷
刘冬华
钱文生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201510033372.9A priority Critical patent/CN104659079B/zh
Publication of CN104659079A publication Critical patent/CN104659079A/zh
Application granted granted Critical
Publication of CN104659079B publication Critical patent/CN104659079B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816Lateral DMOS transistors, i.e. LDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

本发明公开了一种隔离型NLDMOS器件,将N阱104移向沟道侧,使鸟嘴位于N阱上,保证器件有较高的开态击穿电压,并在N阱下方加打一道P型注入区,使漂移区的耗尽区面积增加,关态击穿电压升高,从而能在保证器件的开态击穿电压的同时,保证器件有足够高的关态击穿电压。P型注入区长度可调节,关态击穿电压随P型注入区长度增加而增加。本发明还公开了该种隔离型NLDMOS器件的制造方法。

Description

隔离型NLDMOS器件及其制造方法
技术领域
本发明涉及半导体技术,特别涉及一种隔离型NLDMOS器件及其制造方法。
背景技术
LDMOS(横向扩散金属氧化物半导体)由于具有耐高压、大电流驱动能力、极低功耗以及可与CMOS集成等优点,目前在电源管理电路中被广泛采用。
现有一种40V隔离型NLDMOS(N型横向扩散金属氧化物半导体)器件,如图1所示,在P型硅衬底101上形成有N型深阱102,N型深阱102左部形成有P阱105,右部形成有N阱104;P阱105同N阱104之间有N型深阱102间隔区,P阱105右部、N阱104左部及P阱105同N阱104之间的N型深阱102间隔区上方形成有多晶硅栅107;多晶硅栅107同P阱105右部、P阱105同N阱104之间的N型深阱102间隔区左部之间由栅氧化层106隔离,多晶硅栅107同N阱104左部、P阱105同N阱104之间的N型深阱102间隔区右部之间由场氧103隔离;P阱105上形成有一重掺杂P型区109及一重掺杂N型区112,N阱104右部上形成有一重掺杂N型区108;P阱105上的重掺杂P型区109作为P阱105引出端,P阱105上的重掺杂N型区112、N阱104右部上的重掺杂N型区108分别作为NLDMOS器件的源区、漏区引出端。
图1所示的隔离型NLDMOS器件,N型深阱102和N阱104由于有时需要与其他器件共用,掺杂浓度不可改变。隔离型NLDMOS器件的N型深阱102起到体区与衬底隔离的作用,使漂移区变浓,从而off-BV(关态击穿电压)下降。图1所示的隔离型NLDMOS器件,可以通过拉大N阱104与P阱105的距离提高off-BV(关态击穿电压),但因为拉大N阱104与P阱105的距离后使靠近沟道侧漂移区变淡,会导致on-BV(开态击穿电压)下降。
图1所示的NLDMOS器件,N型深阱102和N阱104由于有时需要与其他器件共用,掺杂浓度不可改变,而N型深阱102较浓且较深,不易耗尽,击穿电压不易提高,只能通过改变器件尺寸与结构提高器件击穿电压。
发明内容
本发明要解决的技术问题是能在保证隔离型NLDMOS器件的on-BV(开态击穿电压)的同时,保证隔离型NLDMOS器件有足够高的off-BV(关态击穿电压),并且不必改变器件尺寸。
为解决上述技术问题,本发明提供的隔离型NLDMOS器件,在P型硅衬底上形成有N型深阱;
在所述N型深阱左部形成有一P阱;
在所述N型深阱右部形成有一N阱;
所述P阱同所述N阱之间有N型深阱间隔区;
P阱右部、N阱左部及P阱同N阱之间的N型深阱间隔区上方,形成有多晶硅栅;
多晶硅栅同P阱右部、P阱同N阱之间的N型深阱间隔区之间,由栅氧化层隔离;
多晶硅栅同N阱左部之间,从左到右依次由栅氧化层、漂移区场氧隔离;
所述N阱下方的N型深阱中,形成有一P型注入区;
P阱上形成有一重掺杂P型区及一重掺杂N型区;
N阱右部上形成有一重掺杂N型区;
P阱上的重掺杂P型区作为P阱引出端;
P阱上的重掺杂N型区、N阱右部上的重掺杂N型区分别作为NLDMOS器件的源区、漏区引出端;
所述N阱的N型掺杂浓度,大于N型深阱的N型掺杂浓度,并且小于重掺杂N型区的N型掺杂浓度;
所述P阱的P型掺杂浓度,大于P型硅衬底的P型掺杂浓度,并且小于重掺杂P型区的P型掺杂浓度;
所述P型注入区的P型掺杂浓度,大于P型硅衬底的P型掺杂浓度。
较佳的,所述P型注入区,最左端在所述P阱左侧到所述漂移区场氧右侧之间。
为解决上述技术问题,本发明提供的隔离型NLDMOS器件的制造方法,包括以下工艺步骤:
一、在P型衬底上通过N型离子注入形成N型深阱;
二.利用有源区光刻,打开场氧区域,刻蚀场氧区,生长场氧,在N型深阱左部上形成沟道区场氧,在N型深阱右部上形成漂移区场氧;
三、光刻打开阱注入区域,在沟道区场氧下方及其左右两侧的N型深阱中注入P型杂质离子形成P阱,在漂移区场氧下方及其左右两侧的N型深阱中注入N型杂质离子形成N阱;所述P阱同所述N阱之间有N型深阱间隔区;
四、在硅片上,通过热氧化方法生长栅氧化层;
五、在所述N阱下方的N型深阱中注入P型杂质离子形成P型注入区;
六、在硅片上,淀积多晶硅;然后进行多晶硅栅刻蚀,形成NLDMOS的栅极多晶硅,栅极多晶硅的左部位于P阱右部上方,右部位于N阱左部上方;
七、选择性的进行源漏离子注入,在沟道区场氧左右两侧的P阱上分别形成有一重掺杂P型区及一重掺杂N型区,在漂移区场氧右侧的N阱上形成有一重掺杂N型区;
八、通过传统的接触孔工艺形成接触孔连接,通过接触孔和金属线引出电极;
P阱上的重掺杂P型区作为P阱引出端;
P阱上的重掺杂N型区、N阱上的重掺杂N型区分别作为NLDMOS器件的源区、漏区引出端。
较佳的,步骤五中,P型注入区的P型注入为硼离子,能量为800KeV到1500KeV,剂量为1E11到1E13个每平方厘米。
较佳的,P型注入区左端在P阱与漂移区场氧之间。
本发明的隔离型NLDMOS器件及其制造方法,将N阱移向沟道侧,使鸟嘴位于N阱1上,保证器件有较高的on-BV(开态击穿电压),并在N阱下方加打一道P型注入区,使漂移区的耗尽区面积增加,off-BV(关态击穿电压)升高,从而能在保证器件的on-BV(开态击穿电压)的同时,保证器件有足够高的off-BV(关态击穿电压)。
附图说明
为了更清楚地说明本发明的技术方案,下面对本发明所需要使用的附图作简单的介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是现有一种隔离型NLDMOS器件截面图;
图2是本发明的隔离型NLDMOS器件一实施例截面图;
图3是本发明的隔离型NLDMOS制造方法一实施例N型深阱形成之后的器件截面图;
图4是本发明的隔离型NLDMOS制造方法一实施例场氧形成之后的器件截面图;
图5是本发明的隔离型NLDMOS制造方法一实施例N阱与P阱形成之后的器件截面图;
图6是本发明的隔离型NLDMOS制造方法一实施例多晶硅栅形成之后的器件截面图;
图7是本发明的隔离型NLDMOS制造方法一实施例源漏注入之后的器件截面图。
具体实施方式
下面将结合附图,对本发明中的技术方案进行清楚、完整的描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
实施例一
隔离型NLDMOS(N型横向扩散金属氧化物半导体)器件,如图2所示,在P型硅衬底101上形成有N型深阱102;
在所述N型深阱102左部形成有一P阱105;
在所述N型深阱102右部形成有一N阱104;
P阱105同N阱104之间有N型深阱102间隔区;
P阱105右部、N阱104左部及P阱105同N阱104之间的N型深阱102间隔区上方,形成有多晶硅栅107;
多晶硅栅107同P阱105右部、P阱105同N阱104之间的N型深阱102间隔区之间,由栅氧化层106隔离;
多晶硅栅107同N阱104左部之间,从左到右依次由栅氧化层106、漂移区场氧103隔离;
所述N阱104下方的N型深阱102中,形成有一P型注入区113;
P阱105上形成有一重掺杂P型区109及一重掺杂N型区112;
N阱104右部上形成有一重掺杂N型区108;
P阱105上的重掺杂P型区109作为P阱105引出端;
P阱105上的重掺杂N型区112、N阱104右部上的重掺杂N型区108分别作为NLDMOS器件的源区、漏区引出端;
所述N阱104的N型掺杂浓度,大于N型深阱102的N型掺杂浓度,并且小于重掺杂N型区108,112的N型掺杂浓度;
所述P阱105的P型掺杂浓度,大于P型硅衬底101的P型掺杂浓度,并且小于重掺杂P型区109的P型掺杂浓度;
所述P型注入区113的P型掺杂浓度,大于P型硅衬底101的P型掺杂浓度。
较佳的,所述P型注入区113,最左端在所述P阱105左侧到所述漂移区场氧103右侧之间。
实施例一的隔离型NLDMOS(N型横向扩散金属氧化物半导体)器件,将N阱104移向沟道侧,使鸟嘴位于N阱104上,保证器件有较高的on-BV(开态击穿电压),并在N阱104下方加打一道P型注入区113,使漂移区的耗尽区面积增加,off-BV(关态击穿电压)升高,从而能在保证器件的on-BV(开态击穿电压)的同时,保证器件有足够高的off-BV(关态击穿电压)。P型注入区113长度可调节,off-BV(关态击穿电压)随P型注入区113长度增加而增加。
实施例二
实施例一的隔离型NLDMOS(N型横向扩散金属氧化物半导体)器件的制造方法,主要包括以下工艺步骤:
一、在P型衬底101上通过N型离子注入形成N型深阱102,如图3所示;
二.利用有源区光刻,打开场氧区域,刻蚀场氧区,生长场氧103,114,在N型深阱102左部上形成沟道区场氧114,在N型深阱102右部上形成漂移区场氧103,如图4所示;
三、光刻打开阱注入区域,在沟道区场氧114下方及其左右两侧的N型深阱102中注入P型杂质离子形成P阱105,在漂移区场氧103下方及其左右两侧的N型深阱102中注入N型杂质离子形成N阱104;所述P阱105同所述N阱104之间有N型深阱102间隔区,如图5所示;
四、在硅片上,通过热氧化方法生长栅氧化层106;
五、在所述N阱104下方的N型深阱102中注入P型杂质离子形成P型注入区113;
六、在硅片上,淀积多晶硅;然后进行多晶硅栅刻蚀,形成NLDMOS的栅极多晶硅107,栅极多晶硅107的左部位于P阱105右部上方,右部位于N阱104左部上方,图6所示;
七、选择性的进行常规的源漏离子注入,在沟道区场氧114左右两侧的P阱105上分别形成有一重掺杂P型区109及一重掺杂N型区112,在漂移区场氧103右侧的N阱104上形成有一重掺杂N型区108,如图7所示;
八、通过传统的接触孔工艺形成接触孔连接,通过接触孔110和金属线111引出电极;
P阱105上的重掺杂P型区109作为P阱105引出端;
P阱105上的重掺杂N型区112、N阱104上的重掺杂N型区108分别作为NLDMOS器件的源区、漏区引出端,最后完成此NLDMOS器件的制作,如图2所示。
较佳的,步骤五中,P型注入区113的P型注入为硼离子,能量为800KeV到1500KeV,剂量为1E11到1E13个每平方厘米。
较佳的,P型注入区113左端在P阱105与漂移区场氧103之间。
实施例二的隔离型NLDMOS器件的制造方法,在N型深阱102左部注入P型杂质离子形成P阱105,在N型深阱102右部注入N型杂质离子形成N阱104,P阱105作为NLDMOS的本底区,N阱104作为NLDMOS的漂移区,将N阱104移向沟道侧,N阱104左侧位置位于P阱105与鸟嘴之间(即鸟嘴位于N阱104上),保证器件有较高的on-BV(开态击穿电压)。同时,在N阱104下方加打一道P型注入区113,使漂移区的耗尽区面积增加,off-BV(关态击穿电压)升高,从而能在保证器件的on-BV(开态击穿电压)的同时,保证器件有足够高的off-BV(关态击穿电压)。P型注入区113长度可调节,off-BV(关态击穿电压)随P型注入区113长度增加而增加。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明保护的范围之内。

Claims (4)

1.一种隔离型NLDMOS器件,其特征在于,在P型硅衬底上形成有N型深阱;
在所述N型深阱左部形成有一P阱;
在所述N型深阱右部形成有一N阱;
所述P阱同所述N阱之间有N型深阱间隔区;
P阱右部、N阱左部及P阱同N阱之间的N型深阱间隔区上方,形成有多晶硅栅;
多晶硅栅同P阱右部、P阱同N阱之间的N型深阱间隔区之间,由栅氧化层隔离;
多晶硅栅同N阱左部之间,从左到右依次由栅氧化层、漂移区场氧隔离;
所述N阱下方的N型深阱中,形成有一P型注入区;
P阱上形成有一重掺杂P型区及一重掺杂N型区;
N阱右部上形成有一重掺杂N型区;
P阱上的重掺杂P型区作为P阱引出端;
P阱上的重掺杂N型区、N阱右部上的重掺杂N型区分别作为NLDMOS器件的源区、漏区引出端;
所述N阱的N型掺杂浓度,大于N型深阱的N型掺杂浓度,并且小于重掺杂N型区的N型掺杂浓度;
所述P阱的P型掺杂浓度,大于P型硅衬底的P型掺杂浓度,并且小于重掺杂P型区的P型掺杂浓度;
所述P型注入区的P型掺杂浓度,大于P型硅衬底的P型掺杂浓度;
所述P型注入区,最左端在所述P阱左侧到所述漂移区场氧右侧之间。
2.一种隔离型NLDMOS器件的制造方法,其特征在于,包括以下工艺步骤:
一、在P型衬底上通过N型离子注入形成N型深阱;
二.利用有源区光刻,打开场氧区域,刻蚀场氧区,生长场氧,在N型深阱左部上形成沟道区场氧,在N型深阱右部上形成漂移区场氧;
三、光刻打开阱注入区域,在沟道区场氧下方及其左右两侧的N型深阱中注入P型杂质离子形成P阱,在漂移区场氧下方及其左右两侧的N型深阱中注入N型杂质离子形成N阱;所述P阱同所述N阱之间有N型深阱间隔区;
四、在硅片上,通过热氧化方法生长栅氧化层;
五、在所述N阱下方的N型深阱中注入P型杂质离子形成P型注入区;
六、在硅片上,淀积多晶硅;然后进行多晶硅栅刻蚀,形成NLDMOS的栅极多晶硅,栅极多晶硅的左部位于P阱右部上方,右部位于N阱左部上方;
七、选择性的进行源漏离子注入,在沟道区场氧左右两侧的P阱上分别形成有一重掺杂P型区及一重掺杂N型区,在漂移区场氧右侧的N阱上形成有一重掺杂N型区;
八、通过传统的接触孔工艺形成接触孔连接,通过接触孔和金属线引出电极;
P阱上的重掺杂P型区作为P阱引出端;
P阱上的重掺杂N型区、N阱上的重掺杂N型区分别作为NLDMOS器件的源区、漏区引出端。
3.根据权利要求2所述的隔离型NLDMOS器件的制造方法,其特征在于,
步骤五中,P型注入区的P型注入为硼离子,能量为800KeV到1500KeV,剂量为1E11到1E13个每平方厘米。
4.根据权利要求2所述的隔离型NLDMOS器件的制造方法,其特征在于,
步骤五中,P型注入区左端在P阱与漂移区场氧之间。
CN201510033372.9A 2015-01-22 2015-01-22 隔离型nldmos器件及其制造方法 Active CN104659079B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510033372.9A CN104659079B (zh) 2015-01-22 2015-01-22 隔离型nldmos器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510033372.9A CN104659079B (zh) 2015-01-22 2015-01-22 隔离型nldmos器件及其制造方法

Publications (2)

Publication Number Publication Date
CN104659079A CN104659079A (zh) 2015-05-27
CN104659079B true CN104659079B (zh) 2017-12-05

Family

ID=53249999

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510033372.9A Active CN104659079B (zh) 2015-01-22 2015-01-22 隔离型nldmos器件及其制造方法

Country Status (1)

Country Link
CN (1) CN104659079B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9391111B1 (en) * 2015-08-07 2016-07-12 Omnivision Technologies, Inc. Stacked integrated circuit system with thinned intermediate semiconductor die

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4587003B2 (ja) * 2008-07-03 2010-11-24 セイコーエプソン株式会社 半導体装置
JP4772843B2 (ja) * 2008-09-17 2011-09-14 シャープ株式会社 半導体装置及びその製造方法
JP2011100847A (ja) * 2009-11-05 2011-05-19 Sharp Corp 半導体装置及びその製造方法
CN104064596B (zh) * 2013-03-19 2016-11-02 上海华虹宏力半导体制造有限公司 Nldmos器件及其制造方法

Also Published As

Publication number Publication date
CN104659079A (zh) 2015-05-27

Similar Documents

Publication Publication Date Title
CN101510561B (zh) 超结纵向双扩散金属氧化物半导体管
CN107316899B (zh) 半超结器件及其制造方法
CN103178093B (zh) 高压结型场效应晶体管的结构及制备方法
CN102044563A (zh) Ldmos器件及其制造方法
CN101552291A (zh) N沟道超结纵向双扩散金属氧化物半导体管
CN104617149B (zh) 隔离型nldmos器件及其制造方法
CN107910374A (zh) 超结器件及其制造方法
CN105047694B (zh) 一种横向高压功率器件的结终端结构
CN103178087A (zh) 超高压ldmos器件结构及制备方法
CN107785411A (zh) 集成有结型场效应晶体管的器件及其制造方法
CN107785366A (zh) 集成有结型场效应晶体管的器件及其制造方法
CN104009087B (zh) 一种静电屏蔽效应晶体管及其设计方法
CN103390545A (zh) 改善沟槽型nmos漏源击穿电压的方法及其结构
CN107785365A (zh) 集成有结型场效应晶体管的器件及其制造方法
CN105140289A (zh) N型ldmos器件及工艺方法
CN103515443A (zh) 一种超结功率器件及其制造方法
CN104332501B (zh) Nldmos器件及其制造方法
CN104659079B (zh) 隔离型nldmos器件及其制造方法
CN105140269B (zh) 一种横向高压功率器件的结终端结构
CN106876439A (zh) 超结器件及其制造方法
CN103811402B (zh) 一种超高压bcd工艺的隔离结构制作工艺方法
CN107919398A (zh) 半超结器件及其制造方法
CN108172623A (zh) 一种高能注入埋层双通道ldmos器件及其制造方法
CN105576022B (zh) 具有超结结构的半导体器件及其制备方法
CN105576021B (zh) Nldmos器件及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant