CN104620384B - Soi晶圆的制造方法 - Google Patents

Soi晶圆的制造方法 Download PDF

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Publication number
CN104620384B
CN104620384B CN201380047666.6A CN201380047666A CN104620384B CN 104620384 B CN104620384 B CN 104620384B CN 201380047666 A CN201380047666 A CN 201380047666A CN 104620384 B CN104620384 B CN 104620384B
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China
Prior art keywords
wafer
bonded
oxide film
soi
bonded wafer
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CN201380047666.6A
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English (en)
Chinese (zh)
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CN104620384A (zh
Inventor
阿贺浩司
石塚徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin-Etsu Handotai Co Ltd
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Shin-Etsu Handotai Co Ltd
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Publication of CN104620384A publication Critical patent/CN104620384A/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments

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  • Element Separation (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
CN201380047666.6A 2012-11-21 2013-10-11 Soi晶圆的制造方法 Active CN104620384B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012-255719 2012-11-21
JP2012255719A JP5821828B2 (ja) 2012-11-21 2012-11-21 Soiウェーハの製造方法
PCT/JP2013/006072 WO2014080563A1 (ja) 2012-11-21 2013-10-11 Soiウェーハの製造方法

Publications (2)

Publication Number Publication Date
CN104620384A CN104620384A (zh) 2015-05-13
CN104620384B true CN104620384B (zh) 2017-06-06

Family

ID=50775761

Family Applications (1)

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CN201380047666.6A Active CN104620384B (zh) 2012-11-21 2013-10-11 Soi晶圆的制造方法

Country Status (7)

Country Link
US (1) US9378999B2 (enExample)
EP (1) EP2924736B1 (enExample)
JP (1) JP5821828B2 (enExample)
KR (1) KR101910100B1 (enExample)
CN (1) CN104620384B (enExample)
SG (1) SG11201501873QA (enExample)
WO (1) WO2014080563A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6556511B2 (ja) * 2015-06-17 2019-08-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN110085549B (zh) * 2018-01-26 2021-06-04 沈阳硅基科技有限公司 一种双面注入得到soi的方法
CN110544668B (zh) 2018-05-28 2022-03-25 沈阳硅基科技有限公司 一种通过贴膜改变soi边缘stir的方法
CN109360805A (zh) * 2018-09-28 2019-02-19 沈阳硅基科技有限公司 一种图形soi硅片的制备方法
CN115188703B (zh) * 2022-05-16 2025-09-19 绍兴中芯集成电路制造股份有限公司 一种soi晶圆及制造方法
FR3146019B1 (fr) * 2023-02-16 2026-07-24 Soitec Silicon On Insulator Procédé de formation d’une zone de fragisilation dans un substrat semi-conducteur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0955671B1 (en) * 1998-04-23 2006-12-06 Shin-Etsu Handotai Company Limited A method of recycling a delaminated wafer and a silicon wafer used for the recycling
US20070069335A1 (en) * 2003-09-08 2007-03-29 Akihiko Endo Bonded wafer and its manufacturing method
CN101124657A (zh) * 2005-02-28 2008-02-13 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆
CN102986020A (zh) * 2010-06-30 2013-03-20 康宁股份有限公司 对绝缘体基材上的硅进行精整的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0355822A (ja) 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH0680624B2 (ja) * 1990-02-28 1994-10-12 信越半導体株式会社 接合ウエーハの製造方法
JP3422225B2 (ja) * 1997-07-08 2003-06-30 三菱住友シリコン株式会社 貼り合わせ半導体基板及びその製造方法
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince
JP4398934B2 (ja) 2005-02-28 2010-01-13 信越半導体株式会社 Soiウエーハの製造方法
JP5233111B2 (ja) 2006-11-30 2013-07-10 株式会社Sumco 貼り合わせsoiウェーハの製造方法
US7902039B2 (en) 2006-11-30 2011-03-08 Sumco Corporation Method for manufacturing silicon wafer
JP2011187502A (ja) * 2010-03-04 2011-09-22 Seiko Epson Corp 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0955671B1 (en) * 1998-04-23 2006-12-06 Shin-Etsu Handotai Company Limited A method of recycling a delaminated wafer and a silicon wafer used for the recycling
US20070069335A1 (en) * 2003-09-08 2007-03-29 Akihiko Endo Bonded wafer and its manufacturing method
CN101124657A (zh) * 2005-02-28 2008-02-13 信越半导体股份有限公司 贴合晶圆的制造方法及贴合晶圆
CN102986020A (zh) * 2010-06-30 2013-03-20 康宁股份有限公司 对绝缘体基材上的硅进行精整的方法

Also Published As

Publication number Publication date
JP2014103329A (ja) 2014-06-05
CN104620384A (zh) 2015-05-13
KR20150087181A (ko) 2015-07-29
EP2924736A1 (en) 2015-09-30
EP2924736B1 (en) 2017-08-30
US9378999B2 (en) 2016-06-28
US20150243550A1 (en) 2015-08-27
WO2014080563A1 (ja) 2014-05-30
JP5821828B2 (ja) 2015-11-24
EP2924736A4 (en) 2016-06-29
KR101910100B1 (ko) 2018-10-19
SG11201501873QA (en) 2015-05-28

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