CN104620376A - 用于2.5d中介板的设备和方法 - Google Patents

用于2.5d中介板的设备和方法 Download PDF

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Publication number
CN104620376A
CN104620376A CN201380046817.6A CN201380046817A CN104620376A CN 104620376 A CN104620376 A CN 104620376A CN 201380046817 A CN201380046817 A CN 201380046817A CN 104620376 A CN104620376 A CN 104620376A
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semiconductor chip
semiconductor
intermediate plate
semiconductor packages
packages according
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CN104620376B (zh
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安瓦尔·穆罕默德
刘伟锋
牛瑞
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Abstract

在2.5D半导体封装配置中，可使用基于聚酰亚胺的再分配层(RDL)减轻施加在连接到中介板的导电互连上的热机械应力。基于聚酰亚胺的RDL位于中介板的上或下面。此外，可通过使用不同直径的微凸块、不同高度的铜柱或多层中介板减少或消除2.5D半导体封装中横向相邻的半导体芯片之间的高度差异，从而相对于矮半导体芯片降低高半导体芯片。

Description

用于2.5D中介板的设备和方法
相关申请案交叉申请
本发明要求2012年9月10日递交的发明名称为“用于2.5D中介板的设备和方法(Devices and Methods for 2.5D Interposers)”的第61/699084号美国临时申请案以及2013年5月17日递交的发明名称为“用于2.5D中介板的设备和方法(Devices and Methods for 2.5D Interposers)”的第13/897156号美国专利申请案的在先申请优先权，这两个在先申请的内容以引用的方式并入本文中，如同全文再现一般。
技术领域
本发明涉及用于电子封装的设备和方法，以及在具体实施例中，涉及用于2.5D中介板的设备和方法。
背景技术
2.5D封装和互连技术是很有前途的半导体封装技术，相比3D封装技术，2.5D封装技术可以实现更低的成本和更好的可靠性。
2.5D封装技术允许在中介板上集成同类或非同类芯片以提高性能和微型化。
2.5D半导体封装中一个潜在的可靠性问题是施加在连接到中介板的导电互连上的热机械应力。例如，在并入了无机中介板(例如硅中介板)的2.5D半导体封装中，无机中介板和有机基板之间的热膨胀系数(CTE)不匹配可能对将无机中介板连接到基板的导电互连(例如可控坍塌芯片连接(C4)凸块)施加应力。或者，在并入了无机中介板的2.5D半导体封装中，有机基板和无机半导体芯片之间的CTE不匹配可能对将半导体芯片连接到中介板的导电互连(例如微凸块)施加热机械应力。无论如何，需要用于减轻施加在导电互连上的热机械应力的技术，这些导电互连将中介板连接到2.5D封装中的基板/半导体芯片。
当横向相邻的半导体芯片具有不同的高度，会出现2.5D半导体封装中另一个潜在的可靠性和/或功能性问题。具体而言，高度差异可增加高芯片在制造时被割坏(或损坏)的可能性，因为当在矮芯片上执行制造过程(例如挂接等)时，高芯片可能容易受到攻击。此外，高度差异可约束2.5D半导体芯片的功能。例如，高度差异可阻止两个芯片共享公共散热片。因此，需要用于减少2.5D半导体封装中横向相邻的半导体芯片之间的高度差异的技术。
发明内容
本发明的实施例描述了用于2.5D中介板的设备和方法，从而大体上实现了技术上的优势。
根据实施例，提供一种半导体封装。在该示例中，所述半导体封装包括有机基板、两个或更多半导体芯片以及位于所述有机基板和所述两个或更多半导体芯片之间的中介板。所述中介板包含再分配层，所述再分配层包括一个或多个基于聚酰亚胺的介电层。
根据另一实施例，提供另一种半导体封装。在该示例中，所述半导体封装包含中介板、挂接到所述中介板顶面的第一半导体芯片以及附于所述中介板的所述顶面的第二半导体芯片。根据2.5D半导体封装配置，所述第二半导体芯片邻近所述第一半导体芯片。所述第二半导体芯片高于所述第一半导体芯片，并且所述第一半导体芯片高于所述第二半导体芯片挂接。
根据又一实施例，提供又一种半导体封装。在该示例中，所述半导体封装包含多层中介板，所述多层中介板包括具有第一层和第二层的上中介板面。所述半导体封装进一步包括挂接到所述上中介板面的所述第一层的第一半导体芯片，以及挂接到所述上中介板面的所述第二层的第二半导体芯片。根据2.5D半导体封装配置，所述第二半导体芯片与所述第一半导体芯片横向相邻。所述第二半导体芯片的高度超过所述第一半导体芯片的高度。所述上中介板面的所述第一层相对于所述上中介板面的所述第二层提升。
附图说明
为了更完整地理解本发明及其优点，现在参考下文结合附图进行的描述，其中：
图1示出了2.5D半导体封装的图；
图2示出了另一2.5D半导体封装的图；
图3示出了实施例2.5D半导体封装的图；
图4示出了另一实施例2.5D半导体封装的图；
图5示出了具有共享散热片的2.5D半导体封装的图；
图6示出了具有不同高度的半导体芯片的2.5D半导体封装的图；
图7示出了又一实施例2.5D半导体封装的图；
图8示出了又一实施例2.5D半导体封装的图；
图9示出了又一实施例2.5D半导体封装的图；以及
图10示出了实施例制造设备的方框图。
除非另有指示，否则不同图中的对应标号和符号通常指代对应部分。绘制各图是为了清楚地说明实施例的相关方面，因此未必是按比例绘制的。
具体实施方式
下文将详细论述对本发明实施例的实施和使用。然而，应了解，本发明提供可在各种具体上下文中体现的许多适用的发明性概念。所论述的具体实施例仅仅说明用以实施和使用本发明的具体方式，而不限制本发明的范围。
本发明的各方面提供用于减轻由于无机中介板和有机基板之间或有机基板与半导体芯片之间的CTE不匹配而施加在导电互连上的热机械应力的技术。具体而言，本发明的实施例在中介板的面上部署基于聚酰亚胺的再分配层(RDL)，其比传统介电层更有弹性，从而充当更有效的缓冲器，用于减轻导电互连(例如C4凸块、微凸块等)上的应力。
本发明的附加方面提供用于减少2.5D半导体封装中的横向相邻的半导体芯片之间的高度差异的各种技术。在一项示例中，使用直径较大的微凸块将矮半导体芯片连接到中介板，从而使得矮半导体芯片相对于高半导体芯片提升。在另一示例中，使用铜柱提升矮半导体芯片。在又一示例中，高半导体芯片下的一部分中介板被蚀刻以相对于矮半导体芯片降低高半导体芯片。
图1示出了2.5D半导体封装100，其包括基板110、中介板140和半导体芯片180至190。基板110可由有机或无机材料组成，并作为半导体设备在基板110之上建立的基础。中介板140可包括有机或无机材料，并作为半导体芯片180至190和基板110之间的接口。半导体芯片180至190可由半导体材料组成，功能集成电路在该半导体材料上制造。基板110通过一个或多个焊球105导电耦合到印刷电路板(PCB)(未示出)，中介板140通过一个或多个可控坍塌芯片连接(C4)凸块120导电耦合到基板110，并且半导体芯片180至190通过微凸块160导电耦合到中介板140。焊球105、C4凸块120和微凸块160各自的大小取决于2.5D半导体封装100的设计和/或功能特性。
需注意的是，2.5D半导体封装100区别于其他半导体封装设计(例如3D或其他)，因为它包括两个或更多横向相邻的半导体芯片180至190。相比之下，3D半导体封装配置将在单一垂直列中堆叠两个或更多芯片。
图2示出了2.5D半导体封装200，其包括基板210、C4凸块220、中介板240、微凸块260和半导体芯片280。需注意的是，2.5D半导体封装200包括一个或多个与半导体芯片280横向相邻的附加半导体芯片。出于清楚和简洁的目的，图2中省略了附加半导体芯片。中介板240通过C4凸块220导电耦合到基板210，并且半导体芯片280通过微凸块260导电耦合到中介板240。中介板240可包含下RDL230和上RDL250以及导电孔241。下RDL230包含导电层234以及两个或更多介电层236和237。同样地，上RDL250包含导电层254以及两个或更多介电层256和257。导电层234、254可由铜或一些其他导电材料组成。可使用下溢层232将C4凸块220连接到下RDL230的导电层234，并可使用下溢层252将微凸块260连接到上RDL250。
中介板240可由有机或无机核心组成。当中介板240的核心由无机化合物(例如硅等)组成，在2.5D半导体封装200的热循环期间，中介板240和基板210之间所产生的CTE不匹配对导电互连(例如C4凸块220等)施加应力。同样地，当中介板240的核心由有机化合物组成，在热循环期间，中介板240和半导体芯片280之间所产生的CTE不匹配对导电互连(例如微凸块260等)施加应力。在介电层236和237、256和257使用Si02或Si3N4的常规做法并不能减轻由CTE不匹配导致的应力，因为Si02或Si3N4相对缺乏弹性。
本发明的各方面利用基于聚酰亚胺的RDL减轻施加在连接到中介板的导电互连上的热机械应力。具体而言，基于聚酰亚胺的RDL包含主要(或完全)由聚酰亚胺(PI)化合物组成的径向层，PI化合物比Si02、Si3N4和其他常规介电化合物更有弹性。因此，在减轻热机械应力方面，基于聚酰亚胺的RDL比常规RDL更有效，从而在2.5D半导体封装配置中提高连接到中介板的导电互连的鲁棒性/可靠性。
可使用基于聚酰亚胺的RDL增加有机中介板和半导体芯片之间的微凸块的鲁棒性。图3示出了实施例2.5D半导体封装300，其包括有机中介板340、微凸块360和半导体芯片380。需注意的是，出于清楚和简洁的目的，图3中省略了基板和附加的横向相邻的半导体芯片。如图所示，有机中介板340包括基于聚酰亚胺的RDL350，其包含导电层354和多个聚酰亚胺介电层356和357。聚酰亚胺介电层356和357比由常规介电材料(例如Si02、Si3N4等)组成的介电层更具弹性，从而更有效地减轻由于有机中介板340和半导体芯片380之间的CTE不匹配导致的热机械应力。
还可使用基于聚酰亚胺的RDL增加C4凸块的鲁棒性，C4凸块将无机中介板耦合到有机基板。图4示出了实施例2.5D半导体封装400，其包括有机基板410、C4凸块420和无机中介板440。需注意的是，出于清楚和简洁的目的，图4中省略了横向相邻的半导体芯片。如图所示，无机中介板440包括基于聚酰亚胺的RDL430，其包含导电层434和多个聚酰亚胺介电层436和437。聚酰亚胺介电层436和437比由常规介电材料(例如Si02、Si3N4等)组成的介电层更具弹性，从而更有效地减轻由于无机中介板440和有机基板410之间的CTE不匹配导致的热机械应力。
一些2.5D半导体封装设计可包含在两个或更多横向相邻的半导体芯片之间共享的散热片。图5示出了2.5D半导体封装500，其包括焊球505、基板510、C4凸块520、中介板540、微凸块560、半导体芯片580至590和散热片595。如图所示，半导体芯片580的高度与半导体芯片590的高度相似(例如H1≈H2)，这允许半导体芯片580至590轻松地共享散热片595。
一些半导体芯片具有不同的厚度/高度。例如，用于执行处理操作的半导体芯片与用于充当存储器的半导体芯片可能具有不同的厚度/高度。当在2.5D封装中实施为横向相邻的芯片时，具有不同高度的半导体芯片可能限制设计/功能和/或降低制造可靠性。图6示出了2.5D半导体封装600，其包括焊球605、基板610、C4凸块620、中介板640、微凸块660和半导体芯片680至690。如图所示，半导体芯片680矮于半导体芯片690，这可对半导体芯片680至690之间的散热片(或另一部件/资源)的共享造成困难(或阻碍)。此外，半导体芯片680至690之间的高度差异可增加半导体芯片690在2.5D半导体封装600的制造过程中被割坏(或损坏)的可能性。
本发明的各方面提供用于减少2.5D半导体封装中的横向相邻的半导体芯片之间的高度差异的各种技术。其中一种技术使用大直径的微凸块将矮半导体芯片连接到中介板以相对于高半导体芯片提升矮半导体芯片。图7示出了2.5D半导体封装700，其包括焊球705、基板710、C4凸块720、中介板740、微凸块760至765以及半导体芯片780至790。如图所示，微凸块765的直径大于微凸块760的直径，从而相对于半导体芯片790提升半导体芯片780。因此，半导体芯片780与半导体芯片790具有相似的绝对高度(例如H1≈H2)。
另一技术使用铜柱来相对于高半导体芯片提升矮半导体芯片。图8示出了2.5D半导体封装800，其包括焊球805、基板810、C4凸块820、中介板840、微凸块860、铜柱865和半导体芯片880至890。如图所示，铜柱865的高度超过微凸块860的直径，从而相对于半导体芯片890提升半导体芯片880。因此，半导体芯片880、890具有相似的绝对高度(例如H1≈H2)。在实施例中，一个或多个微凸块860可与矮于铜柱865的铜柱进行交换，这对相对于半导体芯片890提升半导体芯片880具有相似的效果。
另一技术使用双层中介板来相对于矮半导体芯片降低高半导体芯片。图9示出了2.5D半导体封装900，其包括焊球905、基板910、C4凸块920、双层中介板940、微凸块960和半导体芯片980至990。可通过蚀刻半导体芯片990下的部分中介板940创建双层中介板940，以相对于半导体芯片980降低半导体芯片990。因此，半导体芯片980至990具有相似的绝对高度(例如H1≈H2)。
在实施例中，高半导体芯片的高度/厚度可超过矮半导体芯片的高度/厚度至少50微米。本文中所描述的技术可减少挂接芯片的最高点之间的垂直间隔到不同程度。例如，本发明的实施例可将垂直间隔减少至小于10微米的距离。本发明的另一实施例可将垂直间隔减少至小于5微米的距离。本发明的又一实施例可将垂直间隔减少至小于1微米的距离。
在以中介板为中心的方法中，通过不同材料(Si、GaN、GaAs、SiC等)制造并通过不同纳米技术制作的同类或异类芯片附着到中介板硅芯片(正面、底面、或正面以及底面)上。中介板(通常由硅制成)最小化来宾芯片和宿主中介板之间任何热膨胀系数(CTE)的不匹配。然而，随后硅中介板(具有大约百万分之(PPM)3/℃的CTE)附着到有机基板(具有大约17PPM/℃的CTE)。该CTE不匹配可对将中介板连接至有机基板的焊料C4焊球造成显著的应力。
实施例通过在硅中介板底面提供兼容的基于聚酰亚胺的再分配层(RDL)作为应力缓冲器来减轻该热机械应力。实施例在硅中介板上使用保护应力层来减轻应力。实施例使用一种或多种技术来补偿芯片高度变化。实施例为2.5D半导体封装提高可靠性。
可在谋求微型化的电子领域(例如移动设备、边缘路由器、核心路由器等)中使用实施例。实施例在硅中介板的底面制作RDL以减轻焊块和硅中介板上的应力。
硅主机上的来宾芯片可具有不同的高度。这可引起如硬件附着、处理、可靠性以及全过程中的制造问题。当在芯片的顶部应用散热片时，这还可导致一些热管理问题。本发明的实施例通过在封装中提供大致相等的芯片顶部高度来克服这些问题。在一项示例中，在芯片附着过程之前，厚芯片下的硅中介板区域被蚀刻，使得两个芯片具有相对相等的高度。在另一示例中，改变焊球大小以补偿高度差异。在又一示例中，调整用于将芯片附着到中介板的铜柱的高度以补偿芯片高度变化。
图10示出了实施例制作设备1000的方框图，制作设备1000可用于执行本发明的一个或多个方面。制造设备1000包含处理器1004、存储器1006和多个接口1010至1012，其可(或可不)按图10所示进行排列。处理器1004可以是能够执行计算和/或其他有关处理的任务的任意部件，并且存储器1006可以是能够为处理器1004存储程序和/或指令的任意部件。接口1010至1012可以是允许设备1000与其他设备进行控制指令通信的任意部件或部件集合，这在出厂设置中可能是普通的。
尽管进行了详细的描述，但应理解，可在不脱离由所附权利要求书界定的本发明的精神和范围的情况下，对本文做出各种改变、替代和更改。此外，本发明的范围不希望限于本文中所描述的特定实施例，所属领域的一般技术人员将从本发明中容易了解到，过程、机器、制造工艺、物质成分、构件、方法或步骤(包括目前存在的或以后将开发的)可执行与本文所述对应实施例大致相同的功能或实现与本文所述对应实施例大致相同的效果。因此，所附权利要求书既定在其范围内包括此类过程、机器、制造工艺、物质成分、构件、方法或步骤。

Claims (25)

1.一种半导体封装，其特征在于，包括：
有机基板；
两个或更多半导体芯片；以及
位于2.5D半导体封装配置中的所述有机基板和所述两个或更多半导体芯片之间的中介板，所述中介板包括再分配层，其包括一个或多个基于聚酰亚胺的介电层。
2.根据权利要求1所述的半导体封装，其特征在于，所述中介板包括具有热膨胀系数(CTE)的无机核心，所述热膨胀系数(CTE)比所述有机基板的CTE至少小百万分之五；以及
所述再分配层进一步包括通过导电互连耦合到所述有机基板的一个或多个导电层。
3.根据权利要求2所述的半导体封装，其特征在于，所述中介板包括基于硅的核心。
4.根据权利要求2所述的半导体封装，其特征在于，所述中介板包括玻璃核心。
5.根据权利要求2所述的半导体封装，其特征在于，所述导电互连包括可控坍塌芯片连接(C4)凸块。
6.根据权利要求1所述的半导体封装，其特征在于，所述中介板包括具有热膨胀系数(CTE)的有机核心，所述热膨胀系数(CTE)比所述两个或更多半导体芯片的CTE至少大百万分之五；以及
所述再分配层进一步包括通过导电互连耦合到所述两个或更多半导体芯片的导电层。
7.根据权利要求6所述的半导体封装，其特征在于，所述导电互连包括可控坍塌芯片连接(C4)凸块。
8.根据权利要求1所述的半导体封装，其特征在于，所述两个或更多半导体芯片附于所述中介板的顶面，所述两个或更多半导体芯片彼此横向放置。
9.一种半导体封装，其特征在于，包括：
中介板；
挂接到所述中介板的顶面的第一半导体芯片；以及
附于所述中介板的所述顶面的第二半导体芯片，根据2.5D半导体封装配置，所述第二半导体芯片与所述第一半导体芯片相邻，
其中所述第二半导体芯片高于所述第一半导体芯片；以及
其中所述第一半导体芯片高于所述第二半导体芯片挂接。
10.根据权利要求9所述的半导体封装，其特征在于，所述第二半导体芯片的高度超过所述第一半导体芯片的高度至少50微米。
11.根据权利要求9所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于10微米。
12.根据权利要求9所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于5微米。
13.根据权利要求9所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于1微米。
14.根据权利要求9所述的半导体封装，其特征在于，进一步包括：
将所述第一半导体芯片连接到所述中介板的所述顶面的第一组导电互连；以及
将所述第一半导体芯片连接到所述中介板的所述顶面的第二组导电互连，
其中所述第一组导电互连的高度超过所述第二组导电互连的高度。
15.根据权利要求14所述的半导体封装，其特征在于，所述第一组导电互连包括第一组可控坍塌芯片连接(C4)凸块。
16.根据权利要求15所述的半导体封装，其特征在于，所述第二组导电互连包括第二组C4凸块。
17.根据权利要求16所述的半导体封装，其特征在于，所述第二组C4凸块中的C4凸块比所述第一组C4凸块中的C4凸块具有更小的直径。
18.根据权利要求14所述的半导体封装，其特征在于，所述第一组导电互连包括第一组铜柱。
19.根据权利要求18所述的半导体封装，其特征在于，所述第二组导电互连包括第二组铜柱。
20.根据权利要求19所述的半导体封装，其特征在于，所述第二组铜柱中的铜柱短于所述第一组铜柱中的铜柱。
21.一种半导体封装，其特征在于，包括：
多层中介板，其包括上中介板面，所述上中介板面具有第一层和第二层；
挂接到所述上中介板面的所述第一层的第一半导体芯片；以及
挂接到所述上中介板面的所述第二层的第二半导体芯片，根据2.5D半导体封装配置，所述第二半导体芯片与所述第一半导体芯片横向相邻，
其中所述第二半导体芯片的高度超过所述第一半导体芯片的高度；以及
其中所述上中介板面的所述第一层相对于所述上中介板面的所述第二层提升。
22.根据权利要求21所述的半导体封装，其特征在于，所述第二半导体芯片的高度超过所述第一半导体芯片的高度至少50微米。
23.根据权利要求21所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于10微米。
24.根据权利要求21所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于5微米。
25.根据权利要求21所述的半导体封装，其特征在于，所述第一半导体芯片和第二半导体芯片的最高点之间的垂直间隔小于1微米。
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