CN104576544A - 承载件 - Google Patents
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- CN104576544A CN104576544A CN201310548223.7A CN201310548223A CN104576544A CN 104576544 A CN104576544 A CN 104576544A CN 201310548223 A CN201310548223 A CN 201310548223A CN 104576544 A CN104576544 A CN 104576544A
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- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 11
- 210000002683 foot Anatomy 0.000 description 18
- 238000012545 processing Methods 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012856 packing Methods 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/787—Means for aligning
- H01L2224/78703—Mechanical holding means
- H01L2224/78705—Mechanical holding means in the upper part of the bonding apparatus, e.g. in the capillary or wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
一种承载件,包括承载座、设于该承载座周围的多个导电部与多个支撑条、以及位于该支撑条与该承载座之间且接触连结该承载座的低置结构,使该支撑条与该承载座具有一高度差,且该低置结构与该承载座呈现非共平面。藉此,使该低置结构与承载座的投影面积相连,以于打线制程的固定作业中,该低置结构与承载座均位于固定治具的热板的容置槽中,所以该热板无需额外形成收纳支撑条的开槽,因而不需进行该支撑条的对位,即可完成固定作业,所以能大幅降低制程时间。
Description
技术领域
本发明涉及一种承载件,尤指一种承载半导体组件的承载件。
背景技术
随着电子产业的蓬勃发展,电子产品也逐渐迈向多功能、高性能的趋势。随着电子产业的蓬勃发展,许多电子产品都逐渐朝往轻、薄、短、小等高集积度方向发展,半导体封装件也发展出许多种不同的封装模块,例如,覆晶封装(Flip Chip Package)、打线接合(Wire Bond)等。
目前打线接合技术常以导线架作为承载芯片的承载件。如图1A所示,现有打线式封装件9中,其导线架1包含一承载芯片90的承载座(die pad)10、位于该承载座10角落的多个支撑肋条(tie bar)13(如图1C所示)、及位于该承载座10边缘的多个导脚12,各该导脚12具有外脚部(outer leads portion)120及内脚部(inner leadsportion)121,且该外脚部120用以电性连接至一外部电路(图未示)。该芯片90以银胶90a固着于该承载座10上,且该芯片90具有多个焊垫900,以利用多个导线(bonding wire)91电性连接该导脚12的内脚部121。又藉由如环氧树脂(epoxy)制成绝缘材料的封装胶体92包覆该芯片90、承载座10、导脚12的内脚部121、及焊线91。另外,该支撑肋条13相对该承载座10倾斜且设有低置(down set)结构11,以降低该承载座20的位置,使该承载座20的位置低于该内脚部121的位置,且于封装时平衡上、下模流空间。
于现有封装件9进行打线制程时,需以固定治具将导线架与芯片固定至打线机台上。如图1B所示,现有固定治具8包括一热板80、二轨道81及一窗型压板82。该热板80具有一吸附面80a,用以支撑一承载有多个芯片90的导线架版面1’,并提供热能至该导线架版面1’,以利于打线制程。所述的导线架版面1’具有多个如图1A所示的导线架1,待封装后,再进行切单制程,以获取多个具有该导线架1的封装件9。此外,该些轨道81位于该热板80的二侧,以支撑该导线架版面1’的二侧,且该窗型压板82用以压合该导线架版面1’的上侧。
于置放该导线架版面1’时,如图1C及图1C’所示,该导线架1对应置放于该热板80的容置槽800中,且因该低置结构11的两侧接触连结该支撑肋条13,所以该热板80需额外形成开槽801,供该支撑肋条13的部分结构及该低置结构11位于该开槽801上方,使该热板80避开该低置结构11,以避免该低置结构11受热变形。惟,于制作不同产品而更换该导线架1时,需更换该热板80,所以需将该支撑肋条13精准的调整至该热板80的开槽801的中心点,以将该低置结构11置放于该开槽801中,因而往往造成整个制程时间增加,致使不利量产。
此外,相邻该支撑肋条13的导脚12’经常会位移至该开槽801内,致使该导脚12’悬空,因而不能进行焊接该导线91的作业,导致良率降低。
另外,目前该导线架1的制作中,该内脚部121的间距(Inner LeadPitch,ILP)设计有越来越小的趋势,如ILP为0.148㎜以下,致使上述问题更为严重。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失,本发明的主要目的为揭露一种承载件,能大幅降低制程时间。
本发明的承载件包括:一承载座;多个导电部,其设于该承载座周围;多个支撑条,其设于该承载座周围;以及至少一低置结构,其位于该支撑条与该承载座之间且接触连结该承载座,使该支撑条与该承载座具有一高度差,且该低置结构与该承载座非共平面。
前述的承载件中,该承载件为导线架,且该承载座用以承载半导体组件。
前述的承载件中,该承载座的边缘具有转折处,且该支撑条位于该转折处,例如,该承载座为多边形。
前述的承载件中,该低置结构具有相对的第一侧与第二侧,该第一侧接触结合该承载座,且该第二侧接触结合该支撑条,例如,该第一侧与第二侧之间的距离为0.15至0.3㎜。
另外,前述的承载件中,该低置结构为架体,且相对该承载座倾斜,例如,该低置结构与该承载座形成一夹角,如30度角至50度角。
由上可知,本发明的承载件,藉由该低置结构接触连结该承载座,使该低置结构与该承载座的投影面积相连,以令打线制程用的固定治具的热板无需额外形成开槽,所以相邻该支撑条的导电部不会产生悬空状态,因而能顺利进行焊接导线的作业,致使良率提高。
此外,于量产中更换该承载件及该热板时,只需将该低置结构与该承载座置放于该容置槽中即可,而不需进行该支撑条的对位,所以相较于现有技术,本发明的承载件能大幅降低打线制程的时间,因而有利于量产。
附图说明
图1A为现有半导体封装件的剖面示意图;
图1B为现有打线制程的固定作业的立体示意图;
图1C为现有导线架与热板的局部上视示意图;其中,图1C’为图1C的剖面示意图;以及
图2为本发明的承载件与热板的局部上视示意图;其中,图2’为图2的剖视图。
符号说明
1 导线架
1’ 导线架版面
10,20 承载座
11,21 低置结构
12,12’ 导脚
120 外脚部
121 内脚部
13 支撑肋条
2 承载件
20a 转折处
21a 第一侧
21b 第二侧
22,22’ 导电部
23 支撑条
8 固定治具
80,70 热板
80a 吸附面
800,700 容置槽
801 开槽
81 轨道
82 窗型压板
9 封装件
90 芯片
90a 银胶
900 焊垫
91 导线
92 封装胶体
h 高度差
L 距离
θ 夹角。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式,熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技艺的人士的了解与阅读,并非用以限定本发明可实施的限定条件,所以不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”、及“一”等用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2及图2’为本发明的承载件2及其应用于打线制程的示意图。
如图2所示,所述的承载件2为导线架,其包括:一承载座20、设于该承载座20周围的多个导电部22与多个支撑条23、以及接触连结该承载座20的至少一低置结构21。
所述的承载座20用以承载如芯片的半导体组件(图略)。于本实施例中,该承载座20的边缘具有转折处20a,例如,该承载座20为矩形,且该转折处20a为角落。
所述的导电部22为导脚而位于该承载座20的边缘外,而所述的支撑条23为较该导脚宽的支撑肋条,且该支撑条23位于该承载座20的转折处20a。
所述的低置结构21为网状片形架体,其位于该支撑条23与该承载座20之间,且相对该承载座20倾斜,使该支撑条23与该承载座20具有一高度差h,如图2’所示,以令该低置结构21与该承载座20呈现非共平面。
于本实施例中,该低置结构21具有相对的第一侧21a与第二侧21b,该第一侧21a接触结合该承载座20的转折处20a,且该第二侧21b接触结合该支撑条23。
此外,该第一侧21a与第二侧21b之间的距离L为0.15至0.3㎜,如图2’所示。
又,该低置结构21相对该承载座20倾斜,因而该低置结构21与该承载座20(或热板70)形成一夹角θ,如图2’所示,且该夹角θ为30°至50°。
另外,当该承载座20为矩形或其它几何形状时,该低置结构21的数量可依需求设计,于该承载座20周围设计至少一低置结构21即可,例如,于矩形承载座20的至少一转折处20a上设有该低置结构21;若该转折处20a上未设计有该低置结构21,则该支撑条23接触结合该承载座20的转折处20a。
本发明的低置结构21接触连结该承载座20,使该低置结构21与该承载座20的投影面积相连,所以于打线制程的固定作业中,该低置结构21与该承载座20均位于固定治具(图略)的一热板70的容置槽700中,如图2所示,因而该热板70上无需形成如同现有技术的用以收纳该支撑条23的开槽。
因此,于更换该承载件2及该热板70时,只需将该低置结构21与该承载座20置放于该容置槽700中,而不需将该支撑条23进行对位,即可完成固定作业,所以能大幅降低制程时间,因而利于量产。
此外,因该热板70上并无开槽,所以即使相邻该支撑条23的导电部22’产生位移,仍不会呈现悬空状态,因而能顺利进行焊接导线的作业,以有效提高良率。
综上所述,本发明的承载件,主要藉由该低置结构接触连结该承载座,使该低置结构与该承载座的投影面积相连,以令打线制程用的固定治具的热板无需额外形成开槽,所以不仅利于量产,且能提高良率。
上述实施例仅用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟习此项技艺的人士均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。
Claims (10)
1.一种承载件,其包括:
一承载座;
多个导电部,其设于该承载座周围;
多个支撑条,其设于该承载座周围;以及
至少一低置结构,其位于该支撑条与该承载座之间且接触连结该承载座,使该支撑条与该承载座具有一高度差,且该低置结构与该承载座非共平面。
2.根据权利要求1所述的承载件,其特征在于,该承载件为导线架。
3.根据权利要求1所述的承载件,其特征在于,该承载座用以承载半导体组件。
4.根据权利要求1所述的承载件,其特征在于,该承载座的边缘具有转折处,且该支撑条位于该转折处。
5.根据权利要求4所述的承载件,其特征在于,该承载座为多边形。
6.根据权利要求1所述的承载件,其特征在于,该低置结构具有相对的第一侧与第二侧,该第一侧接触结合该承载座,且该第二侧接触结合该支撑条。
7.根据权利要求6所述的承载件,其特征在于,该第一侧与第二侧之间的距离为0.15至0.3㎜。
8.根据权利要求1所述的承载件,其特征在于,该低置结构为架体,且相对该承载座倾斜。
9.根据权利要求1所述的承载件,其特征在于,该低置结构与该承载座形成一夹角。
10.根据权利要求9所述的承载件,其特征在于,该夹角为30度角至50度角。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4672418A (en) * | 1984-04-11 | 1987-06-09 | Peter Moran | Integrated circuit packages |
US5986333A (en) * | 1997-02-27 | 1999-11-16 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus and method for fabricating the same |
CN101459154A (zh) * | 2007-12-11 | 2009-06-17 | 晶致半导体股份有限公司 | 导线架及应用该导线架的封装结构 |
CN202003989U (zh) * | 2011-03-23 | 2011-10-05 | 南通富士通微电子股份有限公司 | 一种半导体封装框架 |
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TW201203627A (en) * | 2010-07-15 | 2012-01-16 | Lextar Electronics Corp | Light emitting diode and method for forming supporting frame thereof and improved structure of the supporting frame |
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US4672418A (en) * | 1984-04-11 | 1987-06-09 | Peter Moran | Integrated circuit packages |
US5986333A (en) * | 1997-02-27 | 1999-11-16 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus and method for fabricating the same |
CN101459154A (zh) * | 2007-12-11 | 2009-06-17 | 晶致半导体股份有限公司 | 导线架及应用该导线架的封装结构 |
CN202003989U (zh) * | 2011-03-23 | 2011-10-05 | 南通富士通微电子股份有限公司 | 一种半导体封装框架 |
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