CN205723519U - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN205723519U CN205723519U CN201620252089.5U CN201620252089U CN205723519U CN 205723519 U CN205723519 U CN 205723519U CN 201620252089 U CN201620252089 U CN 201620252089U CN 205723519 U CN205723519 U CN 205723519U
- Authority
- CN
- China
- Prior art keywords
- circuit board
- semiconductor devices
- die pad
- bonding
- framework
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000012790 adhesive layer Substances 0.000 claims description 13
- 239000010410 layer Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 8
- 238000003466 welding Methods 0.000 claims description 8
- 239000007769 metal material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 239000006185 dispersion Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229920000106 Liquid crystal polymer Polymers 0.000 description 1
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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Abstract
本实用新型涉及一种半导体器件,可以包括具有开口的电路板、以及框架。该框架可以具有在该开口中的IC裸片焊盘、以及从该IC裸片焊盘向外延伸并且耦接至该电路板的多个臂。该半导体器件可以包括:安装在该IC裸片焊盘上的IC;将该电路板与该IC相耦接的多条键合接线;以及包围该IC、这些键合接线和这些臂的包封材料。
Description
技术领域
本披露涉及半导体器件。
背景技术
在具有集成电路(IC)的电子器件中,IC通常安装到电路板上。为了电耦接在电路板和IC之间的连接,通常对IC进行“封装”。IC封装通常提供用于物理地保护IC的小型封套并且提供用于耦接至电路板的接触焊盘。在一些应用中,封装的IC可以经由焊料凸块耦接到电路板。
一种IC封装的方案包括四方扁平无引线(QFN)封装体。QFN封装体可以提供一些优点,诸如减小引线电感、紧密芯片尺寸占用面积、薄剖面和低重量。并且,QFN封装体通常包括周边I/O焊盘以易于电路板迹线布线,并且暴露的铜裸片焊盘技术提供了增强的热性能和电性能。QFN封装体可以很好地适用于其中尺寸、重量以及热性能和电性能重要的应用。
具体地,由于封装工艺中某些材料的热膨胀系数(CTE)不匹配,最终的IC器件中可能存在一些缺陷。例如,CTE不匹配会在最终的IC器件中引起断裂和间断。并且,载体带或衬底会翘曲,即,产生晶圆弓曲。
实用新型内容
为了解决现有技术的上述问题,本实用新型提供了一种半导体器件,能够避免封装工艺中某些材料的热膨胀系数不匹配而造成的断裂并以有利的方式进行封装。
根据本实用新型的一个方面,半导体器件包括:电路板,所述电路板在其中具有开口;框架,所述框架包括在所述开口中的集成电路(IC)裸片焊盘、以及从所述IC裸片焊盘向外延伸并且耦接至所述电路板的多个臂;安装在所述IC裸片焊盘上的至少一个IC;多条键合接线,所述多条键合接线将所述电路板与所述至少一个IC耦接;以及包封材料,所述包封材料包围所述至少一个IC、所述多条键合接线、以及所述多个臂。
根据一个实施例,所述IC裸片焊盘具有第一和第二相反表面,所述第一相反表面与所述至少一个IC相邻,所述第二相反表面通过所述电路板的所述开口而外露。
根据一个实施例,所述IC裸片焊盘是矩形形状的;并且其中,每个臂在对角线方向上从所述矩形形状的IC裸片焊盘的对应角向外延伸。
根据一个实施例,所述IC裸片焊盘和所述电路板具有多个相邻对齐的底部表面。
根据一个实施例,所述电路板包括电介质层、以及由所述电介质层承载并且分别耦接至所述多条键合接线的多条导电迹线。
根据一个实施例,所述至少一个IC包括衬底、以及由所述衬底承载并且分别耦接至所述多条键合接线的多个键合焊盘。
根据一个实施例,进一步包括在所述多个臂的多个对应的远端与所述电路板之间的粘合层。
根据一个实施例,进一步包括在所述至少一个IC与所述IC裸片焊盘之间的粘合层。
根据一个实施例,所述框架包括金属材料。
根据一个实施例,所述包封材料包围所述电路板和所述框架的多条周边边缘。
根据本实用新型的另一方面,半导体器件包括:电路板,所述电路板在其中具有开口;框架,所述框架包括在所述开口中的矩形形状的集成电路(IC)裸片焊盘、以及在对角线方向上从所述矩形形状的IC裸片焊盘的多个对应的角向外延伸并且耦接至所述电路板的多个臂;安装在所述矩形形状的IC裸片焊盘上的至少一个IC;所述矩形形状的IC裸片焊盘具有第一和第二相反表面,所述第一相反表面与所述至少一个IC相邻,所述第二相反表面通过所述电路板的所述开口而外露;多条键合接线,所述多条键合接线将所述电路板与所述至少一个IC耦接;以及包封材料,所述包封材料包围所述至少一个IC、所述多条键合接线、以及所述多个臂。
根据一个实施例,所述矩形形状的IC裸片焊盘和所述电路板具有多个相邻对齐的底部表面。
根据一个实施例,所述电路板包括电介质层、以及由所述电介质层承载并且分别耦接至所述多条键合接线的多条导电迹线。
根据一个实施例,所述至少一个IC包括衬底、以及由所述衬底承载并且分别耦接至所述多条键合接线的多个键合焊盘。
根据一个实施例,进一步包括在所述多个臂的多个对应的远端与所述电路板之间的粘合层。
通过本实用新型的半导体器件,能够避免封装工艺中某些材料的热膨胀系数不匹配而造成的断裂并以有利的方式进行封装。
附图说明
图1是根据本披露的半导体器件的示意性侧视图。
图2A至图2H是一种用于制作图1的半导体器件的方法中的各步骤的示意性侧视图。
图3是来自图2D的步骤的示意性俯视平面图。
具体实施方式
现在将在下文中参照附图更全面描述本披露,其中附图示出了本实用新型的若干实施例。然而本披露可以以许多不同的形式来实施,并且不应当被解释为限于在此所陈述的实施例。相反,提供这些实施例以使得本披露将是全面和完整的,并且将向本领域技术人员完全传达本披露的范围。贯穿全文相同的附图标记是指相同的元件。
现在首先参照图1,此时描述了根据本披露的半导体器件10。半导体器件10包括在其中具有开口26(图2A至图2C)的电路板11。开口26说明性地是矩形形状的并且被居中放置,但是在其他实施例中可能具有偏移。并且,在其他实施例中,开口26可以具有其他形状(例如,具有被倒圆的边缘的形状)。电路板11说明性地包括电介质层18、以及由该电介质层承载的多条导电迹线19a-19b。该多条导电迹线19a-19b可以限定多个接触焊盘用于耦接至外部电路。该多条导电迹线19a-19b可以包括例如铜和铝中的一者或多者。电介质层18可以包括例如有机层压材料、或液晶聚合物。
半导体器件10包括框架12,该框架包括在开口26中的IC裸片焊盘20、以及从该IC裸片焊盘向外延伸出来并且耦接至电路板11的多个臂21a-21b。在所展示的实施例中,IC裸片焊盘20相对于该多个臂21a-21b被下移设置。在一些实施例中,框架12可以包括金属材料(如铝和铜中的一者或多者),但可以包括具有足够刚度和导热性的任何材料。IC裸片焊盘20说明性地是矩形形状的,并且每个臂21a-21b在对角线方向上从该矩形形状的IC裸片焊盘的对应的角向外延伸。在其他实施例中,IC裸片焊盘20可以采用其他形状。
半导体器件10说明性地包括被安装在IC裸片焊盘20上的IC13。例如,该IC 13可以包括大功率IC,如处理单元。在其他实施例中,可以安装不只一个IC 13。IC 13说明性地包括衬底(例如,硅)27、以及由该衬底承载的多个键合焊盘28a-28b(例如,铜和铝中的一者或多者)。
半导体器件10说明性地包括将IC 13的多个键合焊盘28a-28b中的对应的键合焊盘与电路板11的多条导电迹线19a-19b中的对应的导电迹线相耦接的多条键合接线(例如,铜、银、金和铝中的一者或多者)15a-15b。半导体器件10说明性地包括包围IC 13、该多条键合接线15a-15b以及该多个臂21a-21b的包封材料(例如,电介质树脂)17。
在所展示的实施例中,IC裸片焊盘20具有第一和第二相反表面。该第一相反表面与IC 13相邻,并且该第二相反表面通过电路板11中的开口16而外露。并且,IC裸片焊盘20和电路板11具有多个相邻对齐的底部表面25a-25b。换言之,IC裸片焊盘20和电路板11具有共面的底部表面25a-25b,由此提供有利的低剖面。在其他实施例中,IC裸片焊盘20和电路板11可以具有竖直偏移的底部表面25a-25b。
此外,半导体器件10说明性地包括在该多个壁21a-21b的多个对应的远端与电路板11之间的粘合层(例如,非导电粘合剂)16a-16b。包封材料17说明性地包围电路板11、粘合层16a-16b、以及框架12的多条周边边缘24a-24c,由此为这些周边边缘提供有利的机械保护。在其他实施例中,包封材料17可以交替地停留在电路板11、粘合层16a-16b、和框架12的多条周边边缘24a-24c处。半导体器件10说明性地包括在IC 13与IC裸片焊盘20之间的粘合层(例如,非导电粘合剂)14。
在所展示的实施例中,该多个臂21a-21b侧向地并且平行于电路板11的相对的主平面地延伸。在其他实施例中,该多个臂21a-21b可以与电路板11的这些相对的主平面成角度地延伸。并且,该多个臂21a-21b与电路板11的相邻表面竖直地间隔开。与非导电粘合层16a-16b相结合的这个竖直间距使框架12与电有源部件电隔离开来,即,该框架是非有源部件。并且,在这些实施例中,该多条导电迹线19a-19b可以延伸并且在该多个臂21a-21b下面交叉通过从而提供扇出安排。在其他实施例中,该多个臂21a-21b直接沿着电路板11的表面延伸,限制了该多条导电迹线19a-19b的扇出图案。并且,在其他实施例中,框架12可以是电有源的并且可以用作例如地线。
有利地,半导体器件10可以提供对现有技术中的一些问题的方案。在使用有机层压电路板的现有技术方案中,载体带在制造过程中可能翘曲。而且,如果暴露于过多热量下,成品封装器件也发生翘曲。并且,最终器件的散热性能不尽人意。另一方面,在使用引线框提供连接的现有技术方案中,触点的扇出设计的密度不足。换言之,在一些应用中,引线框方案不能提供足够的输入输出触点。
半导体器件10提供了对这些现有技术问题的方案。具体地,半导体器件10用电路板方法的扇出密度对引线框方案的刚性和散热性能施加影响。由于IC 13与多个触点一起被封装在电路板11中,该多条导电迹线19a-19b容易被布线从而提供大量输入输出触点。
而且,半导体器件10包括框架12,该框架经由IC裸片焊盘20的外露大表面(即,用作各种各样的散热片)有效地将热能传递到外面。事实上,由于IC 13位于这个散热片上,散热性能非常好。并且,框架12在制造和应用用途过程中在这个封装体中保持刚度而不使用现有技术方法的加强件。
另一个方面涉及一种用于制作半导体器件10的方法。该方法包括:形成在其中具有开口26的电路板11。该方法还包括:对框架12进行定位,该框架包括在开口26中的IC裸片焊盘20、以及从该IC裸片焊盘向外延伸并且耦接至电路板11的多个臂21a-21b。该方法包括:将至少一个IC 13定位在IC裸片焊盘20上,形成将电路板11与该至少一个IC相耦接的多条键合接线15a-15b,并且形成包围该至少一个IC、该多条键合接线以及该多个臂21a-21b包围的包封材料17。
现在另外参照图2A至图2H和图3,此时更加详细地描述了用于制作半导体器件10的方法。在以下附图中,尽管同时制造了两个半导体器件10a-10b,但应认识到的是,可以并行制造任意数量的半导体器件10(例如,一次制造几百个)。
在图2A和图2B中,电路板11安装到粘合剂载体层22上。在图2C中,粘合层16a-16b形成在电路板11上用于接收框架12。
在图2D和图3中,框架12安装到电路板上。每个框架12a-12b说明性地包括四个臂21aa-21db,但在其他实施例中可以包括更多或更少臂。例如,在一些实施例中,框架12a-12b可以包括六个臂以提供甚至更大的刚性和散热。每个臂21aa-21db说明性地是矩形形状的,但在其他实施例中可以具有锥形(即,三角形或梯形臂),即,随着臂延伸远离IC裸片焊盘20,宽度变薄。
在图2E中,粘合层14形成在IC裸片焊盘20上,而IC 13安装到该IC裸片焊盘上。在图2F中,该多条键合接线15a-15b形成在多条导电迹线19a-19b与多个IC 13的多个键合焊盘28a-28b之间。
在图2G中,包封材料17形成在电路板11和IC 13之上。一旦完成包封,就去除粘合剂载体层22。在图2H中,用切割刀片23将半导体器件10a-10b的载体条带切割分离。
得益于在前述说明书和相关联附图中呈现的教导,本领域技术人员将想到本披露的许多修改和其他实施例。因此,应该理解的是,本实用新型实施例并不限于所披露的特定实施例,并且修改和实施例旨在包括于所附权利要求书的范围内。
Claims (15)
1.一种半导体器件,其特征在于,包括:
电路板,所述电路板在其中具有开口;
框架,所述框架包括在所述开口中的集成电路IC裸片焊盘、以及从所述IC裸片焊盘向外延伸并且耦接至所述电路板的多个臂;
安装在所述IC裸片焊盘上的至少一个IC;
多条键合接线,所述多条键合接线将所述电路板与所述至少一个IC耦接;以及
包封材料,所述包封材料包围所述至少一个IC、所述多条键合接线、以及所述多个臂。
2.如权利要求1所述的半导体器件,其特征在于,所述IC裸片焊盘具有第一和第二相反表面,所述第一相反表面与所述至少一个IC相邻,所述第二相反表面通过所述电路板的所述开口而外露。
3.如权利要求1所述的半导体器件,其特征在于,所述IC裸片焊盘是矩形形状的;并且其中,每个臂在对角线方向上从所述矩形形状的IC裸片焊盘的对应角向外延伸。
4.如权利要求1所述的半导体器件,其特征在于,所述IC裸片焊盘和所述电路板具有多个相邻对齐的底部表面。
5.如权利要求1所述的半导体器件,其特征在于,所述电路板包括电介质层、以及由所述电介质层承载并且分别耦接至所述多条键合接线的多条导电迹线。
6.如权利要求1所述的半导体器件,其特征在于,所述至少一个IC包括衬底、以及由所述衬底承载并且分别耦接至所述多条键合接线的多个键合焊盘。
7.如权利要求1所述的半导体器件,其特征在于,进一步包括在所述多个臂的多个对应的远端与所述电路板之间的粘合层。
8.如权利要求1所述的半导体器件,其特征在于,进一步包括在所述至少一个IC与所述IC裸片焊盘之间的粘合层。
9.如权利要求1所述的半导体器件,其特征在于,所述框架包括金属材料。
10.如权利要求1所述的半导体器件,其特征在于,所述包封材料包围所述电路板和所述框架的多条周边边缘。
11.一种半导体器件,其特征在于,包括:
电路板,所述电路板在其中具有开口;
框架,所述框架包括在所述开口中的矩形形状的集成电路IC裸片焊盘、以及在对角线方向上从所述矩形形状的IC裸片焊盘的多个对应的角向外延伸并且耦接至所述电路板的多个臂;
安装在所述矩形形状的IC裸片焊盘上的至少一个IC;
所述矩形形状的IC裸片焊盘具有第一和第二相反表面,所述第一相反表面与所述至少一个IC相邻,所述第二相反表面通过所述电路板的所述开口而外露;
多条键合接线,所述多条键合接线将所述电路板与所述至少一个IC耦接;以及
包封材料,所述包封材料包围所述至少一个IC、所述多条键合接线、以及所述多个臂。
12.如权利要求11所述的半导体器件,其特征在于,所述矩形形状的IC裸片焊盘和所述电路板具有多个相邻对齐的底部表面。
13.如权利要求11所述的半导体器件,其特征在于,所述电路板包括电介质层、以及由所述电介质层承载并且分别耦接至所述多条键合接线的多条导电迹线。
14.如权利要求11所述的半导体器件,其特征在于,所述至少一个IC包括衬底、以及由所述衬底承载并且分别耦接至所述多条键合接线的多个键合焊盘。
15.如权利要求11所述的半导体器件,其特征在于,进一步包括在所述多个臂的多个对应的远端与所述电路板之间的粘合层。
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