CN104517833A - 一种肖特基势垒二极管的制造方法 - Google Patents
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- 230000004888 barrier function Effects 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 86
- 229910052751 metal Inorganic materials 0.000 claims abstract description 86
- 238000001704 evaporation Methods 0.000 claims abstract description 19
- 230000008020 evaporation Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 34
- 150000002739 metals Chemical class 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000002360 preparation method Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 4
- 238000010025 steaming Methods 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 2
- 238000010549 co-Evaporation Methods 0.000 abstract 2
- 229920001296 polysiloxane Polymers 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 10
- 238000005036 potential barrier Methods 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
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- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000004821 distillation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 235000016768 molybdenum Nutrition 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
本发明为一种肖特基势垒二极管的制造方法,其特征在于:在硅外延片1上形成肖特基势垒的过程中,采用至少两种金属共蒸掺杂的方法形成,该金属掺杂层4的厚度为10-50nm,掺杂金属和上部电极金属5在共蒸的过程中,通过控制蒸发速率,实现掺杂比例0-100%可调。本发明一方面可以通过一次蒸发工艺实现肖特基二极管金属势垒以及上部金属电极的制备,另一方面可以通过控制金属掺杂层的厚度以及掺杂金属的比例实现肖特基势垒高度的调制。
Description
技术领域
本发明涉及一种半导体分立器件的制造方法,尤其是一种采用掺杂金属作为肖特基(Schottky) 势垒金属的二极管的制造方法。
背景技术
肖特基势垒二极管(Schottky Barrier Diode)的简称是SBD,是利用金属与半导体之间接触势垒进行工作的一种多数载流子器件。由于这种二极管与普通的P-N 结构型二极管相比,具有正向压降小、速度快等特点,因此在现代通讯、超高速器件,微波电路以及高速集成电路中具有广泛用途。
对于肖特基二极管来说,影响功耗最重要的两个参数是正向压降VF和反向漏电流IR。对于硅外延工艺的肖特基二极管,正向压降VF取决于使用的势垒合金层、外延条件(外延层厚度及电阻率)、以及有源区域面积。对于特定规格的肖特基二极管来说外延条件的优化空间较为有限,而通过增大有源区面积来降低正向压降VF与器件小型化要求相冲突,并且还会提高二极管电容,从而增大电路损耗。同时还要考虑当正向电压降低是,反向漏电流会变大。
因此在肖特基二极管的制造中,选择适当的势垒合金层变得尤为重要,金属功函数是影响金属硅化物势垒高度的主要因素制约,通过选择金属功函数比较低的金属,比较常用的有铬(Cr),镍(Ni),铂(Pt),钼(Mo)等,这些金属的硅化物被广泛应用于制作肖特基二极管的势垒合金层,以减小肖特基二极管的正向压降VF。为了减少肖特基二极管的正向功耗,通常希望势垒金属层厚度越薄越好,然而矛盾的是,势垒金属层过薄之后,由于上部电极以及硅外延片的相互扩散,又会导致金属势垒的可靠性下降,而一旦金属势垒层加厚,必然导致反向漏电IR的增加,导致电能损耗上升。目前比较普遍的做法是蒸发或者溅射势垒金属层以后,先做一步合金工艺,使势垒金属和硅形成了金属硅化物势垒,然后通过金属腐蚀,将多余的势垒金属扒掉,这样确保获得稳定的一致性好的肖特基势垒。此方法的问题是势垒金属和上电极金属不是通过一次蒸发工艺完成,导致生产周期加长,另外势垒金属去除过程多采用酸的湿法腐蚀工艺,工艺可控性较差,影响了参数的一致性。
同时,在肖特基二极管的实际应用中,针对不同的应用领域,一些电路设计希望肖特基二极管的VF值尽量降低,而有一些电路设计更关注肖特基二极管的漏电流IR特性,而可以允许适当牺牲一点VF的性能。这就使得如果在制造过程中,通过工艺上的控制实现肖特基势垒高度的调制变得非常有意义,该课题也已经成为当今研究的热点。目前比较普遍的方式是采取叠层势垒金属的方式,比如Si/薄层金属A/薄层金属B/上电极金属类似的结构,其中金属A和金属B是不同的势垒金属,如铬(Cr)/镍(Ni)、镍(Ni)/铒(Er)等,再通过不同的合金工艺来实现肖特基势垒高度的调制。此叠层金属方法容易导致下层金属会变成上层金属的阻挡层,进而影响上层金属和硅之间金属硅化合物的形成,使得势垒高度调制效果变差。
发明内容
本发明为一种肖特基势垒二极管的制造方法,其特征在于:在硅外延片上形成肖特基势垒的过程中,采用至少两种金属共蒸掺杂的方法形成,该金属掺杂层的厚度为10-50nm,掺杂金属和上部电极金属在共蒸的过程中,通过控制蒸发速率,实现掺杂比例0-100%可调。
进一步的,所述至少两种金属共蒸掺杂的方法,是在多源电子束蒸发系统内进行的,且各金属蒸发源速率可控。
进一步的,所述金属共蒸掺杂层是由掺杂金属和上部电极金属共同构成。
进一步的,所述金属掺杂层的掺杂金属比例,通过控制掺杂金属和上部电极金属的蒸发速率来实现0-100%可调。
进一步的,所述金属掺杂层的厚度为10-50nm连续可调;
进一步的,所述金属掺杂层厚度达到设定值之后,停止掺杂金属的蒸发,继续蒸发上部电极金属,完成上部金属电极的制备。
本发明的优点和积极效果是:一方面可以通过一次蒸发工艺实现肖特基二极管金属势垒以及金属上电极的制备,另一方面可以通过控制金属掺杂层的厚度以及掺杂金属的比例实现肖特基势垒高度的调制,本发明对简化肖特基二极管制造流程,提高参数可控性和一致性都有着非常积极的意义。
附图说明
图1 肖特基二极管势垒金属蒸发前的结构示意图。
图2 肖特基二极管中心位置局部放大截面图。
图3肖特基二极管芯片结构示意图。其中,1是硅外延衬底片,2是氧化层,3是P型扩散环,也称保护环,4是金属掺杂层,5是上部金属电极,6是背面金属电极。
具体实施方式
本发明专利的具体实施方式为:
基于标准的SBD制备工艺,首先在Si外延衬底1上面生长氧化层2,然后通过光刻和注入以及推结工艺形成P型扩散环3,然后进行势垒区光刻,光刻后芯片结构示意图如图1所示。
势垒金属是通过至少两种金属共蒸掺杂的方式形成,其结构示意图如图2所示。具体为,在多源电子束蒸发系统内,掺杂金属和上部电极金属作为各自独立的蒸发源,其加热状态、蒸发速率均为可控,共蒸形成金属掺杂层4,掺杂金属的掺杂比例是通过体积半分比计算得出的,以两种金属为例,假设掺杂金属A的蒸发速率为α nm/s,上部电极金属B的蒸发速率为β nm/s,则金属掺杂层中掺杂金属所占体积百分比为:
α/(α+β)×100%
从上面公式我们可以看出,通过调整α和β的值,即通过蒸发速率的控制,可以实现掺杂金属的掺杂比例0-100%可调。
通过多源电子束蒸发系统内的膜厚控制系统,实现金属掺杂层厚度10-50nm的连续可控,具体厚度是根据不同产品、不同工艺要求确定。在金属掺杂层达到工艺规定的厚度后,停止掺杂金属的蒸发,继续蒸发上部电极金属5,完成肖特基二极管上部电极的制备。
通过合金工艺,使金属掺杂层和硅衬底之间形成金属硅化合物,构成肖特基势垒。
接下来的工艺和标准的SBD制备工艺相同,即正面金属光刻、背面减薄、背面多层金属V/Ni/Ag蒸发,形成背面金属电极6,最后是测试划片。整个肖特基二极管芯片结构示意图如图1所示。
Claims (6)
1. 一种肖特基势垒二极管的制造方法,其特征在于:在硅外延片上形成肖特基势垒的过程中,采用至少两种金属共蒸掺杂的方法形成,该金属掺杂层的厚度为10-50nm,掺杂金属和上部电极金属在共蒸的过程中,通过控制蒸发速率,实现掺杂比例0-100%可调。
2.根据权利要求1所述肖特基势垒二极管的制造方法,其特征在于所述至少两种金属共蒸掺杂的方法,是在多源电子束蒸发系统内进行的,且各金属蒸发源速率可控。
3.根据权利要求1所述肖特基势垒二极管的制造方法,其特征在于所述金属共蒸掺杂层是由掺杂金属和上部电极金属共同构成。
4.根据权利要求1所述肖特基势垒二极管的制造方法,其特征在于所述金属掺杂层的掺杂金属比例,通过控制掺杂金属和上部电极金属的蒸发速率来实现0-100%可调。
5.根据权利要求1所述肖特基势垒二极管的制造方法,其特征在于金属掺杂层的厚度为10-50nm连续可调。
6.根据权利要求1所述肖特基势垒二极管的制造方法,其特征在于在金属掺杂层厚度达到设定值之后,停止掺杂金属的蒸发,继续蒸发上部电极金属,完成上部金属电极的制备。
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CN111834467A (zh) * | 2019-04-22 | 2020-10-27 | 复旦大学 | 一种与Si工艺兼容的NixSiy/Ga2O3肖特基二极管及其制备方法 |
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