CN104332399A - 半导体器件制造方法 - Google Patents
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
本发明公开了一种半导体器件制造方法,包括:在衬底上形成半导体器件;在半导体器件上形成保护层,保护层材质为具有张应力的氮化硅;对半导体器件执行退火;采用HF基腐蚀液湿法去除保护层。依照本发明的半导体器件制造方法,通过采用HF湿法腐蚀张应力氮化硅材质的保护层,能避免栅极侧墙和/或硬掩模层的氮化硅受到侵蚀,有效提高器件性能以及可靠性。
Description
技术领域
本发明涉及一种半导体器件制造方法,特别是涉及一种采用张应力氮化硅作为保护层以提高器件可靠性的方法。
背景技术
在90nm节点后,各种新技术逐渐被采用以提高器件的性能。其中之一是应力技术,例如采用外延生长的SiGe、SiC等高应力材质作为源漏区,或者在源漏区上形成氮化硅或者类金刚石无定形碳(DLC)材质的应力衬层(liner),用于提高沟道区载流子迁移率从而提高器件的驱动性能。
上述集成了外延硅锗的器件源漏区可以通过原位掺杂或者离子注入的方式进行掺杂。如果通过注入形成源漏区,在后续的退火过程中为了避免锗元素的污染退火炉,通常在注入完成后在整个硅片上沉积一层保护层,退火完毕后进行硅化工艺(silicide)模块时再将这层保护层去掉。目前通常用的保护层为氮化硅(通过热磷酸去除)或者氧化硅(通过氢氟酸去除)。
然而,在去除保护层的时候为保证保护层被完全去除需要加一定的过漂,这时暴露在外面的侧墙以及硬掩模(hardmask)(通常为无应力氮化硅或者氧化硅)将会被部分腐蚀,从而对器件结构造成破坏,降低了器件的性能以及可靠性。
发明内容
由上所述,本发明的目的在于克服上述技术困难,提出一种创新性半导体制造方法,通过采用HF湿法腐蚀张应力氮化硅材质的保护层,能避免栅极侧墙和/或硬掩模层的氮化硅受到侵蚀,有效提高器件性能以及可靠性。
为此,本发明提供了一种半导体器件制造方法,包括:在衬底上形成半导体器件;在半导体器件上形成保护层,保护层材质为具有张应力的氮化硅;对半导体器件执行退火;采用HF基腐蚀液湿法去除保护层。
其中,半导体器件中包括掺杂区,并且半导体器件选自以下器件之一及其组合:MOSFET、双极晶体管、DMOS、UMOS、FinFET、BiMOS、二极管、发光器件、电阻、电容、电感、接触互连、层间互连。
其中,退火用于以下用途之一及其组合:用于激活源漏掺杂、用于使得非晶体结构转变为多晶或者单晶结构、用于形成金属硅化物、用于驱使掺杂剂形成凝结区、用于降低表面缺陷。
其中,保护层厚度为
其中,湿法腐蚀的时间为1~100s。
其中,HF基腐蚀液为dHF、或dBOE。
其中,半导体器件为MOSFET,在衬底上形成MOSFET的步骤进一步包括:在衬底上形成栅极堆叠和栅极侧墙;以栅极堆叠为掩模,刻蚀衬底形成源漏沟槽;在源漏沟槽中外延生长源漏应力层;以栅极堆叠为掩模,执行轻掺杂注入,形成LDD结构和/或Halo结构;执行重掺杂,形成源漏区。
其中,栅极堆叠的顶部和/或栅极侧墙的材料选自以下之一及其组合:氧化硅、无应力氮化硅、压应力氮化硅。
其中,去除保护层之后进一步包括步骤:形成层间介质层;刻蚀层间介质层,形成暴露源漏区的接触孔;在接触孔中形成金属硅化物;在接触孔中金属硅化物上形成接触塞。
其中,栅极堆叠为假栅极堆叠,在形成层间介质层之后进一步包括:去除假栅极堆叠,在层间介质层中留下栅极沟槽;在栅极沟槽中形成MG/HK结构的最终栅极堆叠。
依照本发明的半导体器件制造方法,通过采用HF湿法腐蚀张应力氮化硅材质的保护层,能避免栅极侧墙和/或硬掩模层的氮化硅受到侵蚀,有效提高器件性能以及可靠性。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1至图4为依照本发明的制造方法各步骤的剖面示意图;以及
图5为依照本发明的器件制造方法的示意性流程图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了有效提高了器件性能以及可靠性的半导体器件制造方法。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
如图1所示,在衬底上形成基础的半导体器件结构,例如形成MOSFET。然而值得注意的是,以下的MOSFET制造流程仅描述了本发明的一个优选实施例,本发明也可用于MOSFET之外的其他实施例。例如,在衬底中形成其他器件结构,例如双极晶体管、DMOS、UMOS、FinFET、BiMOS、二极管、发光器件(例如LED、LCD、OLED等)、电阻、电容、电感、接触互连、层间互连等,也即只要对衬底执行了掺杂形成掺杂区,则可以在整个晶片上沉积本发明的张应力氮化硅材质的保护层,以提高在HF基腐蚀液下相对于氧化硅、无应力氮化硅、压应力氮化硅的衬底上其他(栅极/侧墙/硬掩模)结构的刻蚀选择性,保护这些结构不受过度腐蚀,从而有效提高器件性能以及可靠性。
具体地,首先提供衬底1,衬底1依照器件用途需要而合理选择,可包括单晶体硅(Si)、单晶体锗(Ge)、应变硅(Strained Si)、锗硅(SiGe),或是化合物半导体材料,例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)、锑化铟(InSb),以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑,衬底1优选地为体Si。
优选地,在衬底1中形成浅沟槽隔离(STI)2。例如通过等离子体干法刻蚀、反应离子刻蚀(RIE)或者四甲基氢氧化铵(TMAH)湿法腐蚀硅基衬底1,在衬底1中形成多个浅沟槽(未示出),然后通过LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD等常用工艺在浅沟槽中沉积氧化硅、氮氧化硅等绝缘材质形成STI2。进一步地,优选利用掩模分别对衬底1由STI2包围出的有源区进行衬底掺杂注入,形成p-的NMOS衬底阱区或者n-的PMOS衬底阱区(均未示出)。
随后,在有源区中衬底上形成栅极堆叠3。通过LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等工艺依次沉积形成栅极介质3A、栅极材料层3B以及优选地栅极盖层3C(或者为硬掩模层3C)。在本发明一个实施例中,器件采用后栅工艺形成,因此栅极堆叠3是假栅极堆叠,假栅极介质层3A是氧化硅,假栅极材料层3B是多晶硅、非晶硅、非晶锗、非晶碳等材料,假栅极盖层3C是氮化硅。在本发明另一实施例中,采用前栅工艺形成器件,因此栅极堆叠3保留到最后,栅极介质层3A是氧化硅、氮氧化硅、高k材料,其中高k材料包括但不限于包括选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料(其中,各材料依照多元金属组分配比以及化学价不同,氧原子含量x可合理调整,例如可为1~6且不限于整数),或是包括选自ZrO2、La2O3、LaAlO3、TiO2、Y2O3的稀土基高K介质材料,或是包括Al2O3,以其上述材料的复合层;栅极材料层3B则可为多晶硅、多晶锗硅、或金属,其中金属可包括Co、Ni、Cu、Al、Pd、Pt、Ru、Re、Mo、Ta、Ti、Hf、Zr、W、Ir、Eu、Nd、Er、La等金属单质、或这些金属的合金以及这些金属的氮化物,栅极导电层3B中还可掺杂有C、F、N、O、B、P、As等元素以调节功函数。优选地,栅极导电层3B与栅极绝缘层3A之间还优选通过PVD、CVD、ALD等常规方法形成氮化物的阻挡层(未示出),阻挡层材质为MxNy、MxSiyNz、MxAlyNz、MaAlxSiyNz,其中M为Ta、Ti、Hf、Zr、Mo、W或其它元素。栅极盖层3C仍然可以是氮化硅。随后,采用干法工艺刻蚀上述各个栅极堆叠材料层3A~3C以形成栅极堆叠3。
优选地,如图1所示,在有源区衬底中形成了应力源漏区1SS、1SD。利用栅极堆叠3为掩模,刻蚀衬底1形成源漏沟槽,在源漏沟槽中通过PECVD、MBE、ALD、MOCVD等工艺外延形成应力源漏区1SS、1SD,其材质不同于衬底1的Si,而是可以包括更高应力的SiGe、Si:C、Si:H、SiSn、GeSn、SiGe:C等及其组合。如图1所示,源漏沟槽以及随后外延形成的应力源漏区具有矩形垂直侧壁之外其他复杂的剖面形态,例如为梯形、倒梯形、Σ型等,优选地具有朝向沟道区突出的部分以增强沟道区应力。
优选地,以栅极堆叠3为掩模,对衬底进行轻掺杂,形成了轻掺杂源漏结构(LDD)或者晕状掺杂结构(halo)。例如分别衬底1中有源区垂直注入不同的掺杂离子形成轻掺杂的源漏区1LD/1LS,对有源区倾斜注入不同的掺杂离子以形成halo结构(图中虚线椭圆框所示,未采用附图标记)。
随后,在栅极堆叠3两侧的源漏区上形成栅极侧墙4。采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常用工艺沉积形成侧墙材料层,随后通过刻蚀去除部分侧墙材料层,仅在栅极堆叠3两侧保留而形成栅极侧墙4。在本发明一个优选实施例中,栅极侧墙4如图1所示包括多个叠层,分别是氮化硅、非晶碳(优选ALD工艺)的第一侧墙4A(具有垂直形貌),氧化硅(优选PECVD、HDPCVD或者热氧化、化学氧化)的第二侧墙4B(具有L型结构,也即具有平行于第一侧墙4A的垂直的第一部分4B1,以及平行于衬底1表面的水平的第二部分4B2),以及氮化硅(无应力或者压应力)或者DLC材质(优选PECVD或者磁控溅射工艺,以进一步提高栅极侧墙对沟道区的应力,从而增强沟道区载流子迁移率)的第三侧墙4C(第三侧墙4C位于第二侧墙4B的水平的第二部分4B2之上,具有略微倾斜的侧面形貌)。在本发明其他实施例中,栅极侧墙4可以为单一材料,例如氮化硅或者DLC,可以具有压应力或者不具有应力。
以栅极侧墙4为掩模,对MOSFET的源漏区进行重掺杂,分别形成了掺杂浓度较高、结深较厚的重掺杂漏区1HD、重掺杂源区1HS。掺杂工艺可以是执行垂直离子注入,也可以是在外延形成应力源漏区1SS、1SD同时进行原位掺杂。以上各处的掺杂剂可以包括N、C、F、P、Cl、As、B、In、Sb、Ga、Si、Ge等及其组合。
值得注意的是,与以往注入形成源漏区之后立即进行退火激活掺杂剂不同,在本发明技术方案中,注入形成源漏区,在后续的退火过程中为了避免锗、碳等非Si元素的污染退火炉,通常在注入完成后在整个硅片上沉积一层保护层,退火完毕后进行silicide模块时再将这层保护层去掉。因此增添采用如图2所示的保护层5。在本发明其他实施例中,保护层5同样用于避免锗、碳、其他金属等非Si元素的污染退火炉。
如图2所示,在器件上形成保护层5。例如,保护层5覆盖了STI2、源漏区以及栅极堆叠3和栅极侧墙4。形成工艺例如是PECVD、磁控溅射、MBE、ALD等,保护层5材质例如是氮化硅。优选地,通过控制工艺参数,使得保护层5具有张应力,大小例如400MPa~4GPa并优选1~2GPa。保护层5的厚度依照源漏区中掺杂的非Si元素的浓度以及深度而选定,例如优选为
表1
如以上表1所示,常规张应力氮化硅在dHF中的腐蚀速率比较快,远大于热氧以及TEOS(以TEOS为原料而CVD制备的氧化硅基材料,以下简称TEOS)、压应力氮化硅的腐蚀速率。这为后续采用HF基腐蚀液去除保护层提供了良好的选择性。
如图3所示,执行退火。在MOSFET的示例中,退火以激活源漏区中的掺杂剂。例如在500~1200摄氏度下热处理1ms~10min(火炉退火、尖峰退火、快速退火RTA等常用工艺,工艺参数依照掺杂剂浓度和结深所需设定),使得源漏区中注入或者原位掺杂的掺杂剂激活,使得源漏区具有与衬底有源区不同的掺杂类型和浓度。然而,在其他半导体器件的示例中,退火可以用于使得非晶体结构转变为多晶或者单晶结构、可以用于形成金属硅化物、可以用于驱使掺杂剂形成凝结区、可以降低表面缺陷等等。
如图4所示,采用HF基腐蚀液湿法去除张应力氮化硅材质的保护层5。湿法腐蚀液可以包括稀释氢氟酸dHF,稀释的缓释刻蚀液dBOE(BOE,NH4F与HF的混合溶液,两者体积比例如2:1~1:4)。腐蚀温度例如18~35摄氏度,并优选23摄氏度。腐蚀时间例如1s~100s,优选为20~40s。如上述表1所示,由于HF腐蚀液对于张应力氮化硅的腐蚀速度远大于氧化硅或者压应力氮化硅,因此通过控制腐蚀时间,可以使得保护层5完全被腐蚀,而同时栅极侧墙4、硬掩模3C等基本不受腐蚀或者轻微腐蚀,避免了对栅极结构造成损伤,降低了工艺集成的难度。
此后,采用常规工艺,完成器件制造。
例如,在整个器件上形成低k材料的层间介质层(ILD),采用CMP、回刻等工艺平坦化ILD直至暴露栅极堆叠3。在后栅工艺中,去除假栅极堆叠3,在ILD中留下栅极沟槽,并在栅极沟槽中沉积形成最终的MG/HK结构(栅极绝缘层为高k材料,栅极导电层为金属)的栅极堆叠。刻蚀ILD直至暴露源漏区,形成接触孔。优选地,在接触孔中形成金属硅化物以降低接触电阻。随后通过MOCVD、MBE、ALD、蒸发、溅射等工艺,在接触孔中金属硅化物上形成了接触金属层,形成了最终的接触塞(plug)。
值得注意的是,以上参照MOSFET制造流程描述了本发明的一个优选实施例,然而本发明也可用于MOSFET之外的其他实施例。例如,在衬底中形成其他器件结构,例如双极晶体管、DMOS、UMOS、FinFET、BiMOS等,也即只要对衬底执行了掺杂形成掺杂区,则可以在整个晶片上沉积本发明的张应力氮化硅材质的保护层5,以提高在HF基腐蚀液下相对于氧化硅、无应力氮化硅、压应力氮化硅的衬底上栅极/侧墙/硬掩模结构的刻蚀选择性,保护这些结构不受过度腐蚀,从而有效提高器件性能以及可靠性。
依照本发明的半导体器件制造方法,通过采用HF湿法腐蚀张应力氮化硅材质的保护层,能避免栅极侧墙和/或硬掩模层的氮化硅受到侵蚀,有效提高器件性能以及可靠性。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (10)
1.一种半导体器件制造方法,包括:
在衬底上形成半导体器件;
在半导体器件上形成保护层,保护层材质为具有张应力的氮化硅;
对半导体器件执行退火;
采用HF基腐蚀液,湿法腐蚀去除保护层。
2.如权利要求1的半导体器件制造方法,其中,半导体器件中包括掺杂区,并且半导体器件选自以下器件之一及其组合:MOSFET、双极晶体管、DMOS、UMOS、FinFET、BiMOS、二极管、发光器件、电阻、电容、电感、接触互连、层间互连。
3.如权利要求1的半导体器件制造方法,其中,退火用于以下用途之一及其组合:用于激活源漏掺杂、用于使得非晶体结构转变为多晶或者单晶结构、用于形成金属硅化物、用于驱使掺杂剂形成凝结区、用于降低表面缺陷。
4.如权利要求1的半导体器件制造方法,其中,保护层厚度为1~
5.如权利要求1的半导体器件制造方法,其中,湿法腐蚀的时间为1~100s。
6.如权利要求1的半导体器件制造方法,其中,HF基腐蚀液为dHF、或dBOE。
7.如权利要求1的半导体器件制造方法,其中,半导体器件为MOSFET,在衬底上形成MOSFET的步骤进一步包括:在衬底上形成栅极堆叠和栅极侧墙;以栅极堆叠为掩模,刻蚀衬底形成源漏沟槽;在源漏沟槽中外延生长源漏应力层;以栅极堆叠为掩模,执行轻掺杂注入,形成LDD结构和/或Halo结构;执行重掺杂,形成源漏区。
8.如权利要求7的半导体器件制造方法,其中,栅极堆叠的顶部和/或栅极侧墙的材料选自以下之一及其组合:氧化硅、无应力氮化硅、压应力氮化硅。
9.如权利要求7的半导体器件制造方法,其中,去除保护层之后进一步包括步骤:形成层间介质层;刻蚀层间介质层,形成暴露源漏区的接触孔;在接触孔中形成金属硅化物;在接触孔中金属硅化物上形成接触塞。
10.如权利要求9的半导体器件制造方法,其中,栅极堆叠为假栅极堆叠,在形成层间介质层之后进一步包括:
去除假栅极堆叠,在层间介质层中留下栅极沟槽;
在栅极沟槽中形成MG/HK结构的最终栅极堆叠。
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CN110797309B (zh) * | 2018-08-01 | 2021-04-02 | 旺宏电子股份有限公司 | 半导体基板与半导体装置 |
CN112349586A (zh) * | 2019-08-09 | 2021-02-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构的形成方法 |
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