CN104241388A - 一种带三角槽的soi-ldmos高压功率器件 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000005684 electric field Effects 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 66
- 239000001301 oxygen Substances 0.000 claims description 66
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 63
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 238000009413 insulation Methods 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 230000000452 restraining effect Effects 0.000 claims description 5
- 239000000615 nonconductor Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- -1 oxonium ion Chemical class 0.000 claims description 3
- 150000002926 oxygen Chemical class 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
本发明公开了一种带三角槽的SOI-LDMOS高压功率器件。本发明针对现有技术SOI-LDMOS器件关断时,漏极电压将在埋氧层下方诱导出电子反型层,它会阻止等势线穿过埋氧层,导致击穿过早发生在硅层,纵向耐压难以提高的问题,公开了一种带三角槽的SOI-LDMOS高压功率器件。其主要是通过在漂移区下方的埋氧层上蚀刻出的三角形沟槽;这样在漂移区下方,就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷,这些电荷大大提高了器件纵向耐压。而且,器件漂移区厚度从源到漏线性增加,根据RESURF(降低表面电场)原理,横向电场因受到调制而变得均匀,有利于提高横向耐压和抑制比导通电阻的快速增加。
Description
技术领域
本发明属于高压功率器件领域,具体涉及一种带三角槽的SOI-LDMOS高压功率器件。
背景技术
目前,现有技术在SOI-LDMOS器件关断时,漏极电压将在埋氧层下方诱导出电子反型层,它会阻止等势线穿过埋氧层,导致击穿过早发生在硅层,纵向耐压难以提高的问题。因为横向耐压的提高可以通过增加漂移区长度、横向电场来实现,所以SOI-LDMOS器件耐压的提高主要受纵向耐压限制。从理论上来讲增加漂移区和埋氧层厚度可提高纵向耐压。但SiO2是热的不良导体,增加埋氧层厚度会使自热效应更加严重,而增加漂移区厚度会导致掺杂浓度降低,比导通电阻迅速增加,最后厚的漂移区和埋氧层也不利于与低压电路集成。如何提高SOI-LDMOS功率器件耐压,是它在高压功率器件,尤其是智能功率集成电路领域应用的关键。
发明内容
(一)要解决的技术问题
为解决上述问题,本发明提出了一种带三角槽的SOI-LDMOS高压功率器件。其主要是通过在漂移区下方的埋氧层上蚀刻出的三角形沟槽;这样在漂移区下方,就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷,这些电荷大大提高了器件纵向耐压。
(二)技术方案
一种带三角槽的SOI-LDMOS高压功率器件,其主要包括:衬底电极、纵向由下而上的P型衬底、漂移区、源电极、漏电极、栅电极、绝缘SiO2层(常称为埋氧层)和空穴层;其中所述的漂移区横向两端分别形成了n+源区和n+漏区,在n+源区的边上是p体区;所述的埋氧层上蚀刻出了一个三角形沟槽,如此在漂移区下方就存在一个埋氧层斜面,所述的空穴层就在这个埋氧层斜面上。
进一步的,所述的整个埋氧层均处于水平面,能与低压电路完全的集成在一起;因此,当此器件的埋氧层与常规器件的厚度一样时,他的等效厚度会比常规器件薄,就能有效缓解自热效应。
进一步的,所述的漂移区长度为30μm,埋氧层厚度为1μm,三角槽深度为0.5μm时,埋氧层电场被增强到7×106V/cm,耐压为353V。
进一步的,所述的埋氧层为绝缘SiO2层,SiO2是热的不良导体,增加埋氧层厚度会使自热效应更加严重,而增加漂移区厚度会导致掺杂浓度降低,比导通电阻迅速增加,最后厚的漂移区和埋氧层也不利于与低压电路集成,因此埋氧层和漂移区的厚度一定要薄。
进一步的,所述的埋氧层的三角形槽的形成方式是先在硅表面上注入氧离子,形成二氧化硅层,然后在其表面蚀刻出三角形槽,再着沉积多晶硅,最后与另一硅片键合并减薄。
进一步的,所述的埋氧层沟槽的三角形形状并不是唯一的,只要能使埋氧层表面倾斜都可以;埋氧层上下界面都可各蚀刻一个三角形沟槽。
进一步的,其特征是在漂移区和衬底之间的绝缘SiO2层(常称为埋氧层),如此,在漂移区下方就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷,这些电荷大力度的提高了器件的纵向耐压;而且,器件漂移区厚度从源到漏线性增加,根据RESURF(降低表面电场)原理,横向电场因受到调制而变得均匀,有利于提高横向耐压和抑制比导通电阻的快速增加。
(三)有益效果
本发明与现有技术相比较,其具有以下有益效果:本发明在漂移区下方的埋氧层上蚀刻出一个三角形沟槽。这样在漂移区下方,就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷。这些电荷大大提高了器件纵向耐压。而且,器件漂移区厚度从源到漏线性增加,根据RESURF(降低表面电场)原理,横向电场因受到调制而变得均匀,有利于提高横向耐压和抑制比导通电阻的快速增加。新器件埋氧层等效厚度比常规器件薄,能有效缓解自热效应。另外,器件的整个埋氧层处于水平,完全能与低压电路集成在一起。相比其他耐压结构,带三角槽的SOI-LDMOS高压功率器件实现工艺简单,更易商用化。
附图说明
图1是本发明的整体结构示意图。
图2是本发明击穿时的二维电势分布示意图。
图3是本发明的实现主要工艺流程示意图。
具体实施方式
如图1所示,一种带三角槽的SOI-LDMOS高压功率器件,其主要包括:衬底电极、纵向由下而上的P型衬底、漂移区、源电极、漏电极、栅电极、绝缘SiO2层(常称为埋氧层)和空穴层;其中所述的漂移区横向两端分别形成了n+源区和n+漏区,在n+源区的边上是p体区;所述的埋氧层上蚀刻出了一个三角形沟槽,如此在漂移区下方就存在一个埋氧层斜面,所述的空穴层就在这个埋氧层斜面上。
其中,所述的整个埋氧层均处于水平面,能与低压电路完全的集成在一起;因此,当此器件的埋氧层与常规器件的厚度一样时,他的等效厚度会比常规器件薄,就能有效缓解自热效应。
如图2所示,本发明在被击穿时,埋氧层中的等势线分布比较密,而且表面电场分布更加均匀。所述的漂移区长度为30μm,埋氧层厚度为1μm,三角槽深度为0.5μm时,埋氧层电场被增强到7×106V/cm,耐压为353V。
其中,所述的埋氧层为绝缘SiO2层,SiO2是热的不良导体,增加埋氧层厚度会使自热效应更加严重,而增加漂移区厚度会导致掺杂浓度降低,比导通电阻迅速增加,最后厚的漂移区和埋氧层也不利于与低压电路集成,因此埋氧层和漂移区的厚度一定要薄。
如图3所示,,所述的埋氧层的三角形槽的形成方式是先在硅表面上注入氧离子,形成二氧化硅层,然后在其表面蚀刻出三角形槽,再着沉积多晶硅,最后与另一硅片键合并减薄。
其中,所述的埋氧层沟槽的三角形形状并不是唯一的,只要能使埋氧层表面倾斜都可以;埋氧层上下界面都可各蚀刻一个三角形沟槽。
其中,其特征是在漂移区和衬底之间的绝缘SiO2层(常称为埋氧层),如此,在漂移区下方就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷,这些电荷大力度的提高了器件的纵向耐压;而且,器件漂移区厚度从源到漏线性增加,根据RESURF(降低表面电场)原理,横向电场因受到调制而变得均匀,有利于提高横向耐压和抑制比导通电阻的快速增加。
上面所述的实施例仅仅是对本发明的优选实施方式进行描述,并非对本发明的构思和范围进行限定。在不脱离本发明设计构思的前提下,本领域普通人员对本发明的技术方案做出的各种变型和改进,均应落入到本发明的保护范围,本发明请求保护的技术内容,已经全部记载在权利要求书中。
Claims (7)
1.一种带三角槽的SOI-LDMOS高压功率器件,其主要包括:衬底电极、纵向由下而上的P型衬底、漂移区、源电极、漏电极、栅电极、绝缘SiO2层(常称为埋氧层)和空穴层;其中所述的漂移区横向两端分别形成了n+源区和n+漏区,在n+源区的边上是p体区;所述的埋氧层上蚀刻出了一个三角形沟槽,如此在漂移区下方就存在一个埋氧层斜面,所述的空穴层就在这个埋氧层斜面上。
2.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征在于:所述的整个埋氧层均处于水平面,能与低压电路完全的集成在一起;因此,当此器件的埋氧层与常规器件的厚度一样时,他的等效厚度会比常规器件薄,就能有效缓解自热效应。
3.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征在于:所述的漂移区长度为30μm,埋氧层厚度为1μm,三角槽深度为0.5μm时,埋氧层电场被增强到7×106V/cm,耐压为353V。
4.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征在于:所述的埋氧层为绝缘SiO2层,SiO2是热的不良导体,增加埋氧层厚度会使自热效应更加严重,而增加漂移区厚度会导致掺杂浓度降低,比导通电阻迅速增加,最后厚的漂移区和埋氧层也不利于与低压电路集成,因此埋氧层和漂移区的厚度一定要薄。
5.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征在于:所述的埋氧层的三角形槽的形成方式是先在硅表面上注入氧离子,形成二氧化硅层,然后在其表面蚀刻出三角形槽,再着沉积多晶硅,最后与另一硅片键合并减薄。
6.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征在于:所述的埋氧层沟槽的三角形形状并不是唯一的,只要能使埋氧层表面倾斜都可以;埋氧层上下界面都可各蚀刻一个三角形沟槽。
7.根据权利要求1所述的一种带三角槽的SOI-LDMOS高压功率器件,其特征是在漂移区和衬底之间的绝缘SiO2层(常称为埋氧层),如此,在漂移区下方就存在一个埋氧层斜面,它可以束缚带正电的空穴,形成高浓度的正面电荷,这些电荷大力度的提高了器件的纵向耐压;而且,器件漂移区厚度从源到漏线性增加,根据RESURF(降低表面电场)原理,横向电场因受到调制而变得均匀,有利于提高横向耐压和抑制比导通电阻的快速增加。
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