CN104241235B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN104241235B
CN104241235B CN201410253650.7A CN201410253650A CN104241235B CN 104241235 B CN104241235 B CN 104241235B CN 201410253650 A CN201410253650 A CN 201410253650A CN 104241235 B CN104241235 B CN 104241235B
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conductor pin
semiconductor chip
center
mep
semiconductor devices
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CN201410253650.7A
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CN104241235A (zh
Inventor
小野善宏
木田刚
坂田贤治
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

一种半导体芯片和插线板通过导体柱彼此耦合。位于最外围开口之上的导体柱的中心在远离半导体芯片的中心的方向上偏离开口的中心。当将其中每个导体柱和绝缘层彼此重叠的区域指定为重叠区域时，重叠区域的比开口在更内侧上的宽度小于重叠区域的比开口在更外侧上的宽度。因此，当作用在导体柱上的应力被释放时，保持了半导体芯片和接线板之间的耦合可靠性。

Description

半导体器件
相关申请的交叉引用
2013年6月7日提交的日本专利申请公开No.2013-121005的包括说明书、附图和说明书摘要的全部内容以引用的方式并入本文。
技术领域
本发明涉及一种半导体器件，例如，一种可以应用于具有导体柱的半导体器件的技术。
背景技术
在将半导体芯片安装在接线板上时会使用到半导体器件。将半导体芯片安装到半导体器件的方法通常包括使用接线键合和倒装芯片安装的一种方法。与这些方法相反，其中通过在半导体芯片的电极之上形成导体柱并且在导体柱之上形成焊料层，来将半导体芯片面朝下地安装在接线板之上的方法正在研究中。与导体柱相关的技术包括专利文件1中公开的一种技术。
专利文件2公开了，在将在电极之上形成凸块时，凸块偏离电极。专利文件3教导了，在需要通过使用印刷技术在电极之上形成凸块时，掩膜的开口偏离电极。更具体地说，关于定位在芯片角处的电极，专利文件3教导了，掩膜的开口偏离芯片的中心。
[现有技术文件]
[专利文件]
[专利文件1]
日本特开No.2011-204840
[专利文件2]
日本特开No.2012-79973
[专利文件3]
日本特开No.2004-349621
发明内容
在与接线板水平的平面方向上，半导体芯片的线性热膨胀系数与接线板的线性热膨胀系数不同。因此，当半导体器件中发生温度改变时，在半导体芯片和接线板之间的界面上在剪切方向上产生应力。当半导体芯片和接线板通过导体柱彼此耦合时，该应力作用于导体柱。随着与半导体芯片的中心的距离的增加，作用于导体柱的应力会变得更大。因此，在电极和位于半导体芯片角处的导体柱之间的界面处，可能发生剥落。特别是当绝缘层SR1的温度变得高于其软化点时，绝缘层SR1不能吸收应力，据此发生剥落的可能性变得高。
与绝缘层SR1的温度变得高于其软化点相反时，可以想象的是，这引起绝缘膜在电极的外围之上延展，并且进一步地引起导体柱的外围在绝缘膜之上延展。根据该结构，作用在导体柱上的应力通过绝缘膜得以释放。然而，为了增加导体柱外围的这种延展量，必须使得导体柱的直径大，或者必须使得用于暴露形成在绝缘膜中的电极的开口小。然而，当使得导体柱的直径大时，导体柱的节距变得小，据此相邻导体柱可能会经由焊料发生短路。当使得开口小时，导体柱和电极之间的耦合电阻变得大。因此，在作用在导体柱上的应力被释放时，难以保持半导体芯片和接线板之间的耦合可靠性。其它目的和新颖特征将由本说明书的说明和附图而变得显而易见。
[解决方案]
将导体柱和绝缘膜彼此重叠的部分指定为重叠区域。第一直线从最接近半导体芯片第一侧一端的第一导体柱的中心(起点)延伸到半导体芯片的衬底中心(终点)。根据本发明的实施例，作为位于第一直线上的重叠区域宽度的第一宽度小于作为延长线上重叠区域宽度的第二宽度，延长线在第一直线经过第一导体柱中心的方向上延伸。第二直线，作为经过第一导体柱中心以及与在绝缘膜中形成的开口外的第一导体柱重叠的第一开口中心的直线，与第一侧相交呈一定角度，但是不为90°。
根据本发明的上述实施例，在释放作用在导体柱上的应力时，可以保持半导体芯片和接线板之间的耦合可靠性。
附图说明
图1A是根据本发明的一个实施例的半导体器件的平面图，而图1B为图1A的A-A截面图；
图2是图1B所示结构的部分放大图；
图3是示出了在接线板第二表面之上形成的外部端子的布局的示意图；
图4是用于解释在半导体芯片中的电极布置的示意图；
图5A是用于解释在第一区域中第一开口和在第一开口上方的导体柱的相对位置的示意图，而图5B是图5A中虚线范围内的区域的放大图；
图6A是用于解释在第二区域中开口和在开口上方的导体柱的相对位置的示意图，而图6B是图6A中虚线包围的区域的放大图；
图7是用于解释在第三区域中开口和在开口上方的导体柱的相对位置的示意图；
图8是用于解释接线板中的开口的形状的示意图；
图9是示出了在开口中的第一端子的布置示例的示意图；
图10是示出了导体柱的构造的截面图；
图11A和图11B是用于解释在半导体器件中生成的应力的示意图；
图12是用于解释在半导体芯片的导体柱和接线板的第一端子之间的耦合结构的截面图；
图13A至图13D是示出了在半导体芯片中形成导体柱的方法的截面图；
图14A至图14D是用于解释将半导体芯片安装于接线板的方法一个示例的截面图；
图15是示出了接线板的构造的平面图；
图16是示出了根据修改例1的半导体器件的半导体芯片的构造的截面图；
图17是示出了根据修改例2的半导体器件的半导体芯片的构造的截面图；
图18是示出了根据修改例3的半导体器件的半导体芯片的构造的截面图；
图19A至图19E是示出了在半导体芯片的第一区域中开口和导体柱的相对位置的修改例的截面图；
图20是示出了具有半导体器件的电子装置的第一示例的截面图；
图21是示出了具有半导体器件的电子装置的第二示例的截面图；
图22是示出了具有半导体器件的电子装置的第三示例的截面图；
图23是示出了具有半导体器件的电子装置的第四示例的截面图；
图24是示出了具有半导体器件的电子装置的第五示例的截面图；
图25是示出了具有半导体器件的电子装置的第六示例的截面图；
图26是示出了具有半导体器件的电子装置的第七示例的截面图；
图27是示出了具有半导体器件的电子装置的第八示例的截面图；
图28是示出了根据第九示例的电子装置的半导体器件的截面图。
具体实施方式
下面将参照附图对本发明的优选的实施例进行描述。在所有附图中，为相似的构成元件给定了相似的附图标记并且省略了对其的说明。
(实施例)
图1A是根据该实施例的半导体器件SD的平面图。图1B是图1A的A-A’截面图。在图1A中，出于图示的目的省略了密封树脂MDR。
半导体器件SD包括接线板IP和半导体芯片SC。半导体芯片SC具有多个电极，这些电极以这样的方式安装在接线板IP的第一表面之上，使得它们面朝接线板IP的第一表面。半导体芯片SC的电极EL(其将在下文中描述)和接线板IP的端子通过使用导体柱MEP彼此耦合。半导体芯片SC和接线板IP之间的空间用密封材料RL密封。密封材料RL为例如NCF(非导电膜)，并且可以为NCP(非导电胶)或如将在下文中描述的底部填充树脂。
接线板IP的第一表面和半导体芯片SC用密封树脂MDR密封。在图1B所示的示例中，密封树脂MDR的外围位于在平面图中接线板IP的内侧上。密封树脂MDR的外围和接线板的外围可以形成相同的平面。
多个外部端子SB，例如焊球，形成在与接线板IP的第一表面相对的第二表面之上。外部端子SB用于将半导体器件SD安装在电路板(例如，母版)上。
接线板IP和半导体芯片SC均为矩形或方形。半导体芯片SC比接线板IP小。接线板IP一侧的长度在例如8mm或更大至15mm或更小范围内。半导体芯片SC的一侧的长度在例如3mm或更大至10mm或更小范围内。接线板IP的厚度在例如0.2mm或更大至0.6mm或更小范围内。半导体芯片SC的厚度在例如0.05mm或更大至0.4mm或更小范围内。
图2是图1B所示结构的部分放大图；在该图所示的示例中，接线板IP为组合(built-up)基板并且具有四个接线层。位于与第二表面(在图中为下侧)最接近处的接线层具有多个第二端子LND(例如，焊盘)。外部端子SB与相应的第二端子LND连接。
位于与接线板IP的第一表面(在图中为上侧)最接近处的接线层位于绝缘层IL之上并且具有多个第一端子FNG。第一端子FNG耦合至相应的导体柱MEP。绝缘层SR2，例如阻焊层，形成在接线板IP的第一表面之上。开口SRO形成在绝缘层SR2中。第一端子FNG位于相应的开口SRO中。
图3是示出了在接线板IP的第二表面之上的外部端子SB的布局的示意图。在该平面图中，外部端子SB设置在接线板IP的中央侧上的区域以及接线板IP的外围侧上的区域中。在中央侧上的区域的最外位置的外部端子SB和在外围侧上的区域的最内位置的外部端子SB之间的距离大于在中央侧上的区域中的外部端子SB的总距离以及在外围侧上的区域中的外部端子SB的总距离。外部端子SB的布置不限于该图中示出的布置。例如，外部端子SB可以仅设置在接线板IP的外围侧上的区域中或者接线板IP的整个表面之上。
图4是用于解释半导体芯片SC中的电极EL的布置的示意图；电极EL沿半导体芯片SC的四侧(第一侧SID1、第二侧SID2、第三侧SID3以及第四侧SID4)分多行(图中为两行)布置。绝缘层SR1(其将在下文中描述)形成在具有半导体芯片SC的电极EL的表面之上。开口OP形成在绝缘层SR1中。开口OP形成在相应的电极EL上方。导体柱MEP形成在相应的开口OP上方。开口OP可以不以相等间距布置。例如，多数开口OP以相等间距布置但是某些开口OP的间距可以比其余间距更宽。开口OP的行可以形成正方形的网格或Z字形。
在该图所示的示例中，多个电极EL和多个开口OP形成在半导体芯片SC的中央部分中。导体柱MEP也形成在开口OP上方。在半导体芯片SC中央部分中的导体柱MEP的布局密度小于在半导体芯片SC外围部分中的导体柱MEP的布局密度。
在该平面图中，各个导体柱MEP的尺寸均大于各个开口OP。因此，导体柱MEP的外围在绝缘层SR1之上延展。在该图所示的示例中，导体柱MEP的整个外围均在绝缘层SR1之上延展。
在该平面图中，导体柱MEP的中心和开口OP的中心的相对位置根据开口OP在半导体芯片SC中的位置而有所不同。例如，对于位于最外围处的开口OP和导体柱MEP，导体柱MEP的中心在朝着半导体芯片SC的外侧的方向上偏离与导体柱MEP重叠的开口OP的中心。例如，在以半导体芯片SC的中心CEN1为基准时，该偏离方向可以认为是径向的，。
下文将以第一区域AR1、第二区域AR2和第三区域AR3为例做出解释。第一区域AR1包含与半导体芯片SC的第一侧SID1的一端最接近的开口OP(第一开口OP1)。第二区域AR2包含与第一侧SID1的中心最接近的开口OP。第三区域AR3包含在半导体芯片SC的中央部分中的开口OP。
在下文的描述中，半导体芯片SC的中心CEN1限定为例如半导体芯片SC的对角线的交叉点。参照图5、图6和图7进行描述的内容还可以适用于除了第一侧SID1的三侧(第二侧SID2、第三侧SID3和第四侧SID4)。
图5A是用于解释在第一区域AR1中第一开口OP1和位于开口OP1上方的导体柱EMP(第一导体柱MEP1)的相对位置的示意图。图5B是图5A中虚线范围内的区域的放大图。
如参照图4，开口OP和导体柱MEP沿第一侧SID1分多行布置。除了在最外围的开口OP处以外，其它开口OP的中心几乎与位于开口OP上方的导体柱MEP的中心对准。与此相反，位于最外围处的开口OP的中心偏离位于开口OP上方的导体柱MEP的中心。
更具体地说，如图5A所示，位于在最外围的开口OP上方的导体柱MEP的中心在远离半导体芯片SC的中心CEN1的方向上偏离开口OP的中心。特别地，第一开口OP1的位置和第一导体柱MEP1的位置将被相互比较。将从第一开口OP1的中心CEN3(作为起点)延伸至半导体芯片SC的中心CEN1(半导体芯片SC的衬底的中心)(作为终点)的直线设计为第一直线STL1。将导体柱MEP和绝缘层SR1彼此重叠的区域指定为重叠区域。位于第一直线STL1上的重叠区域的宽度(第一宽度)小于在延长线EXL上的重叠区域的宽度(第二宽度)，该延长线朝第一直线STL1的半导体芯片SC的外部侧延伸(即，第一直线STL1的在经过第一导体柱MEP1的中心的方向上延伸的延长线)。换言之，比第一开口OP1与半导体芯片SC的中央侧更接近的重叠区域宽度小于比第一开口OP1与第一侧SID1更接近的重叠区域宽度。
如图5B所示，第一导体柱MEP1的中心CEN2比第一开口OP1的中心CEN3更远离半导体芯片SC的中心CEN1。进一步地，由经过中心CEN2和中心CEN3的直线(第二直线STL2)与第一侧STD1形成的角度θ1不为90°(根据该图的限定，小于90°)。
图6A是用于解释在第二区域AR2中开口OP和在开口上方的导体柱MEP的相对位置的示意图。图6B为图6A中由虚线包围的区域的放大图。同样在第二区域AR2中，除最外围的开口之外的其它开口OP的中心几乎与位于这些开口上方的导体柱MEP的中心对准。与此相反，位于最外围的开口OP的中心在朝着第一侧SID1的方向上偏离位于这些开口上方的导体柱MEP的中心。因此，在第二区域AR2中，比开口OP与半导体芯片SC的中央侧更接近的重叠区域宽度小于比开口OP与接近第一侧SID1更接近的重叠区域宽度。
如图6B所示，接近与第一侧SID1的中心最接近的导体柱MEP(第二导体柱MEP2)的中心CEN5比开口OP(第二开口OP2)的中心CEN4更远离半导体芯片SC的中心CEN1。由经过第二导体柱MEP2的中心CEN5和第二开口OP2的中心CEN4的直线(第三直线STL3)与第一侧SID1形成的角度θ2为90°或比θ1更接近90°。
由图5和图6应理解，在第一侧SID1的一端侧的1/3中的导体柱MEP的布置节距(例如，在一个区域(包括第一区域AR1)中的导体柱MEP的布置节距)的平均值比在第一侧SID1的下一个1/3中的导体柱MEP的布置节距(例如，在一个区域(包括第二区域AR2)中的导体柱MEP的布置节距)的平均值更大。换言之，随着与半导体芯片SC的中心CEN1的距离变得更大，导体柱MEP的中心相对于开口更多地朝半导体芯片SC的外侧移动。在这种情况下，下文待述的应力松弛效应变大。
还应理解的是，导体柱MEP的布置节距的平均值比开口OP的布置节距的平均值更大。因此，如下文所描述的，可以使接线板IP的第一端子FNG的布置节距比开口OP的布置节距更大。
如图5和图6所示，从外侧来看，第二行中的导体柱MEP的中心几乎与和导体柱MEP重叠的开口OP的中心对准。
图7是用于解释在第三区域AR3中开口OP和在的开口OP上方的导体柱MEP的相对位置的示意图。如该图所示，在第三区域AR3中，导体柱MEP的中心几乎与开口OP的中心对准。即使是在第三区域AR3中，导体柱MEP的中心也可以在远离半导体芯片SC的中心的方向上(例如径向方向)偏离开口OP的中心。
图8是用于解释接线板IP的开口SRO的形状的示意图。该图示出了接线板IP的待安装半导体芯片SC的表面。开口SRO形成在与半导体芯片SC的导体柱MEP相对的区域中。
更具体地说，导体柱MEP首先沿半导体芯片SC的外围布置。因此，开口SRO具有沿半导体芯片SC的外围的形状。导体柱MEP也布置在半导体芯片SC的中央部分中。因此，开口SRO也形成在半导体芯片SC的中央部分中。多个第一端子FNG(未在图中示出)形成在开口SRO中。第一端子FNG位于与相应的导体柱MEP的位置上。
如上所描述的，位于半导体芯片SC的外围处的导体柱MEP的中心偏离与导体柱MEP相对应的开口OP的中心。因此，第一端子FNG的布置节距比开口OP的布置节距更大。
图9是示出了开口SRO中的第一端子FNG的布置的一个示例的示意图；如上所描述的，第一端子FNG的布置节距比半导体芯片SC的开口OP的布置节距更大。因此，接线INC1可以这样布置，使得它们在某些第一端子FNG之间经过。接线INC1形成在与第一端子FNG相同的层中。每个接线INC1的在开口SRO中存在的部分可为直的或部分弯曲的。
图10是示出了导体柱MEP的构造的截面图。在该图所示的示例中，半导体芯片SC具有在衬底SUB之上的复合接线层MIL。最顶部的接线层具有电极EL。复合接线层MIL的外部的最顶层为保护绝缘膜PSL(例如包括氧化硅层和氮化硅层的叠层膜)。由于每个电极EL的一部分位于保护绝缘膜PSL中形成的开口中，所以该部分从保护绝缘膜PSL中露出来。阻挡金属层BRM2形成在电极EL下方。
绝缘层SR1形成在保护绝缘膜PSL上方。绝缘层SR1为例如阻焊层。位于电极EL上方的开口OP形成在绝缘层SR1中。阻挡金属层BRM1形成在位于开口OP中的电极EL和位于电极EL周围的绝缘层SR1之上。阻挡金属层BRM1包括TiN层、Ti层和TiW层中的至少一个。
导体柱MEP形成在阻挡金属层BRM1之上。导体柱MEP由例如柱状Cu制成。导体柱MEP的高度在例如15μm或更大至50μm或更小范围内。Ni层NIL和焊料层SLD以此顺序形成在导体柱MEP之上。Ni层NIL的厚度小于导体柱MEP的高度。合金层可以形成在Ni层NIL和导体柱MEP之间的界面以及Ni层NIL和焊料层SLD之间的界面中的至少一个界面上。在该图中，合金层ALL形成在Ni层NIL和焊料层SLD之间的界面上。
保护绝缘膜PSL(第二绝缘膜)具有沿电极EL的外围的凸出部。导体柱MEP的一部分(在该图左侧的部分)位于保护绝缘膜PSL的凸出部的外侧上。在该图所示的示例中，导体柱MEP的另一部分(在该图右侧的部分)位于电极EL的内侧上。在该平面图中，在该图右侧的部分也可以位于电极EL的外侧上。
图11A和图11B是用于解释半导体器件SD中生成的应力的示意图。接线板IP利用树脂形成。因此，接线板IP的线性膨胀系数大于半导体芯片SC的线性膨胀系数。因此如图11A所示，当半导体器件SD的温度上升时，张应力在半导体芯片SC与接线板IP之间的界面上作用在半导体芯片SC的顶表面上。另一方面如图11B所示，当半导体器件SD的温度下降时，压应力在半导体芯片SC与接线板IP之间的界面上作用在半导体芯片SC的顶表面上。当压应力作用在半导体芯片SC的后表面时的各种需要采取的措施正在研究中。为处理这种情况，本发明的发明者发现，即使是在半导体器件的温度上升时(即，即使是在张应力作用在半导体芯片SC的后表面上时)，也必须采取措施。将参照图12对此进行解释。
图12是用于解释在半导体芯片SC的导体柱MEP和接线板IP的第一端子FNG之间的耦合结构的截面图。在该图中，左侧为半导体芯片SC的外侧(例如，第一侧SID1)。
如该图所示，导体柱MEP和第一端子FNG经由焊料层SLD彼此耦合。当施加半导体器件SD的温度时，力被施加于导体柱MEP的与焊料层SLD耦合的耦合表面(顶表面)，该力在使导体柱MEP移向半导体芯片SC的外围(在该图中为从右侧到左侧)的方向上。在这种情况下，以导体柱MEP下表面的与半导体芯片SC的外围接近的端部作为支点，在将导体柱MEP从半导体芯片SC的电极EL剥落的方向上施加一个力。
为处理这种情况，在本实施例中使导体柱MEP的中心比开口OP的中心更接近半导体芯片SC的外围。因此，可以使从支点到作用点的距离大于从施力点到支点的距离。因此，可以以防止导体柱MEP与半导体芯片SC分离。
当复合接线层MIL中的至少一个为具有比氧化硅膜的介电常数更低的介电常数的低介电常数膜(例如多孔膜)时，脱落等不便可能发生在位于低介电常数膜的导体柱MEP下方的部分。在该实施例中，也可以抑制这种不便的发生。
随后将参照图13A至图13D对生产半导体芯片SC的方法进行说明。图13A至图13D是示出了形成半导体芯片SC的导体柱MEP的方法的截面图。在图13A至图13D中，为了便于解释，导体柱MEP的中心与第一开口OP1的中心对准。
首先在衬底SUB(例如，硅片)之上形成元件分离膜。从而，元件形成区域被分离。元件分离膜通过使用例如STI方法形成或者可以通过使用LOCOS方法形成。然后，位于元件形成区域中、在衬底SUB之上形成栅极绝缘膜和栅极电极。栅极绝缘膜可以为氧化硅膜或者具有比氧化硅膜的介电常数更高的介电常数的高介电常数膜(例如硅酸鉿膜)。当栅极绝缘膜为氧化硅膜时，栅极电极由多晶硅膜制成。当栅极绝缘膜为高介电常数膜时，栅极电极由包括金属膜(例如TiN)和多晶硅膜的叠层膜制成。当栅极电极由多晶硅制成时，可以在形成栅极电极的步骤中在元件分离膜之上形成多晶硅电阻器。
然后，位于元件分离区域中、在衬底SUB中形成源极和漏极延伸区。其后，在栅极电极的侧壁之上形成侧壁。位于元件形成区域中、在的衬底SUB之上形成将会成为源极和漏极的杂质区。从而，在衬底SUB之上形成MOS晶体管。
然后，在元件分离膜和MOS晶体管之上形成复合接线层MIL。在最顶部接线层中形成电极EL。此时，在电极EL下方形成阻挡金属层BRM2(未在图13中示出)。然后，在复合接线层MIL之上形成保护绝缘膜PSL和开口。
然后，如图13A所示，在保护绝缘膜PSL和电极EL上方形成绝缘层SR1和绝缘层SR1的开口OP。例如通过涂层，来形成绝缘层SR1。当绝缘层SR1为感光膜(诸如阻焊膜)时，通过曝光和显影来形成绝缘层SR1的开口OP。然后，在绝缘层SR1和电极EL之上形成阻挡金属层BRM1。
然后，如图13B所示，在阻挡金属层ERM1之上形成保护图案(resist pattern)RS1。保护图案RS1在待形成导体柱MEP的区域中具有开口。
然后，如图13C所示，通过将从保护图案RS1露出的阻挡金属层BRM1用作种子层来执行电镀。从而，以此顺序形成导体柱MEP、Ni层NIL和焊料层SLD。
其后，如图13D所示，移除保护图案RS1。例如通过湿法蚀刻，来移除阻挡金属层BRM1的未被导体柱MEP覆盖的部分。
其后，使焊料层SLD熔化并凝固。由此形成导体柱MEP。在形成导体柱MEP之后，通过切割获得为分离的片的半导体芯片SC。
图14A至图14D是用于解释将半导体芯片SC安装至接线板IP的方法的一个示例的截面图。这些图所示的方法将NCF用作密封材料RL。首先准备好接线板IP。如图15所示，多个接线板IP彼此耦合。
在接线板IP的第一端子FNG的顶表面、侧表面和端表面之上形成Ni层和Au层。可以在Ni层和Au层之间形成Pd层。可以在这些表面之上焊料层形成(诸如Sn层或SnAg层)，或者，这些表面可以经受OSP处理(预焊剂处理)。
然后，如图14A所示，作为密封材料RL的NCF布置在多个接线板IP之上。
然后，如图14B所示，半导体芯片SC以这样的方式布置在密封材料RL之上，使得导体柱MEP面朝接线板IP的。其后，将半导体芯片SC压入密封材料RL中。从而，使接线板IP的第一端子FNG(未图示)和在半导体芯片SC的导体柱MEP之上的焊料层SLD(未图示)彼此接触。在这种状态下，加热并且然后冷却半导体芯片SC和接线板IP。从而使焊料层SLD键合至第一端子FNG。
然后，如图14C所示，使用密封材料MDR分别密封多个接线板IP和多个半导体芯片SC。外部端子SB与接线板IP的第二表面连接。
然后，如图14D所示，切割接线板IP，获得独立的半导体器件SD。
在图14A所示的步骤中，可以在接线板上覆盖NCP(非导电胶)代替NCF，或者可以在将半导体芯片SC安装至接线板IP之后，利用毛细现象来将底部填充树脂充满在半导体芯片SC和接线板IP之间。可以将NCF附于半导体芯片SC而非附于接线板IP。
根据该实施例，当将导体柱MEP和绝缘层SR1彼此重叠的区域指定为重叠区域时，比开口第一OP1与半导体芯片SC的中央侧更接近的重叠区域宽度小于比第一开口OP1与第一侧SID1更接近的重叠区域宽度。因此，当半导体器件SD的温度上升时，能够防止导体柱MEP与半导体芯片SC分开。
(修改例1)
图16是示出了根据修改例1的半导体器件SD的半导体芯片SC的构造的截面图。该图所示的半导体芯片SC具有与根据上述实施例的半导体芯片SC的构造相同的构造，除了该半导体芯片SC在导体柱MEP和焊料层SLD之间不具有Ni层NIL和合金层ALL。
通过本修改例可以获得与根据上述实施例的半导体器件SD相同的效果。
修改例2
图17是示出了根据修改例2的半导体器件的半导体芯片SC的构造的截面图。该图所示的半导体芯片SC具有与根据修改例1的半导体芯片SC的构造相同的构造，除了该半导体芯片SC不具有绝缘层SR1。在该修改例中，在将确定导体柱MEP的位置时，形成在保护绝缘膜PSL中的开口与修改例1中的开口OP相对应。
通过本修改例也可以获得与根据上述实施例的半导体器件SD相同的效果。
(修改例3)
图18是示出了根据修改例3的半导体器件的半导体芯片SC的构造的截面图。该图所示的半导体芯片SC具有与根据上述实施例以及修改例1和修改例2中的任一实施例的半导体器件的构造相同的构造，除了在平面视图中至少部分导体柱MEP与半导体芯片SC的保护环GDL重叠。
通过本修改例也可以获得与根据上述实施例的半导体器件SD相同的效果。
(修改例4)
根据本修改例的半导体器件SD与上述实施例和修改例1-3中的任一实施例相同，除了开口OP和在半导体芯片SC的第一区域AR1中的导体柱MEP的相对位置。
在图19A所示的示例中，第一导体柱MEP1在与第二侧SID2平行的方向上偏离第一开口OP1。这也同样适用于导体柱MEP，除了第一导体柱MEP1。更具体地说，在沿第一侧SID1布置的导体柱MEP中，位于最外围的导体柱MEP在与第二侧SID2平行的方向上偏离开口OP。偏离宽度可以随着导体柱MEP与第一侧SID1的端部更接近而更大。
在图19B所示的示例中，第一导体柱MEP1在与第一侧SID1平行的方向上偏离第一开口OP1。这也同样适用于导体柱MEP，除了第一导体柱MEP1。更具体地说，在沿第一侧SID1布置的导体柱MEP中，位于最外围的导体柱MEP在与第一侧SID1平行的方向上偏离开口OP。偏离宽度可以随着导体柱MEP与第一侧SID1的端部更接近而更大。
在图19C所示的示例中，不仅位于最外围的导体柱MEP，还有位于该行中更内侧的导体柱MEP都在如上述实施例所示的相同方向上偏移。
在图19D所示的示例中，不仅位于最外围的导体柱MEP，还有位于该行中更内侧的导体柱MEP都在如图19A所示的相同方向上偏移。
在图19E所示的示例中，不仅位于最外围的导体柱MEP，还有位于该行中更内侧的导体柱MEP都在如图19B所示的相同方向上偏移。
在图19C至19E中，第二行中的各个导体柱MEP从外侧偏移的量小于位于最外围的各个导体柱MEP的偏离量。这些偏离量可以是相同的。
通过本修改例也可以获得与根据上述实施例相同的效果。
(修改例5)
图20是示出了具有半导体器件SD的电子装置的第一示例的截面图。该电子装置具有通常称谓的POP(叠层封装)结构，在该结构中，半导体器件SD2安装在半导体器件SD之上。
更具体地说，密封树脂MDR不覆盖接线板IP的外围部分的至少一部分。将用于耦合半导体器件SD2的外部端子SB2的端子设置在接线板IP的第一表面的未用密封树脂MDR覆盖的部分中。
半导体器件SD2具有这样的构造，使得半导体芯片SC2安装在接线板IP2之上并且通过键合接线WIR耦合至接线板IP2。用密封树脂MDR2密封半导体芯片SC2和键合接线WIR。
在该图所示的示例中，当将半导体器件SD2安装在半导体器件SD之上时，对半导体器件SD供热以熔化外部端子SB2。将应力通过该热量作用于导体柱MEP。在该修改例中，能够通过上述实施例中解释的功能来防止导体柱MEP与半导体芯片SC分开。
图21是示出了具有半导体器件SD的电子装置的第二示例的截面图。该图所示的示例具有与图20所示示例的结构相同的结构，除了半导体器件SD不具有密封树脂MDR。
图22是示出了具有半导体器件SD的电子装置的第三示例的截面图。在该图中，半导体器件SD具有通常称谓的COC(叠层芯片)结构，在该结构中，半导体器件SD具有在半导体芯片SC之上的半导体芯片SC2。半导体芯片SC2和接线板IP通过键合接线WIR彼此耦合。用密封树脂MDR密封半导体芯片SC、半导体芯片SC2和键合接线WIR。
图23是示出了具有半导体器件SD的电子装置的第四示例的截面图。在该修改例中，金属体HS经由树脂层BNL1安装在半导体芯片SC之上。金属体HS的外围朝接线板IP弯曲并且经由树脂层BNL2耦合至接线板IP。即，在该示例中将半导体芯片SC生成的热量经由金属体HS释放至其它部分。
图24是示出了具有半导体器件SD的电子装置的第五示例的截面图。根据该修改例的电子装置具有与图23所示电子装置的构造相同的构造，除了以下几点。第一，金属体HS为平板。金属体HS的外围与接线板IP经由树脂层BNL2、环形金属板STF(例如加强件)和树脂层BNL3耦合至接线板IP。
图25是示出了具有半导体器件SD的电子装置的第六示例的截面图。根据该实施例的电子装置具有与图24所示示例的构造相同的构造，除了该电子装置不具有金属体HS和树脂层BNL2，以及除了该树脂层BNL在平面视图中还可以形成在金属体HS和半导体芯片SC之间。
图26是示出了具有半导体器件SD的电子装置的第七示例的截面图。根据该修改例的电子装置具有与图23所示电子装置的构造相同的构造，除了以下几点。第一，金属体HS为平板并且安装在半导体芯片SC的后表面之上。金属体HS的外围不耦合至接线板IP。
图27是示出了具有半导体器件SD的电子装置的第八示例的截面图。根据该修改例的电子装置具有与图23所示电子装置的构造相同的构造，除了该电子装置不具有金属体HS和树脂层BNL1和BNL2。
图28是示出了具有半导体器件SD的电子装置的第九示例的截面图。根据该修改例的电子装置的半导体器件SD具有与根据上述实施例的半导体器件SD的构造相同的构造，除了在半导体芯片SC之上安装至少一个半导体芯片SC2。
更具体地说，用密封材料RL2密封半导体芯片SC2的侧表面。在半导体芯片SC中形成穿通电极TSV1，在半导体芯片SC2中形成穿通电极TSV2。半导体芯片SC2经由穿通电极TSV2耦合至半导体芯片SC。在该图所示的示例中，在平面图中，穿通电极TSV2与相应的穿通电极TSV1对准。例如，半导体芯片SC2为存储芯片，而半导体芯片SC为逻辑芯片。
第一至第三示例为便携式电子装置，诸如便携式通信终端和便携式游戏设备。第四至第九示例为图像再现设备，诸如导航设备和TV。
通过这些修改例可以获得与根据上述实施例相同的效果。
虽然已参照本发明的优选实施例对本发明的发明者做出的发明进行了具体描述，但是应理解，本发明并不限于此，并且在不脱离本发明的精神和范围的条件下，可以对本发明进行改变和变化。

Claims (7)

1.一种半导体器件，其包括：
具有第一主面和在所述第一主面上形成的多个电极的接线板，以及
半导体芯片，其安装在所述接线板之上并且经由多个焊料耦合至所述电极，
其中，所述半导体芯片包括：
第二主面、在所述第二主面上形成的多个电极焊盘、
覆盖所述多个电极焊盘的各自的电极焊盘的一部分的第一绝缘膜、
从所述多个电极焊盘上的所述第一绝缘膜露出的多个开口部、
在所述多个电极焊盘和所述第一绝缘膜上形成并连接到所述多个焊料上的多个导体柱、以及
在所述多个电极焊盘中的第一电极焊盘的外侧形成的保护环；
其中，所述多个导体柱中的第一导体柱与所述第一绝缘膜重叠的部分指定为重叠区域时，第一宽度小于第二宽度，所述第一宽度为所述重叠区域的位于第一直线上的宽度，所述第一直线经过所述第一导体柱的中心和所述半导体芯片的中心，所述第二宽度为所述重叠区域的位于延长线上的宽度，所述延长线在经过所述第一直线的所述第一导体柱的中心的方向上延伸，
在截面图中，所述第一导体柱被设置为覆盖所述保护环。
2.根据权利要求1所述的半导体器件，
其中，所述第一导体柱的所述中心比多个所述开口部中的位于所述第一电极焊盘上的第一开口部的中心更远离所述半导体芯片的所述中心。
3.根据权利要求1所述的半导体器件，
其中，所述半导体芯片具有覆盖所述第二主面上的所述多个电极焊盘的各自的电极焊盘的一部分的第二绝缘膜，
所述第二绝缘膜由所述第一绝缘膜覆盖。
4.根据权利要求1所述的半导体器件，
其中，所述导体柱的布置节距的平均值比所述开口部的布置节距的平均值更大。
5.根据权利要求1所述的半导体器件，
其中，在平面图中，所述第一导体柱是所述多个导体柱中的与所述半导体芯片的端部最接近的导体柱。
6.根据权利要求3所述的半导体器件，
其中，所述第二绝缘膜是氧化硅和氮化硅的叠层膜。
7.根据权利要求1所述的半导体器件，
其中，所述多个电极焊盘、所述多个开口部和所述多个导体柱沿所述半导体芯片的第一侧以至少两行布置，以及
在所述两行中更内一行中的所述导体柱的中心和与所述导体柱重叠的所述开口部的中心对准。
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