CN104170089B - 用于ac led的硅衬底上的氮化镓led与氮化铝镓/氮化镓器件的集成 - Google Patents
用于ac led的硅衬底上的氮化镓led与氮化铝镓/氮化镓器件的集成 Download PDFInfo
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Abstract
一种用于制造外延结构的方法,包括提供衬底(102,202,302,402)和衬底的第一侧上的异质结堆叠,以及在衬底的第二侧上形成GaN发光二极管堆叠(134)。异质结堆叠包括无掺杂氮化镓(GaN)层和无掺杂GaN层上的掺杂氮化铝镓(AlGaN)层。GaN发光二极管堆叠(134)包括衬底之上的n型GaN层(136)、n型GaN层之上的GaN/氮化铟镓(InGaN)多量子阱(MQW)结构(138)、n型GaN/InGaN MQW结构之上的p型AlGaN层(140),以及p型AlGaN层之上的p型GaN层(142)。
Description
技术领域
本公开涉及半导体发光二极管,并且更具体地涉及具有衬底上的氮化铝镓/氮化镓器件的氮化镓发光二极管。
背景技术
发光二极管(LED)是需要恒定电压供给的直流(DC)器件。然而,基于LED的灯具从交流电压(AC)的市电电源运行。结果,基于LED的灯具包括能够操控大的AC并且将它转换成DC电压的LED驱动器。LED驱动器通常由硅器件制成,诸如横向扩散金属氧化物半导体(LDMOS)或者功率金属氧化物半导体场效应晶体管(MOSFET)。
发明内容
在本公开的一个或多个实施例中,一种用于制造外延结构的方法包括提供衬底和在衬底的第一侧上的异质结堆叠,以及在衬底的第二侧上形成GaN发光二极管堆叠。异质结堆叠包括衬底的第一侧之上的无掺杂氮化镓(GaN)层和无掺杂GaN层上的掺杂氮化铝镓(AlGaN)层。GaN发光二极管堆叠包括衬底的第二侧之上的n型GaN层、n型GaN层之上的GaN/氮化铟镓(InGaN)多量子阱(MQW)结构、n型GaN/InGaN MQW结构之上的p型AlGaN层,以及p型AlGaN层之上的p型GaN层。
附图说明
在附图中:
图1是用于将氮化镓(GaN)发光二极管(LED)与氮化铝镓(AlGaN)/GaN器件集成在硅衬底上的外延结构的截面视图;
图2是用于将GaN LED与AlGaN/GaN器件集成在蓝宝石衬底上的外延结构的截面视图;
图3是用于将GaN LED与AlGaN/GaN器件集成在碳化硅(SiC)衬底上的外延结构的截面视图;
图4是用于将GaN LED与AlGaN/GaN器件集成在GaN衬底上的外延结构的截面视图;
图5示出了由经受形成AlGaN/GaN异质结场效应晶体管(HFET)和AlGaN/GaN肖特基二极管的附加处理的图2的结构导致的结构的截面视图;
图6是与LED串联连接的桥式整流器电路的电路图;以及
图7示出了所有根据本发明的实施例设置的由经受形成图6的桥式整流器电路的附加处理的图2的结构导致的结构的截面视图。
在不同附图中的相同参考数字的使用指示类似或者相同的元件。
具体实施方式
由于氮化镓(GaN)具有比硅(Si)更高的带隙,GaN晶体管具有比Si晶体管高得多的击穿电压,因此GaN晶体管可以操控高得多的电压和电流密度。这允许较小的GaN晶体管操控与较大的基于Si的功率晶体管相同的电压。随着Si上GaN(GaN-on-Si)技术的出现,生长在150mm(6英寸)硅衬底上的GaN晶体管与基于硅的功率器件相比具有价格竞争力并且提供更好的性能。通过将GaN发光二极管(LED)与GaN晶体管集成在硅衬底上,组合架构将比将GaN LED与分立的基于Si的电驱动器配对的常规方法更经济并且具有更高的AC-DC转换效率。
根据本公开的实施例,通过在衬底的一侧上形成GaN LED并且在衬底的另一侧上形成氮化铝镓(AlGaN)/GaN器件(或者反之亦然)来制作外延结构。AlGaN/GaN器件可以是异质结场效应晶体管(HFET)和肖特基二极管,其被用于AC-DC转换或者DC-DC向下转换(高电压到低电压转换)。若干LED和AlGaN/GaN器件可以取决于转换方案而串联或者并联连接。
注意,“在……之上”的使用包括在另一层或者层的堆叠上直接形成一层或层的堆叠。取决于结构位于衬底的顶侧还是背侧上,“在……之上”可以分别指示另一层或者层的堆叠上方或者下方的一层或者层的堆叠。可以可互换地使用术语堆叠或者层的堆叠。
图1是在本公开的一个或多个实施例中的用于将GaN LED与AlGaN/GaN器件集成在硅(Si)衬底102上的外延结构100的截面视图。由于归因于Ga和Si形成破坏Si衬底的共晶材料这一事实,GaN并不良好地适于Si衬底上的直接外延生长,因此无掺杂氮化铝(AlN)缓冲层104首先形成在硅衬底102的第一侧105(例如,如所示的顶侧)之上以充当GaN与硅之间的阻挡。薄AlN缓冲层104(例如,100埃至2微米)被用于降低缺陷密度。无掺杂AlxGa1-xN层106可以形成在无掺杂AlN缓冲层104之上以在Si与GaN之间提供附加的分离。
应变改造堆叠108可以形成在AlxGa1-xN层106之上。应变改造堆叠108调节由于结构100中的Si与GaN之间的热膨胀差异所致的应变。应变改造堆叠108包括无掺杂或者掺杂GaN层110和GaN层110之上的无掺杂或者掺杂AlN应变释放层112。堆叠108的GaN层110直接形成在AlxGa1-xN层106之上。第二应变改造堆叠108A(未示出)可以形成在第一改造堆叠108之上。
无掺杂GaN层114形成在应变改造堆叠108的AlN应变释放层112之上以将应变改造堆叠108从AlGaN/GaN异质结堆叠116分离。可替换地,GaN层114可以掺杂有诸如铁(Fe)之类的n型掺杂剂以增加它的电阻。GaN层114是非导电层,其在HFET断开时防止来自形成在GaN层114上方的AlGaN/GaN异质结堆叠116(稍后描述)中的任何HFET的横向漏电流。隔离沟槽可以向下蚀刻到GaN层114以使形成在GaN层114上方的器件电绝缘。
AlGaN/GaN异质结堆叠116形成在GaN层114之上。AlGaN/GaN异质结堆叠116包括无掺杂GaN层118、无掺杂GaN层118上的重掺杂n型AlxGa1-xN层120以及n型AlxGa1-xN层120之上的钝化层122(例如,n型GaN)。异质结堆叠116的无掺杂GaN层118直接在GaN层114之上。AlGaN/GaN异质结堆叠116可以被进一步处理以形成包括HFET和肖特基二极管的器件。附加的电路元件可以与AlGaN/GaN异质结堆叠116集成或者构建在AlGaN/GaN异质结堆叠116之上的层中。例如,可以利用AlGaN/GaN异质结堆叠116的半导体层(例如,GaN层118)通过在它们之间的某个距离处形成两个金属接触来制作电阻器。而且,电容器可以由沉积在AlGaN/GaN异质结堆叠116上方并且夹在两个金属层之间的介电层(二氧化硅或者氮化硅)制成,并且电感器可以通过在AlGaN/GaN异质结堆叠116的半导体层(例如,GaN层118)顶上形成长缠绕金属图案来制成。
无掺杂AlN缓冲层124形成在硅衬底102的第二侧125之上以充当GaN与硅之间的阻挡层。无掺杂AlxGa1-xN层126形成在无掺杂AlN缓冲层124之上以提供归因于GaN与Si之间的热膨胀和晶格常数中的差异的应力释放。
应变改造堆叠128可以形成在无掺杂AlxGa1-xN层126之上。应变改造堆叠128包括无掺杂GaN层130和无掺杂GaN层130之上的无掺杂AlN应变释放层132。堆叠128的无掺杂GaN层130直接在AlxGa1-xN层126之上。可以在另一改造堆叠128之上重复应变改造堆叠128的结构。
GaN LED堆叠134形成在应变改造堆叠128的无掺杂AlN应变释放层132之上。GaNLED堆叠134包括n型GaN层136、n型GaN层136之上的GaN/InyGa1-yN多量子阱(MQW)层138、GaN/InyGa1-yN MQW层138之上的p型AlxGa1-xN层140以及p型AlxGa1-xN层140之上的p型GaN层142。注意,不同层中的AlxGa1-xN和InyGa1-yN可以具有不同的组成并且可以一般被分别指示为AlGaN和InGaN。堆叠134的N型GaN层136直接在无掺杂AlN应变释放层132之上。GaN LED堆叠134可以被进一步处理到n型GaN层136和p型GaN层142的暴露区域以用于形成n接触和p接触。附加的电路元件可以与GaN LED堆叠134集成或者构建在GaN LED堆叠134之上的层中。
注意,GaN LED堆叠134不像异质结堆叠116那样形成在非导电GaN层之上,因为LED是竖直器件,所以横向漏电流不是大的关注点。
图2是在本公开的一个或多个实施例中的用于将GaN LED与AlGaN/GaN器件集成在蓝宝石衬底202上的外延结构200的截面视图。无掺杂缓冲层204首先形成在蓝宝石衬底202的第一侧205(例如,如所示的顶侧)之上以提供用于生长其它层的种子。无掺杂缓冲层204可能包括GaN或者AlN。无掺杂GaN层206接下来形成在无掺杂缓冲层204上。可替换地,GaN层206可以掺杂有诸如Fe之类的n型掺杂剂以增加它的电阻。GaN层206是非导电的,因此当HFET被断开时它防止来自层上方的任何HFET器件的横向漏电流。隔离沟槽可以向下蚀刻到GaN层206以使形成在层上方的器件电绝缘。
(早前描述的)AlGaN/GaN异质结堆叠116形成在GaN层206之上。异质结堆叠116的无掺杂GaN层118直接在GaN层206之上。AlGaN/GaN异质结堆叠116可以被进一步处理以形成包括HFET和肖特基二极管的器件。附加的电路元件可以与AlGaN/GaN异质结堆叠116集成或者构建在AlGaN/GaN异质结堆叠116之上的层中。
无掺杂成核层208形成在蓝宝石衬底202的第二侧209(例如,如所示的背侧)之上以播种其它层。无掺杂成核层208可以包括GaN或者AlN。(早前描述的)GaN LED堆叠134形成在无掺杂成核层208之上。堆叠134的N型GaN层136直接在无掺杂成核层208之上。GaN LED堆叠134可以被进一步处理到n型GaN层136和p型GaN层142的暴露区域以用于形成n接触和p接触。附加的电路元件可以与GaN LED堆叠134集成或者构建在GaN LED堆叠134之上的层中。
图3是在本公开的一个或多个实施例中的用于将GaN LED与AlGaN/GaN器件集成在碳化硅(SiC)衬底302上的外延结构300的截面视图。无掺杂成核层304首先形成在SiC衬底302的第一侧305(例如,如所示的顶侧)之上以播种其它层。无掺杂成核层304可以包括AlN或者AlxGa1-xN。无掺杂GaN层306然后形成在无掺杂成核层304上。可替换地,GaN层306可以掺杂有诸如Fe之类的n型掺杂剂以增加它的电阻。GaN层306是非导电的,因此当HFET被断开时它防止来自层上方的任何HFET器件的横向漏电流。隔离沟槽可以向下蚀刻到GaN层306以使形成在层上方的器件电绝缘。
(早前描述的)AlGaN/GaN异质结堆叠116形成在GaN层306之上。异质结堆叠116的无掺杂GaN层118直接在GaN层306之上。AlGaN/GaN异质结堆叠116可以被进一步处理以形成包括HFET和肖特基二极管的器件。附加的电路元件可以与AlGaN/GaN异质结堆叠116集成或者构建在AlGaN/GaN异质结堆叠116之上的层中。
无掺杂成核层308形成在SiC衬底302的第二侧(例如,如所示的背侧)309之上以播种其它层。无掺杂成核层308可以包括AlN或者AlxGa1-xN。(早前描述的)GaN LED堆叠134形成在无掺杂成核层308之上。堆叠134的n型GaN层136直接在无掺杂成核层308之上。GaN LED堆叠134可以被进一步处理以使n型GaN层136和p型GaN层142的区域暴露以用于形成n接触和p接触。附加的电路元件可以与GaN LED堆叠134集成或者构建在GaN LED堆叠134之上的层中。
图4是在本公开的一个或多个实施例中的用于将GaN LED与AlGaN/GaN器件集成在GaN衬底402上的外延结构400的截面视图。无掺杂GaN层404可以形成在GaN衬底402的第一侧405(例如,如所示的顶侧)上。可替换地,GaN层404可以掺杂有诸如Fe之类的掺杂剂以增加它的电阻。GaN层404是非导电的,因此当HFET被断开时它防止来自层上方的任何HFET器件的横向漏电流。隔离沟槽可以向下蚀刻到GaN层404以使形成在层上方的器件电绝缘。
(早前描述的)AlGaN/GaN异质结堆叠116形成在GaN层404之上。异质结堆叠116的无掺杂GaN层118直接在GaN层404之上。AlGaN/GaN异质结堆叠116可以被进一步处理以形成包括HFET和肖特基二极管的器件。附加的电路元件可以与AlGaN/GaN异质结堆叠116集成或者构建在AlGaN/GaN异质结堆叠116之上的层中。
(早前描述的)GaN LED堆叠134形成在GaN衬底402的第二侧406(例如,如所示的背侧)上。堆叠134的n型GaN层136直接在GaN衬底402之上。GaN LED堆叠134可以被进一步处理到n型GaN层136和p型GaN层142的暴露区域以用于形成n接触和p接触。附加的电路元件可以与GaN LED堆叠134集成或者构建在GaN LED堆叠134之上的层中。
图5示出了在本公开的一个或多个实施例中的由经受形成AlGaN/GaN HFET 506和AlGaN/GaN肖特基二极管508的附加处理的结构200(图2)导致的结构500的截面视图。
GaN LED堆叠134中的p型GaN层142可以被粗糙化以改进光提取。p接触501形成在p型GaN层142上。结构200(图2)的一个或多个部分被向下移除到n型GaN层136中以形成用于GaN LED堆叠134中的LED的n接触502。在替换方案中,可以移除层116、206、204、202和208的部分以形成n接触502。在又一替换方案中,可以移除层206、204、202、208以及除p型GaN层142之外的GaN LED堆叠134的所有层以形成p接触501。使所有接触位于器件的一侧上使得能够实现倒装芯片配置。
隔离沟槽504穿过AlGaN/GaN异质结堆叠116、GaN层206以及GaN或AlN缓冲层204向下蚀刻到蓝宝石衬底202以使HFET 506和肖特基二极管508电绝缘。HFET 506和肖特基二极管508通过互连(未示出)连接以形成用于GaN LED堆叠134中的LED的驱动器电路。诸如电阻器、电容器和电感器之类的其它电路元件也可以形成在AlGaN/GaN异质结堆叠116中。
HFET 506包括栅极512以及栅极512的相对侧上的源极514和漏极516。栅极512接触n型AlxGa1-xN层120,并且源极514和漏极516接触无掺杂GaN层118。对于栅极512,在n型GaN钝化层122中蚀刻开口,并且在n型AlxGa1-xN层120上沉积金属。对于源极514和漏极516,金属被沉积在n型GaN钝化层122上并且通过退火向下扩散到无掺杂GaN层118。
肖特基二极管508包括阳极电极518和阴极电极520。阳极电极518接触n型AlxGa1- xN层120。为了形成阳极电极518,在n型GaN钝化层122中蚀刻开口并且在n型AlxGa1-xN层120上沉积金属。阴极电极520接触无掺杂GaN层118。为了形成阴极电极520,金属被沉积在n型GaN钝化层122上并且通过退火向下扩散到无掺杂GaN层118。
图6是连接到LED 604的桥式整流器电路602的电路图。在本公开的一个或多个实施例中,桥式整流器电路602将AC电压供给转换成DC电压以便向LED供电。电路602包括以典型的菱形配置设置的二极管D1、D2、D3和D4,其中二极管D1的阴极连接到二极管D2的阳极和AC供给电压的一侧,二极管D4的阴极连接到二极管D3的阳极和AC供给电压的另一侧。二极管D1和D4的阳极是用于LED 604的整流供给电压的负侧并且连接到LED 604的阴极。二极管D2和D3的阴极是整流电压的正侧并且连接到LED 604的阳极。
图7示出了在本公开的一个或多个实施例中的由经受形成桥式整流器电路602(图6)的附加处理的结构200(图2)导致的结构700的截面视图。电路602中的每个二极管实现为异质结堆叠116中的AlGaN/GaN肖特基二极管。二极管D1包括阳极电极702和阴极电极704。二极管D2具有阳极电极706并且与二极管D3共享阴极电极708,因为它们通过无掺杂GaN层118串联连接。二极管D3具有阳极电极710和阴极电极708。二极管D4具有阳极电极712和阴极电极714。每个阳极电极接触n型AlxGa1-xN层120,并且每个阴极电极接触无掺杂GaN层118。二极管D1、D2、D3和D4通过针对形成结构500(图5)中的二极管508所描述的方法来形成。
部分的AlGaN/GaN异质结堆叠116、GaN层206以及GaN或AlN缓冲层204被移除以使蓝宝石衬底202的区域暴露。在一个暴露区域中,n接触722通过以下形成:蚀刻穿过蓝宝石衬底202和GaN或AlN缓冲层208并且部分地到GaN LED堆叠134中的n型GaN层136中的开口,并且在开口中沉积金属。在另一暴露区域中,p接触726通过以下形成:蚀刻穿过蓝宝石衬底202、GaN或AlN缓冲层208以及GaN LED堆叠134的孔,并且在孔中沉积金属以接触GaN LED堆叠134中的p型GaN层142。尽管未示出,但是用于n接触722和p接触726的孔的侧壁覆盖有诸如氧化物之类的绝缘体。在可替换的实施例中,用于n接触722和p接触726的开口每个都足够宽以允许沉积金属柱而不接触开口的“侧面”。在另一替换方案中,p型GaN层142的一部分留在开口的底部处,并且p接触726沉积在p型GaN层142的非粗糙化表面上。在该最后的实施例中,不存在阻碍来自由GaN LED堆叠134形成的LED的任何光的p接触。
二极管D1、二极管D2、D3和二极管D4通过隔离沟槽716从彼此电绝缘。隔离沟槽716穿过AlGaN/GaN异质结堆叠116、GaN层206和GaN或AlN缓冲层204向下蚀刻到蓝宝石衬底202以使二极管D1、二极管D2、D3对和D4从彼此电绝缘。互连连接二极管D1、D2、D3和D4,如图6中所示。具体地,互连将阴极电极708(D2和D3的阴极)连接到GaN LED堆叠126中的LED的p接触726(阳极),并且将阳极电极702和712连接到GaN LED堆叠134中的LED的n接触722(阴极)。AC电压的一侧被供给到二极管D1的阴极电极704以及二极管D2的阳极电极706。AC电压的另一侧被供给到二极管D3的阳极电极710以及二极管D4的阴极电极714。
本公开的实施例提供了超过常规基于LED的灯具的以下优点。本公开的实施例将LED与LED驱动器电路集成在相同衬底模板上。将利用金属互连在圆片级上集成器件来取代于分离地制作分立的LED和LED驱动器电路并且然后在管芯级上将它们进行组合的常规方法。
本公开的实施例改进了AC-DC转换效率。GaN晶体管开关具有比基于Si的器件更低的特征导通电阻,这提供了由于开关操作的较少的欧姆损耗。
本公开的实施例具有较小的占用空间(footprint)。GaN晶体管可以操控比基于Si的器件更高的操作电压,因此开关晶体管可以制作得更小。必要的电容器或者电感器也可以在圆片级上制作,因此减小了总面积。
本公开的实施例更经济。在LED驱动器电路与LED之间不再需要诸如引线键合和焊接之类的管芯级互连,因为现在它们在圆片级上完成。
本公开的实施例提供了较好的温度稳定性并且防止热逸散。LED电流当以恒定电压被驱动时往往具有正温度系数,因为当LED变热时,LED的开启电压变得较小。相比之下,由于当FET变热时载流子迁移率中的下降,场效应晶体管(FET)往往具有负温度系数。通过将LED和LED驱动器电路放置在相同衬底上,温度效应得以自补偿,从而防止热逸散。
本公开的实施例对于LED公司而言允许较容易的制造。LED公司可以从其它公司获取具有生长在Si、蓝宝石或者SiC衬底上的AlGaN/GaN晶体管结构的外延圆片并且集中在改进衬底的另一侧上的LED结构上而不用烦恼优化晶体管结构的问题。另外,LED结构的厚度将不会干扰生长在衬底的另一侧上的晶体管结构。换言之,LED和晶体管的圆片处理不会彼此严重影响。
所公开的实施例的特征的各种其它适配和组合在本发明的范围之内。以下权利要求涵盖大量的实施例。
Claims (15)
1.一种用于制造外延结构的方法,包括:
提供衬底和衬底的第一侧之上的异质结堆叠,异质结堆叠包括衬底的第一侧之上的无掺杂氮化镓(GaN)层和无掺杂GaN层上的掺杂氮化铝镓(AlGaN)层;以及
在衬底的第二侧之上形成GaN发光二极管堆叠,GaN发光二极管堆叠包括衬底的第二侧之上的n型GaN层、n型GaN层之上的n型GaN/氮化铟镓(InGaN)多量子阱(MQW)结构、n型GaN/InGaN MQW结构之上的p型AlGaN层,以及p型AlGaN层之上的p型GaN层,
处理异质结堆叠以形成耦合到发光二极管堆叠的一个或多个器件,一个或多个器件选择形成包括AlGaN/GaN异质结场效应晶体管(HFET)和AlGaN/GaN肖特基二极管的组。
2.权利要求1所述的方法,其中:
衬底是硅衬底;
提供衬底和衬底的第一侧之上的异质结堆叠包括:
在衬底的第一侧之上形成第一应变改造堆叠,第一应变改造堆叠调节硅与GaN之间的应变;以及
在第一应变改造堆叠之上形成异质结堆叠;并且
所述方法还包括在衬底的第二侧之上形成第二应变改造堆叠,GaN发光二极管堆叠形成在第二应变改造堆叠之上,
其中:
第一应变改造堆叠包括:
衬底的第一侧之上的第一GaN层;以及
第一GaN层上的第一氮化铝(AlN)应变释放层;并且
第二应变改造堆叠包括:
衬底的第二侧之上的第二GaN层;以及
第二GaN层上的第二AlN应变释放层。
3.权利要求2所述的方法,还包括:
在衬底的第一侧之上形成第一无掺杂AlN缓冲层;以及
在第一无掺杂AlN缓冲层之上形成第一无掺杂AlGaN层,其中第一应变改造堆叠形成在第一无掺杂AlGaN层之上;
在衬底的第二侧之上形成第二无掺杂AlN缓冲层;以及
在第二无掺杂AlN缓冲层之上形成第二无掺杂AlGaN层,其中第二应变改造堆叠形成在第二无掺杂AlGaN层之上。
4.权利要求3所述的方法,还包括在第一应变改造堆叠与异质结堆叠之间,形成非导电GaN层。
5.权利要求1所述的方法,其中衬底包括蓝宝石衬底,所述方法还包括:
在衬底的第一侧之上形成第一GaN或者AlN成核层;
在GaN或者AlN成核层之上形成非导电GaN层,其中异质结堆叠形成在非导电GaN层之上;以及
在衬底的第二侧之上形成第二GaN或者AlN成核层,其中GaN发光二极管堆叠形成在第二GaN或者AlN缓冲层之上。
6.权利要求1所述的方法,其中衬底包括碳化硅(SiC)衬底,所述方法还包括:
在衬底的第一侧之上形成第一AlN或者AlGaN成核层;
在第一AlN或者AlGaN缓冲层之上形成非导电GaN层,异质结堆叠形成在非导电GaN层之上;以及
在衬底的第二侧之上形成第二AlN或者AlGaN成核层,GaN发光二极管堆叠形成在第二AlN或者AlGaN成核层之上。
7.权利要求1所述的方法,其中衬底包括GaN衬底,所述方法还包括在衬底的第一侧之上形成非导电GaN层,异质结堆叠形成在非导电GaN层之上。
8.权利要求1所述的方法,其中所述处理异质结堆叠包括:
形成接触无掺杂GaN层的用于AlGaN/GaN HFET的源极;
形成接触无掺杂GaN层的用于AlGaN/GaN HFET的漏极;
形成接触掺杂AlGaN层的用于AlGaN/GaN HFET的栅极;
形成接触掺杂AlGaN层的用于AlGaN/GaN肖特基二极管的阳极;以及
形成接触无掺杂GaN层的用于AlGaN/GaN肖特基二极管的阴极。
9.一种外延结构,包括:
衬底;
衬底的第一侧之上的异质结堆叠,异质结堆叠包括衬底的第一侧之上的无掺杂GaN层和无掺杂GaN层上的掺杂AlGaN层;以及
衬底的第二侧之上的GaN发光二极管堆叠,GaN发光二极管堆叠包括衬底的第二侧之上的n型GaN层、n型GaN层之上的n型GaN/InGaN MQW结构、n型GaN/InGaN MQW结构之上的p型AlGaN层,以及p型AlGaN层之上的p型GaN层
其中异质结堆叠包括耦合到发光二极管堆叠的一个或多个器件,一个或多个器件包括AlGaN/GaN异质结场效应晶体管(HFET)和AlGaN/GaN肖特基二极管中的一个或多个
其中器件中的至少一个连接到GaN发光二极管堆叠。
10.权利要求9所述的结构,其中衬底是硅衬底,所述结构还包括:
衬底的第一侧之上的第一应变改造堆叠,第一应变改造堆叠调节硅与GaN之间的应变,异质结堆叠在第一应变改造堆叠之上;以及
衬底的第二侧之上的第二应变改造堆叠,GaN发光二极管堆叠在第二应变改造堆叠之上
其中:
第一应变改造堆叠包括:
衬底的第一侧之上的第一GaN层;以及
第一GaN层上的第一氮化铝(AlN)应变释放层;并且
第二应变改造堆叠包括:
衬底的第二侧之上的第二GaN层;以及
第二GaN层上的第二AlN应变释放层。
11.权利要求9所述的结构,还包括:
衬底的第一侧之上的第一无掺杂AlN缓冲层;以及
第一无掺杂AlN缓冲层之上的第一无掺杂AlGaN层,第一应变改造堆叠在第一无掺杂AlGaN层之上;
衬底的第二侧之上的第二无掺杂AlN缓冲层;
第二无掺杂AlN缓冲层之上的第二无掺杂AlGaN层,GaN发光二极管堆叠在第二无掺杂AlGaN层之上;以及
第一应变改造堆叠之上的非导电GaN层,异质结堆叠在第一非导电GaN层之上。
12.权利要求9所述的结构,其中衬底包括蓝宝石衬底,所述结构还包括:
衬底的第一侧之上的第一GaN或者AlN成核层;第一GaN或者AlN成核层之上的非导电GaN层,异质结堆叠在非导电GaN层之上;以及
衬底的第二侧之上的第二GaN或者AlN成核层,GaN发光二极管堆叠在第二GaN或者AlN成核层之上。
13.权利要求9所述的结构,其中衬底包括SiC衬底,所述结构还包括:
衬底的第一侧之上的第一AlN或者AlGaN成核层;
第一AlN或者AlGaN成核层之上的非导电GaN层,异质结堆叠在非导电GaN层之上;以及
衬底的第二侧之上的第二AlN或者AlGaN成核层,GaN发光二极管堆叠在第二AlN或者AlGaN成核层之上。
14.权利要求9所述的结构,其中衬底包括GaN衬底,所述结构还包括衬底的第一侧之上的非导电GaN层,异质结堆叠在非导电GaN层之上。
15.权利要求9所述的结构,其中异质结堆叠包括:
接触无掺杂GaN层的用于AlGaN/GaN HFET的源极;
接触无掺杂GaN层的用于AlGaN/GaN HFET的漏极;
接触掺杂AlGaN层的用于AlGaN/GaN HFET的栅极;
接触掺杂AlGaN层的用于AlGaN/GaN肖特基二极管的阳极;以及
接触无掺杂GaN层的用于AlGaN/GaN肖特基二极管的阴极。
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